arch/mips/pci/pci-xlr.c

   1 /*
   2  * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   3  * reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the NetLogic
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/types.h>
  36 #include <linux/pci.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/msi.h>
  40 #include <linux/mm.h>
  41 #include <linux/irq.h>
  42 #include <linux/irqdesc.h>
  43 #include <linux/console.h>
  44
  45 #include <asm/io.h>
  46
  47 #include <asm/netlogic/interrupt.h>
  48 #include <asm/netlogic/xlr/msidef.h>
  49 #include <asm/netlogic/xlr/iomap.h>
  50 #include <asm/netlogic/xlr/pic.h>
  51 #include <asm/netlogic/xlr/xlr.h>
  52
  53 static void *pci_config_base;
  54
  55 #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
  56
  57 /* PCI ops */
  58 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  59         int where)
  60 {
  61         u32 data;
  62         u32 *cfgaddr;
  63
  64         cfgaddr = (u32 *)(pci_config_base +
  65                         pci_cfg_addr(bus->number, devfn, where & ~3));
  66         data = *cfgaddr;
  67         return cpu_to_le32(data);
  68 }
  69
  70 static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  71         int where, u32 data)
  72 {
  73         u32 *cfgaddr;
  74
  75         cfgaddr = (u32 *)(pci_config_base +
  76                         pci_cfg_addr(bus->number, devfn, where & ~3));
  77         *cfgaddr = cpu_to_le32(data);
  78 }
  79
  80 static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  81         int where, int size, u32 *val)
  82 {
  83         u32 data;
  84
  85         if ((size == 2) && (where & 1))
  86                 return PCIBIOS_BAD_REGISTER_NUMBER;
  87         else if ((size == 4) && (where & 3))
  88                 return PCIBIOS_BAD_REGISTER_NUMBER;
  89
  90         data = pci_cfg_read_32bit(bus, devfn, where);
  91
  92         if (size == 1)
  93                 *val = (data >> ((where & 3) << 3)) & 0xff;
  94         else if (size == 2)
  95                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  96         else
  97                 *val = data;
  98
  99         return PCIBIOS_SUCCESSFUL;
 100 }
 101
 102
 103 static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 104                 int where, int size, u32 val)
 105 {
 106         u32 data;
 107
 108         if ((size == 2) && (where & 1))
 109                 return PCIBIOS_BAD_REGISTER_NUMBER;
 110         else if ((size == 4) && (where & 3))
 111                 return PCIBIOS_BAD_REGISTER_NUMBER;
 112
 113         data = pci_cfg_read_32bit(bus, devfn, where);
 114
 115         if (size == 1)
 116                 data = (data & ~(0xff << ((where & 3) << 3))) |
 117                         (val << ((where & 3) << 3));
 118         else if (size == 2)
 119                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 120                         (val << ((where & 3) << 3));
 121         else
 122                 data = val;
 123
 124         pci_cfg_write_32bit(bus, devfn, where, data);
 125
 126         return PCIBIOS_SUCCESSFUL;
 127 }
 128
 129 struct pci_ops nlm_pci_ops = {
 130         .read  = nlm_pcibios_read,
 131         .write = nlm_pcibios_write
 132 };
 133
 134 static struct resource nlm_pci_mem_resource = {
 135         .name           = "XLR PCI MEM",
 136         .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
 137         .end            = 0xdfffffffUL,
 138         .flags          = IORESOURCE_MEM,
 139 };
 140
 141 static struct resource nlm_pci_io_resource = {
 142         .name           = "XLR IO MEM",
 143         .start          = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
 144         .end            = 0x100fffffUL,
 145         .flags          = IORESOURCE_IO,
 146 };
 147
 148 struct pci_controller nlm_pci_controller = {
 149         .index          = 0,
 150         .pci_ops        = &nlm_pci_ops,
 151         .mem_resource   = &nlm_pci_mem_resource,
 152         .mem_offset     = 0x00000000UL,
 153         .io_resource    = &nlm_pci_io_resource,
 154         .io_offset      = 0x00000000UL,
 155 };
 156
 157 static int get_irq_vector(const struct pci_dev *dev)
 158 {
 159         if (!nlm_chip_is_xls())
 160                 return  PIC_PCIX_IRQ;   /* for XLR just one IRQ*/
 161
 162         /*
 163          * For XLS PCIe, there is an IRQ per Link, find out which
 164          * link the device is on to assign interrupts
 165         */
 166         if (dev->bus->self == NULL)
 167                 return 0;
 168
 169         switch  (dev->bus->self->devfn) {
 170         case 0x0:
 171                 return PIC_PCIE_LINK0_IRQ;
 172         case 0x8:
 173                 return PIC_PCIE_LINK1_IRQ;
 174         case 0x10:
 175                 if (nlm_chip_is_xls_b())
 176                         return PIC_PCIE_XLSB0_LINK2_IRQ;
 177                 else
 178                         return PIC_PCIE_LINK2_IRQ;
 179         case 0x18:
 180                 if (nlm_chip_is_xls_b())
 181                         return PIC_PCIE_XLSB0_LINK3_IRQ;
 182                 else
 183                         return PIC_PCIE_LINK3_IRQ;
 184         }
 185         WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
 186         return 0;
 187 }
 188
 189 #ifdef CONFIG_PCI_MSI
 190 void destroy_irq(unsigned int irq)
 191 {
 192             /* nothing to do yet */
 193 }
 194
 195 void arch_teardown_msi_irq(unsigned int irq)
 196 {
 197         destroy_irq(irq);
 198 }
 199
 200 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 201 {
 202         struct msi_msg msg;
 203         int irq, ret;
 204
 205         irq = get_irq_vector(dev);
 206         if (irq <= 0)
 207                 return 1;
 208
 209         msg.address_hi = MSI_ADDR_BASE_HI;
 210         msg.address_lo = MSI_ADDR_BASE_LO   |
 211                 MSI_ADDR_DEST_MODE_PHYSICAL |
 212                 MSI_ADDR_REDIRECTION_CPU;
 213
 214         msg.data = MSI_DATA_TRIGGER_EDGE |
 215                 MSI_DATA_LEVEL_ASSERT    |
 216                 MSI_DATA_DELIVERY_FIXED;
 217
 218         ret = irq_set_msi_desc(irq, desc);
 219         if (ret < 0) {
 220                 destroy_irq(irq);
 221                 return ret;
 222         }
 223
 224         write_msi_msg(irq, &msg);
 225         return 0;
 226 }
 227 #endif
 228
 229 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 230 {
 231         return get_irq_vector(dev);
 232 }
 233
 234 /* Do platform specific device initialization at pci_enable_device() time */
 235 int pcibios_plat_dev_init(struct pci_dev *dev)
 236 {
 237         return 0;
 238 }
 239
 240 static int __init pcibios_init(void)
 241 {
 242         /* PSB assigns PCI resources */
 243         pci_probe_only = 1;
 244         pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 245
 246         /* Extend IO port for memory mapped io */
 247         ioport_resource.start =  0;
 248         ioport_resource.end   = ~0;
 249
 250         set_io_port_base(CKSEG1);
 251         nlm_pci_controller.io_map_base = CKSEG1;
 252
 253         pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
 254         register_pci_controller(&nlm_pci_controller);
 255
 256         return 0;
 257 }
 258
 259 arch_initcall(pcibios_init);
 260
 261 struct pci_fixup pcibios_fixups[] = {
 262         {0}
 263 };