arch/mips/pci/pci.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
   8  */
   9 #include <linux/kernel.h>
  10 #include <linux/mm.h>
  11 #include <linux/bootmem.h>
  12 #include <linux/export.h>
  13 #include <linux/init.h>
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16
  17 /*
  18  * Indicate whether we respect the PCI setup left by the firmware.
  19  *
  20  * Make this long-lived  so that we know when shutting down
  21  * whether we probed only or not.
  22  */
  23 int pci_probe_only;
  24
  25 #define PCI_ASSIGN_ALL_BUSSES   1
  26
  27 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
  28
  29 /*
  30  * The PCI controller list.
  31  */
  32
  33 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  34
  35 unsigned long PCIBIOS_MIN_IO;
  36 unsigned long PCIBIOS_MIN_MEM;
  37
  38 static int pci_initialized;
  39
  40 /*
  41  * We need to avoid collisions with `mirrored' VGA ports
  42  * and other strange ISA hardware, so we always want the
  43  * addresses to be allocated in the 0x000-0x0ff region
  44  * modulo 0x400.
  45  *
  46  * Why? Because some silly external IO cards only decode
  47  * the low 10 bits of the IO address. The 0x00-0xff region
  48  * is reserved for motherboard devices that decode all 16
  49  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  50  * but we want to try to avoid allocating at 0x2900-0x2bff
  51  * which might have be mirrored at 0x0100-0x03ff..
  52  */
  53 resource_size_t
  54 pcibios_align_resource(void *data, const struct resource *res,
  55                        resource_size_t size, resource_size_t align)
  56 {
  57         struct pci_dev *dev = data;
  58         struct pci_controller *hose = dev->sysdata;
  59         resource_size_t start = res->start;
  60
  61         if (res->flags & IORESOURCE_IO) {
  62                 /* Make sure we start at our min on all hoses */
  63                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  64                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  65
  66                 /*
  67                  * Put everything into 0x00-0xff region modulo 0x400
  68                  */
  69                 if (start & 0x300)
  70                         start = (start + 0x3ff) & ~0x3ff;
  71         } else if (res->flags & IORESOURCE_MEM) {
  72                 /* Make sure we start at our min on all hoses */
  73                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  74                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  75         }
  76
  77         return start;
  78 }
  79
  80 static void __devinit pcibios_scanbus(struct pci_controller *hose)
  81 {
  82         static int next_busno;
  83         static int need_domain_info;
  84         struct pci_bus *bus;
  85
  86         if (!hose->iommu)
  87                 PCI_DMA_BUS_IS_PHYS = 1;
  88
  89         if (hose->get_busno && pci_probe_only)
  90                 next_busno = (*hose->get_busno)();
  91
  92         bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
  93         hose->bus = bus;
  94
  95         need_domain_info = need_domain_info || hose->index;
  96         hose->need_domain_info = need_domain_info;
  97         if (bus) {
  98                 next_busno = bus->subordinate + 1;
  99                 /* Don't allow 8-bit bus number overflow inside the hose -
 100                    reserve some space for bridges. */
 101                 if (next_busno > 224) {
 102                         next_busno = 0;
 103                         need_domain_info = 1;
 104                 }
 105
 106                 if (!pci_probe_only) {
 107                         pci_bus_size_bridges(bus);
 108                         pci_bus_assign_resources(bus);
 109                         pci_enable_bridges(bus);
 110                 }
 111         }
 112 }
 113
 114 static DEFINE_MUTEX(pci_scan_mutex);
 115
 116 void __devinit register_pci_controller(struct pci_controller *hose)
 117 {
 118         if (request_resource(&iomem_resource, hose->mem_resource) < 0)
 119                 goto out;
 120         if (request_resource(&ioport_resource, hose->io_resource) < 0) {
 121                 release_resource(hose->mem_resource);
 122                 goto out;
 123         }
 124
 125         *hose_tail = hose;
 126         hose_tail = &hose->next;
 127
 128         /*
 129          * Do not panic here but later - this might happen before console init.
 130          */
 131         if (!hose->io_map_base) {
 132                 printk(KERN_WARNING
 133                        "registering PCI controller with io_map_base unset\n");
 134         }
 135
 136         /*
 137          * Scan the bus if it is register after the PCI subsystem
 138          * initialization.
 139          */
 140         if (pci_initialized) {
 141                 mutex_lock(&pci_scan_mutex);
 142                 pcibios_scanbus(hose);
 143                 mutex_unlock(&pci_scan_mutex);
 144         }
 145
 146         return;
 147
 148 out:
 149         printk(KERN_WARNING
 150                "Skipping PCI bus scan due to resource conflict\n");
 151 }
 152
 153 static int __init pcibios_init(void)
 154 {
 155         struct pci_controller *hose;
 156
 157         /* Scan all of the recorded PCI controllers.  */
 158         for (hose = hose_head; hose; hose = hose->next)
 159                 pcibios_scanbus(hose);
 160
 161         pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
 162
 163         pci_initialized = 1;
 164
 165         return 0;
 166 }
 167
 168 subsys_initcall(pcibios_init);
 169
 170 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 171 {
 172         u16 cmd, old_cmd;
 173         int idx;
 174         struct resource *r;
 175
 176         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 177         old_cmd = cmd;
 178         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
 179                 /* Only set up the requested stuff */
 180                 if (!(mask & (1<<idx)))
 181                         continue;
 182
 183                 r = &dev->resource[idx];
 184                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 185                         continue;
 186                 if ((idx == PCI_ROM_RESOURCE) &&
 187                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 188                         continue;
 189                 if (!r->start && r->end) {
 190                         printk(KERN_ERR "PCI: Device %s not available "
 191                                "because of resource collisions\n",
 192                                pci_name(dev));
 193                         return -EINVAL;
 194                 }
 195                 if (r->flags & IORESOURCE_IO)
 196                         cmd |= PCI_COMMAND_IO;
 197                 if (r->flags & IORESOURCE_MEM)
 198                         cmd |= PCI_COMMAND_MEMORY;
 199         }
 200         if (cmd != old_cmd) {
 201                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 202                        pci_name(dev), old_cmd, cmd);
 203                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 204         }
 205         return 0;
 206 }
 207
 208 /*
 209  *  If we set up a device for bus mastering, we need to check the latency
 210  *  timer as certain crappy BIOSes forget to set it properly.
 211  */
 212 static unsigned int pcibios_max_latency = 255;
 213
 214 void pcibios_set_master(struct pci_dev *dev)
 215 {
 216         u8 lat;
 217         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 218         if (lat < 16)
 219                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 220         else if (lat > pcibios_max_latency)
 221                 lat = pcibios_max_latency;
 222         else
 223                 return;
 224         printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
 225                pci_name(dev), lat);
 226         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 227 }
 228
 229 unsigned int pcibios_assign_all_busses(void)
 230 {
 231         return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
 232 }
 233
 234 int pcibios_enable_device(struct pci_dev *dev, int mask)
 235 {
 236         int err;
 237
 238         if ((err = pcibios_enable_resources(dev, mask)) < 0)
 239                 return err;
 240
 241         return pcibios_plat_dev_init(dev);
 242 }
 243
 244 static void pcibios_fixup_device_resources(struct pci_dev *dev,
 245         struct pci_bus *bus)
 246 {
 247         /* Update device resources.  */
 248         struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
 249         unsigned long offset = 0;
 250         int i;
 251
 252         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 253                 if (!dev->resource[i].start)
 254                         continue;
 255                 if (dev->resource[i].flags & IORESOURCE_IO)
 256                         offset = hose->io_offset;
 257                 else if (dev->resource[i].flags & IORESOURCE_MEM)
 258                         offset = hose->mem_offset;
 259
 260                 dev->resource[i].start += offset;
 261                 dev->resource[i].end += offset;
 262         }
 263 }
 264
 265 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 266 {
 267         /* Propagate hose info into the subordinate devices.  */
 268
 269         struct pci_controller *hose = bus->sysdata;
 270         struct list_head *ln;
 271         struct pci_dev *dev = bus->self;
 272
 273         if (!dev) {
 274                 bus->resource[0] = hose->io_resource;
 275                 bus->resource[1] = hose->mem_resource;
 276         } else if (pci_probe_only &&
 277                    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 278                 pci_read_bridge_bases(bus);
 279                 pcibios_fixup_device_resources(dev, bus);
 280         }
 281
 282         for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
 283                 dev = pci_dev_b(ln);
 284
 285                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 286                         pcibios_fixup_device_resources(dev, bus);
 287         }
 288 }
 289
 290 void __init
 291 pcibios_update_irq(struct pci_dev *dev, int irq)
 292 {
 293         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 294 }
 295
 296 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 297                          struct resource *res)
 298 {
 299         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 300         unsigned long offset = 0;
 301
 302         if (res->flags & IORESOURCE_IO)
 303                 offset = hose->io_offset;
 304         else if (res->flags & IORESOURCE_MEM)
 305                 offset = hose->mem_offset;
 306
 307         region->start = res->start - offset;
 308         region->end = res->end - offset;
 309 }
 310
 311 void __devinit
 312 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 313                         struct pci_bus_region *region)
 314 {
 315         struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
 316         unsigned long offset = 0;
 317
 318         if (res->flags & IORESOURCE_IO)
 319                 offset = hose->io_offset;
 320         else if (res->flags & IORESOURCE_MEM)
 321                 offset = hose->mem_offset;
 322
 323         res->start = region->start + offset;
 324         res->end = region->end + offset;
 325 }
 326
 327 #ifdef CONFIG_HOTPLUG
 328 EXPORT_SYMBOL(pcibios_resource_to_bus);
 329 EXPORT_SYMBOL(pcibios_bus_to_resource);
 330 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 331 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 332 #endif
 333
 334 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 335                         enum pci_mmap_state mmap_state, int write_combine)
 336 {
 337         unsigned long prot;
 338
 339         /*
 340          * I/O space can be accessed via normal processor loads and stores on
 341          * this platform but for now we elect not to do this and portable
 342          * drivers should not do this anyway.
 343          */
 344         if (mmap_state == pci_mmap_io)
 345                 return -EINVAL;
 346
 347         /*
 348          * Ignore write-combine; for now only return uncached mappings.
 349          */
 350         prot = pgprot_val(vma->vm_page_prot);
 351         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 352         vma->vm_page_prot = __pgprot(prot);
 353
 354         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 355                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 356 }
 357
 358 char * (*pcibios_plat_setup)(char *str) __devinitdata;
 359
 360 char *__devinit pcibios_setup(char *str)
 361 {
 362         if (pcibios_plat_setup)
 363                 return pcibios_plat_setup(str);
 364         return str;
 365 }