arch/mips/pci/pci.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 2011 Wind River Systems,
   9  *   written by Ralf Baechle (ralf@linux-mips.org)
  10  */
  11 #include <linux/bug.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/export.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/of_address.h>
  20
  21 #include <asm/cpu-info.h>
  22
  23 /*
  24  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
  25  * assignments.
  26  */
  27
  28 /*
  29  * The PCI controller list.
  30  */
  31
  32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  33
  34 unsigned long PCIBIOS_MIN_IO;
  35 unsigned long PCIBIOS_MIN_MEM;
  36
  37 static int pci_initialized;
  38
  39 /*
  40  * We need to avoid collisions with `mirrored' VGA ports
  41  * and other strange ISA hardware, so we always want the
  42  * addresses to be allocated in the 0x000-0x0ff region
  43  * modulo 0x400.
  44  *
  45  * Why? Because some silly external IO cards only decode
  46  * the low 10 bits of the IO address. The 0x00-0xff region
  47  * is reserved for motherboard devices that decode all 16
  48  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  49  * but we want to try to avoid allocating at 0x2900-0x2bff
  50  * which might have be mirrored at 0x0100-0x03ff..
  51  */
  52 resource_size_t
  53 pcibios_align_resource(void *data, const struct resource *res,
  54                        resource_size_t size, resource_size_t align)
  55 {
  56         struct pci_dev *dev = data;
  57         struct pci_controller *hose = dev->sysdata;
  58         resource_size_t start = res->start;
  59
  60         if (res->flags & IORESOURCE_IO) {
  61                 /* Make sure we start at our min on all hoses */
  62                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  63                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  64
  65                 /*
  66                  * Put everything into 0x00-0xff region modulo 0x400
  67                  */
  68                 if (start & 0x300)
  69                         start = (start + 0x3ff) & ~0x3ff;
  70         } else if (res->flags & IORESOURCE_MEM) {
  71                 /* Make sure we start at our min on all hoses */
  72                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  73                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  74         }
  75
  76         return start;
  77 }
  78
  79 static void pcibios_scanbus(struct pci_controller *hose)
  80 {
  81         static int next_busno;
  82         static int need_domain_info;
  83         LIST_HEAD(resources);
  84         struct pci_bus *bus;
  85
  86         if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
  87                 next_busno = (*hose->get_busno)();
  88
  89         pci_add_resource_offset(&resources,
  90                                 hose->mem_resource, hose->mem_offset);
  91         pci_add_resource_offset(&resources,
  92                                 hose->io_resource, hose->io_offset);
  93         pci_add_resource_offset(&resources,
  94                                 hose->busn_resource, hose->busn_offset);
  95         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
  96                                 &resources);
  97         hose->bus = bus;
  98
  99         need_domain_info = need_domain_info || hose->index;
 100         hose->need_domain_info = need_domain_info;
 101
 102         if (!bus) {
 103                 pci_free_resource_list(&resources);
 104                 return;
 105         }
 106
 107         next_busno = bus->busn_res.end + 1;
 108         /* Don't allow 8-bit bus number overflow inside the hose -
 109            reserve some space for bridges. */
 110         if (next_busno > 224) {
 111                 next_busno = 0;
 112                 need_domain_info = 1;
 113         }
 114
 115         /*
 116          * We insert PCI resources into the iomem_resource and
 117          * ioport_resource trees in either pci_bus_claim_resources()
 118          * or pci_bus_assign_resources().
 119          */
 120         if (pci_has_flag(PCI_PROBE_ONLY)) {
 121                 pci_bus_claim_resources(bus);
 122         } else {
 123                 pci_bus_size_bridges(bus);
 124                 pci_bus_assign_resources(bus);
 125         }
 126         pci_bus_add_devices(bus);
 127 }
 128
 129 #ifdef CONFIG_OF
 130 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
 131 {
 132         struct of_pci_range range;
 133         struct of_pci_range_parser parser;
 134
 135         pr_info("PCI host bridge %s ranges:\n", node->full_name);
 136         hose->of_node = node;
 137
 138         if (of_pci_range_parser_init(&parser, node))
 139                 return;
 140
 141         for_each_of_pci_range(&parser, &range) {
 142                 struct resource *res = NULL;
 143
 144                 switch (range.flags & IORESOURCE_TYPE_BITS) {
 145                 case IORESOURCE_IO:
 146                         pr_info("  IO 0x%016llx..0x%016llx\n",
 147                                 range.cpu_addr,
 148                                 range.cpu_addr + range.size - 1);
 149                         hose->io_map_base =
 150                                 (unsigned long)ioremap(range.cpu_addr,
 151                                                        range.size);
 152                         res = hose->io_resource;
 153                         break;
 154                 case IORESOURCE_MEM:
 155                         pr_info(" MEM 0x%016llx..0x%016llx\n",
 156                                 range.cpu_addr,
 157                                 range.cpu_addr + range.size - 1);
 158                         res = hose->mem_resource;
 159                         break;
 160                 }
 161                 if (res != NULL)
 162                         of_pci_range_to_resource(&range, node, res);
 163         }
 164 }
 165
 166 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
 167 {
 168         struct pci_controller *hose = bus->sysdata;
 169
 170         return of_node_get(hose->of_node);
 171 }
 172 #endif
 173
 174 static DEFINE_MUTEX(pci_scan_mutex);
 175
 176 void register_pci_controller(struct pci_controller *hose)
 177 {
 178         struct resource *parent;
 179
 180         parent = hose->mem_resource->parent;
 181         if (!parent)
 182                 parent = &iomem_resource;
 183
 184         if (request_resource(parent, hose->mem_resource) < 0)
 185                 goto out;
 186
 187         parent = hose->io_resource->parent;
 188         if (!parent)
 189                 parent = &ioport_resource;
 190
 191         if (request_resource(parent, hose->io_resource) < 0) {
 192                 release_resource(hose->mem_resource);
 193                 goto out;
 194         }
 195
 196         *hose_tail = hose;
 197         hose_tail = &hose->next;
 198
 199         /*
 200          * Do not panic here but later - this might happen before console init.
 201          */
 202         if (!hose->io_map_base) {
 203                 printk(KERN_WARNING
 204                        "registering PCI controller with io_map_base unset\n");
 205         }
 206
 207         /*
 208          * Scan the bus if it is register after the PCI subsystem
 209          * initialization.
 210          */
 211         if (pci_initialized) {
 212                 mutex_lock(&pci_scan_mutex);
 213                 pcibios_scanbus(hose);
 214                 mutex_unlock(&pci_scan_mutex);
 215         }
 216
 217         return;
 218
 219 out:
 220         printk(KERN_WARNING
 221                "Skipping PCI bus scan due to resource conflict\n");
 222 }
 223
 224 static void __init pcibios_set_cache_line_size(void)
 225 {
 226         struct cpuinfo_mips *c = &current_cpu_data;
 227         unsigned int lsize;
 228
 229         /*
 230          * Set PCI cacheline size to that of the highest level in the
 231          * cache hierarchy.
 232          */
 233         lsize = c->dcache.linesz;
 234         lsize = c->scache.linesz ? : lsize;
 235         lsize = c->tcache.linesz ? : lsize;
 236
 237         BUG_ON(!lsize);
 238
 239         pci_dfl_cache_line_size = lsize >> 2;
 240
 241         pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
 242 }
 243
 244 static int __init pcibios_init(void)
 245 {
 246         struct pci_controller *hose;
 247
 248         pcibios_set_cache_line_size();
 249
 250         /* Scan all of the recorded PCI controllers.  */
 251         for (hose = hose_head; hose; hose = hose->next)
 252                 pcibios_scanbus(hose);
 253
 254         pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
 255
 256         pci_initialized = 1;
 257
 258         return 0;
 259 }
 260
 261 subsys_initcall(pcibios_init);
 262
 263 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 264 {
 265         u16 cmd, old_cmd;
 266         int idx;
 267         struct resource *r;
 268
 269         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 270         old_cmd = cmd;
 271         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
 272                 /* Only set up the requested stuff */
 273                 if (!(mask & (1<<idx)))
 274                         continue;
 275
 276                 r = &dev->resource[idx];
 277                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 278                         continue;
 279                 if ((idx == PCI_ROM_RESOURCE) &&
 280                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 281                         continue;
 282                 if (!r->start && r->end) {
 283                         printk(KERN_ERR "PCI: Device %s not available "
 284                                "because of resource collisions\n",
 285                                pci_name(dev));
 286                         return -EINVAL;
 287                 }
 288                 if (r->flags & IORESOURCE_IO)
 289                         cmd |= PCI_COMMAND_IO;
 290                 if (r->flags & IORESOURCE_MEM)
 291                         cmd |= PCI_COMMAND_MEMORY;
 292         }
 293         if (cmd != old_cmd) {
 294                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 295                        pci_name(dev), old_cmd, cmd);
 296                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 297         }
 298         return 0;
 299 }
 300
 301 unsigned int pcibios_assign_all_busses(void)
 302 {
 303         return 1;
 304 }
 305
 306 int pcibios_enable_device(struct pci_dev *dev, int mask)
 307 {
 308         int err;
 309
 310         if ((err = pcibios_enable_resources(dev, mask)) < 0)
 311                 return err;
 312
 313         return pcibios_plat_dev_init(dev);
 314 }
 315
 316 void pcibios_fixup_bus(struct pci_bus *bus)
 317 {
 318         struct pci_dev *dev = bus->self;
 319
 320         if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
 321             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 322                 pci_read_bridge_bases(bus);
 323         }
 324 }
 325
 326 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 327 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 328
 329 void pci_resource_to_user(const struct pci_dev *dev, int bar,
 330                           const struct resource *rsrc, resource_size_t *start,
 331                           resource_size_t *end)
 332 {
 333         phys_addr_t size = resource_size(rsrc);
 334
 335         *start = fixup_bigphys_addr(rsrc->start, size);
 336         *end = rsrc->start + size;
 337 }
 338
 339 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 340                         enum pci_mmap_state mmap_state, int write_combine)
 341 {
 342         unsigned long prot;
 343
 344         /*
 345          * I/O space can be accessed via normal processor loads and stores on
 346          * this platform but for now we elect not to do this and portable
 347          * drivers should not do this anyway.
 348          */
 349         if (mmap_state == pci_mmap_io)
 350                 return -EINVAL;
 351
 352         /*
 353          * Ignore write-combine; for now only return uncached mappings.
 354          */
 355         prot = pgprot_val(vma->vm_page_prot);
 356         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 357         vma->vm_page_prot = __pgprot(prot);
 358
 359         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 360                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 361 }
 362
 363 char * (*pcibios_plat_setup)(char *str) __initdata;
 364
 365 char *__init pcibios_setup(char *str)
 366 {
 367         if (pcibios_plat_setup)
 368                 return pcibios_plat_setup(str);
 369         return str;
 370 }