2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
9 #include <linux/kernel.h>
11 #include <linux/bootmem.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
17 * Indicate whether we respect the PCI setup left by the firmware.
19 * Make this long-lived so that we know when shutting down
20 * whether we probed only or not.
24 #define PCI_ASSIGN_ALL_BUSSES 1
26 unsigned int pci_probe
= PCI_ASSIGN_ALL_BUSSES
;
29 * The PCI controller list.
32 static struct pci_controller
*hose_head
, **hose_tail
= &hose_head
;
34 unsigned long PCIBIOS_MIN_IO
= 0x0000;
35 unsigned long PCIBIOS_MIN_MEM
= 0;
37 static int pci_initialized
;
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
53 pcibios_align_resource(void *data
, struct resource
*res
,
54 resource_size_t size
, resource_size_t align
)
56 struct pci_dev
*dev
= data
;
57 struct pci_controller
*hose
= dev
->sysdata
;
58 resource_size_t start
= res
->start
;
60 if (res
->flags
& IORESOURCE_IO
) {
61 /* Make sure we start at our min on all hoses */
62 if (start
< PCIBIOS_MIN_IO
+ hose
->io_resource
->start
)
63 start
= PCIBIOS_MIN_IO
+ hose
->io_resource
->start
;
66 * Put everything into 0x00-0xff region modulo 0x400
69 start
= (start
+ 0x3ff) & ~0x3ff;
70 } else if (res
->flags
& IORESOURCE_MEM
) {
71 /* Make sure we start at our min on all hoses */
72 if (start
< PCIBIOS_MIN_MEM
+ hose
->mem_resource
->start
)
73 start
= PCIBIOS_MIN_MEM
+ hose
->mem_resource
->start
;
79 static void __devinit
pcibios_scanbus(struct pci_controller
*hose
)
81 static int next_busno
;
82 static int need_domain_info
;
86 PCI_DMA_BUS_IS_PHYS
= 1;
88 if (hose
->get_busno
&& pci_probe_only
)
89 next_busno
= (*hose
->get_busno
)();
91 bus
= pci_scan_bus(next_busno
, hose
->pci_ops
, hose
);
94 need_domain_info
= need_domain_info
|| hose
->index
;
95 hose
->need_domain_info
= need_domain_info
;
97 next_busno
= bus
->subordinate
+ 1;
98 /* Don't allow 8-bit bus number overflow inside the hose -
99 reserve some space for bridges. */
100 if (next_busno
> 224) {
102 need_domain_info
= 1;
105 if (!pci_probe_only
) {
106 pci_bus_size_bridges(bus
);
107 pci_bus_assign_resources(bus
);
108 pci_enable_bridges(bus
);
113 static DEFINE_MUTEX(pci_scan_mutex
);
115 void __devinit
register_pci_controller(struct pci_controller
*hose
)
117 if (request_resource(&iomem_resource
, hose
->mem_resource
) < 0)
119 if (request_resource(&ioport_resource
, hose
->io_resource
) < 0) {
120 release_resource(hose
->mem_resource
);
125 hose_tail
= &hose
->next
;
128 * Do not panic here but later - this might hapen before console init.
130 if (!hose
->io_map_base
) {
132 "registering PCI controller with io_map_base unset\n");
136 * Scan the bus if it is register after the PCI subsystem
139 if (pci_initialized
) {
140 mutex_lock(&pci_scan_mutex
);
141 pcibios_scanbus(hose
);
142 mutex_unlock(&pci_scan_mutex
);
149 "Skipping PCI bus scan due to resource conflict\n");
152 /* Most MIPS systems have straight-forward swizzling needs. */
154 static inline u8
bridge_swizzle(u8 pin
, u8 slot
)
156 return (((pin
- 1) + slot
) % 4) + 1;
159 static u8 __init
common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
163 while (dev
->bus
->parent
) {
164 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
165 /* Move up the chain of bridges. */
166 dev
= dev
->bus
->self
;
170 /* The slot is the slot of the last bridge. */
171 return PCI_SLOT(dev
->devfn
);
174 static int __init
pcibios_init(void)
176 struct pci_controller
*hose
;
178 /* Scan all of the recorded PCI controllers. */
179 for (hose
= hose_head
; hose
; hose
= hose
->next
)
180 pcibios_scanbus(hose
);
182 pci_fixup_irqs(common_swizzle
, pcibios_map_irq
);
189 subsys_initcall(pcibios_init
);
191 static int pcibios_enable_resources(struct pci_dev
*dev
, int mask
)
197 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
199 for (idx
=0; idx
< PCI_NUM_RESOURCES
; idx
++) {
200 /* Only set up the requested stuff */
201 if (!(mask
& (1<<idx
)))
204 r
= &dev
->resource
[idx
];
205 if (!(r
->flags
& (IORESOURCE_IO
| IORESOURCE_MEM
)))
207 if ((idx
== PCI_ROM_RESOURCE
) &&
208 (!(r
->flags
& IORESOURCE_ROM_ENABLE
)))
210 if (!r
->start
&& r
->end
) {
211 printk(KERN_ERR
"PCI: Device %s not available "
212 "because of resource collisions\n",
216 if (r
->flags
& IORESOURCE_IO
)
217 cmd
|= PCI_COMMAND_IO
;
218 if (r
->flags
& IORESOURCE_MEM
)
219 cmd
|= PCI_COMMAND_MEMORY
;
221 if (cmd
!= old_cmd
) {
222 printk("PCI: Enabling device %s (%04x -> %04x)\n",
223 pci_name(dev
), old_cmd
, cmd
);
224 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
230 * If we set up a device for bus mastering, we need to check the latency
231 * timer as certain crappy BIOSes forget to set it properly.
233 static unsigned int pcibios_max_latency
= 255;
235 void pcibios_set_master(struct pci_dev
*dev
)
238 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
240 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
241 else if (lat
> pcibios_max_latency
)
242 lat
= pcibios_max_latency
;
245 printk(KERN_DEBUG
"PCI: Setting latency timer of device %s to %d\n",
247 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
250 unsigned int pcibios_assign_all_busses(void)
252 return (pci_probe
& PCI_ASSIGN_ALL_BUSSES
) ? 1 : 0;
255 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
259 if ((err
= pcibios_enable_resources(dev
, mask
)) < 0)
262 return pcibios_plat_dev_init(dev
);
265 static void pcibios_fixup_device_resources(struct pci_dev
*dev
,
268 /* Update device resources. */
269 struct pci_controller
*hose
= (struct pci_controller
*)bus
->sysdata
;
270 unsigned long offset
= 0;
273 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
274 if (!dev
->resource
[i
].start
)
276 if (dev
->resource
[i
].flags
& IORESOURCE_PCI_FIXED
)
278 if (dev
->resource
[i
].flags
& IORESOURCE_IO
)
279 offset
= hose
->io_offset
;
280 else if (dev
->resource
[i
].flags
& IORESOURCE_MEM
)
281 offset
= hose
->mem_offset
;
283 dev
->resource
[i
].start
+= offset
;
284 dev
->resource
[i
].end
+= offset
;
288 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
290 /* Propagate hose info into the subordinate devices. */
292 struct pci_controller
*hose
= bus
->sysdata
;
293 struct list_head
*ln
;
294 struct pci_dev
*dev
= bus
->self
;
297 bus
->resource
[0] = hose
->io_resource
;
298 bus
->resource
[1] = hose
->mem_resource
;
299 } else if (pci_probe_only
&&
300 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
301 pci_read_bridge_bases(bus
);
302 pcibios_fixup_device_resources(dev
, bus
);
305 for (ln
= bus
->devices
.next
; ln
!= &bus
->devices
; ln
= ln
->next
) {
308 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
309 pcibios_fixup_device_resources(dev
, bus
);
314 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
316 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
319 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
320 struct resource
*res
)
322 struct pci_controller
*hose
= (struct pci_controller
*)dev
->sysdata
;
323 unsigned long offset
= 0;
325 if (res
->flags
& IORESOURCE_IO
)
326 offset
= hose
->io_offset
;
327 else if (res
->flags
& IORESOURCE_MEM
)
328 offset
= hose
->mem_offset
;
330 region
->start
= res
->start
- offset
;
331 region
->end
= res
->end
- offset
;
335 pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
336 struct pci_bus_region
*region
)
338 struct pci_controller
*hose
= (struct pci_controller
*)dev
->sysdata
;
339 unsigned long offset
= 0;
341 if (res
->flags
& IORESOURCE_IO
)
342 offset
= hose
->io_offset
;
343 else if (res
->flags
& IORESOURCE_MEM
)
344 offset
= hose
->mem_offset
;
346 res
->start
= region
->start
+ offset
;
347 res
->end
= region
->end
+ offset
;
350 #ifdef CONFIG_HOTPLUG
351 EXPORT_SYMBOL(pcibios_resource_to_bus
);
352 EXPORT_SYMBOL(pcibios_bus_to_resource
);
353 EXPORT_SYMBOL(PCIBIOS_MIN_IO
);
354 EXPORT_SYMBOL(PCIBIOS_MIN_MEM
);
357 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
358 enum pci_mmap_state mmap_state
, int write_combine
)
363 * I/O space can be accessed via normal processor loads and stores on
364 * this platform but for now we elect not to do this and portable
365 * drivers should not do this anyway.
367 if (mmap_state
== pci_mmap_io
)
371 * Ignore write-combine; for now only return uncached mappings.
373 prot
= pgprot_val(vma
->vm_page_prot
);
374 prot
= (prot
& ~_CACHE_MASK
) | _CACHE_UNCACHED
;
375 vma
->vm_page_prot
= __pgprot(prot
);
377 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
378 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
381 char * (*pcibios_plat_setup
)(char *str
) __devinitdata
;
383 char *__devinit
pcibios_setup(char *str
)
385 if (pcibios_plat_setup
)
386 return pcibios_plat_setup(str
);