arch/mips/philips/pnx8550/common/int.c

   1 /*
   2  *
   3  * Copyright (C) 2005 Embedded Alley Solutions, Inc
   4  * Ported to 2.6.
   5  *
   6  * Per Hallsmark, per.hallsmark@mvista.com
   7  * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
   8  * Copyright (C) 2001 Ralf Baechle
   9  *
  10  * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
  11  *
  12  *  This program is free software; you can distribute it and/or modify it
  13  *  under the terms of the GNU General Public License (Version 2) as
  14  *  published by the Free Software Foundation.
  15  *
  16  *  This program is distributed in the hope it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  19  *  for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along
  22  *  with this program; if not, write to the Free Software Foundation, Inc.,
  23  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  24  *
  25  */
  26 #include <linux/compiler.h>
  27 #include <linux/init.h>
  28 #include <linux/irq.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kernel_stat.h>
  33 #include <linux/random.h>
  34 #include <linux/module.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/gdb-stub.h>
  38 #include <int.h>
  39 #include <uart.h>
  40
  41 /* default prio for interrupts */
  42 /* first one is a no-no so therefore always prio 0 (disabled) */
  43 static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
  44         0, 1, 1, 1, 1, 15, 1, 1, 1, 1,  //   0 -  9
  45         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  10 - 19
  46         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  20 - 29
  47         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  30 - 39
  48         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  40 - 49
  49         1, 1, 1, 1, 1, 1, 1, 1, 2, 1,   //  50 - 59
  50         1, 1, 1, 1, 1, 1, 1, 1, 1, 1,   //  60 - 69
  51         1                       //  70
  52 };
  53
  54 static void hw0_irqdispatch(int irq)
  55 {
  56         /* find out which interrupt */
  57         irq = PNX8550_GIC_VECTOR_0 >> 3;
  58
  59         if (irq == 0) {
  60                 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
  61                 return;
  62         }
  63         do_IRQ(PNX8550_INT_GIC_MIN + irq);
  64 }
  65
  66
  67 static void timer_irqdispatch(int irq)
  68 {
  69         irq = (0x01c0 & read_c0_config7()) >> 6;
  70
  71         if (unlikely(irq == 0)) {
  72                 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
  73                 return;
  74         }
  75
  76         if (irq & 0x1)
  77                 do_IRQ(PNX8550_INT_TIMER1);
  78         if (irq & 0x2)
  79                 do_IRQ(PNX8550_INT_TIMER2);
  80         if (irq & 0x4)
  81                 do_IRQ(PNX8550_INT_TIMER3);
  82 }
  83
  84 asmlinkage void plat_irq_dispatch(void)
  85 {
  86         unsigned int pending = read_c0_status() & read_c0_cause();
  87
  88         if (pending & STATUSF_IP2)
  89                 hw0_irqdispatch(2);
  90         else if (pending & STATUSF_IP7) {
  91                 if (read_c0_config7() & 0x01c0)
  92                         timer_irqdispatch(7);
  93         }
  94
  95         spurious_interrupt();
  96 }
  97
  98 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
  99 {
 100         unsigned long status = read_c0_status();
 101
 102         status &= ~((clr_mask & 0xFF) << 8);
 103         status |= (set_mask & 0xFF) << 8;
 104
 105         write_c0_status(status);
 106 }
 107
 108 static inline void mask_gic_int(unsigned int irq_nr)
 109 {
 110         /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
 111         PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
 112 }
 113
 114 static inline void unmask_gic_int(unsigned int irq_nr)
 115 {
 116         /* set prio mask to lower four bits and enable interrupt */
 117         PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
 118 }
 119
 120 static inline void mask_irq(unsigned int irq_nr)
 121 {
 122         if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
 123                 modify_cp0_intmask(1 << irq_nr, 0);
 124         } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
 125                 (irq_nr <= PNX8550_INT_GIC_MAX)) {
 126                 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
 127         } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
 128                 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
 129                 modify_cp0_intmask(1 << 7, 0);
 130         } else {
 131                 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
 132         }
 133 }
 134
 135 static inline void unmask_irq(unsigned int irq_nr)
 136 {
 137         if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
 138                 modify_cp0_intmask(0, 1 << irq_nr);
 139         } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
 140                 (irq_nr <= PNX8550_INT_GIC_MAX)) {
 141                 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
 142         } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
 143                 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
 144                 modify_cp0_intmask(0, 1 << 7);
 145         } else {
 146                 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
 147         }
 148 }
 149
 150 int pnx8550_set_gic_priority(int irq, int priority)
 151 {
 152         int gic_irq = irq-PNX8550_INT_GIC_MIN;
 153         int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
 154
 155         gic_prio[gic_irq] = priority;
 156         PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
 157
 158         return prev_priority;
 159 }
 160
 161 static struct irq_chip level_irq_type = {
 162         .typename =     "PNX Level IRQ",
 163         .ack =          mask_irq,
 164         .mask =         mask_irq,
 165         .mask_ack =     mask_irq,
 166         .unmask =       unmask_irq,
 167 };
 168
 169 static struct irqaction gic_action = {
 170         .handler =      no_action,
 171         .flags =        IRQF_DISABLED,
 172         .name =         "GIC",
 173 };
 174
 175 static struct irqaction timer_action = {
 176         .handler =      no_action,
 177         .flags =        IRQF_DISABLED,
 178         .name =         "Timer",
 179 };
 180
 181 void __init arch_init_irq(void)
 182 {
 183         int i;
 184         int configPR;
 185
 186         for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
 187                 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
 188                 mask_irq(i);    /* mask the irq just in case  */
 189         }
 190
 191         /* init of GIC/IPC interrupts */
 192         /* should be done before cp0 since cp0 init enables the GIC int */
 193         for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
 194                 int gic_int_line = i - PNX8550_INT_GIC_MIN;
 195                 if (gic_int_line == 0 )
 196                         continue;       // don't fiddle with int 0
 197                 /*
 198                  * enable change of TARGET, ENABLE and ACTIVE_LOW bits
 199                  * set TARGET        0 to route through hw0 interrupt
 200                  * set ACTIVE_LOW    0 active high  (correct?)
 201                  *
 202                  * We really should setup an interrupt description table
 203                  * to do this nicely.
 204                  * Note, PCI INTA is active low on the bus, but inverted
 205                  * in the GIC, so to us it's active high.
 206                  */
 207 #ifdef CONFIG_PNX8550_V2PCI
 208                 if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
 209                         /* PCI INT through gpio 8, which is setup in
 210                          * pnx8550_setup.c and routed to GPIO
 211                          * Interrupt Level 0 (GPIO Connection 58).
 212                          * Set it active low. */
 213
 214                         PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
 215                 } else
 216 #endif
 217                 {
 218                         PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
 219                 }
 220
 221                 /* mask/priority is still 0 so we will not get any
 222                  * interrupts until it is unmasked */
 223
 224                 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
 225         }
 226
 227         /* Priority level 0 */
 228         PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
 229
 230         /* Set int vector table address */
 231         PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 232
 233         set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
 234                                  handle_level_irq);
 235         setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 236
 237         /* init of Timer interrupts */
 238         for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
 239                 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
 240
 241         /* Stop Timer 1-3 */
 242         configPR = read_c0_config7();
 243         configPR |= 0x00000038;
 244         write_c0_config7(configPR);
 245
 246         set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
 247                                  handle_level_irq);
 248         setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 249 }
 250
 251 EXPORT_SYMBOL(pnx8550_set_gic_priority);