2 * Pistachio platform setup
4 * Copyright (C) 2014 Google, Inc.
5 * Copyright (C) 2016 Imagination Technologies
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/of_address.h>
16 #include <linux/of_fdt.h>
18 #include <asm/cacheflush.h>
19 #include <asm/dma-coherence.h>
20 #include <asm/fw/fw.h>
21 #include <asm/mips-boards/generic.h>
22 #include <asm/mips-cm.h>
23 #include <asm/mips-cpc.h>
25 #include <asm/smp-ops.h>
26 #include <asm/traps.h>
29 * Core revision register decoding
30 * Bits 23 to 20: Major rev
31 * Bits 15 to 8: Minor rev
32 * Bits 7 to 0: Maintenance rev
34 #define PISTACHIO_CORE_REV_REG 0xB81483D0
35 #define PISTACHIO_CORE_REV_A1 0x00100006
36 #define PISTACHIO_CORE_REV_B0 0x00100106
38 const char *get_system_type(void)
43 core_rev
= __raw_readl((const void *)PISTACHIO_CORE_REV_REG
);
46 case PISTACHIO_CORE_REV_B0
:
47 sys_type
= "IMG Pistachio SoC (B0)";
50 case PISTACHIO_CORE_REV_A1
:
51 sys_type
= "IMG Pistachio SoC (A1)";
55 sys_type
= "IMG Pistachio SoC";
62 static void __init
plat_setup_iocoherency(void)
65 * Kernel has been configured with software coherency
66 * but we might choose to turn it off and use hardware
69 if (mips_cm_numiocu() != 0) {
70 /* Nothing special needs to be done to enable coherency */
71 pr_info("CMP IOCU detected\n");
74 pr_info("Hardware DMA cache coherency disabled\n");
76 pr_info("Hardware DMA cache coherency enabled\n");
79 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
81 pr_info("Software DMA cache coherency enabled\n");
85 void __init
*plat_get_fdt(void)
88 panic("Device-tree not present");
89 return (void *)fw_arg1
;
92 void __init
plat_mem_setup(void)
94 __dt_setup_arch(plat_get_fdt());
96 plat_setup_iocoherency();
99 #define DEFAULT_CPC_BASE_ADDR 0x1bde0000
100 #define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
102 phys_addr_t
mips_cpc_default_phys_base(void)
104 return DEFAULT_CPC_BASE_ADDR
;
107 phys_addr_t
mips_cdmm_phys_base(void)
109 return DEFAULT_CDMM_BASE_ADDR
;
112 static void __init
mips_nmi_setup(void)
115 extern char except_vec_nmi
;
117 base
= cpu_has_veic
?
118 (void *)(CAC_BASE
+ 0xa80) :
119 (void *)(CAC_BASE
+ 0x380);
120 memcpy(base
, &except_vec_nmi
, 0x80);
121 flush_icache_range((unsigned long)base
,
122 (unsigned long)base
+ 0x80);
125 static void __init
mips_ejtag_setup(void)
128 extern char except_vec_ejtag_debug
;
130 base
= cpu_has_veic
?
131 (void *)(CAC_BASE
+ 0xa00) :
132 (void *)(CAC_BASE
+ 0x300);
133 memcpy(base
, &except_vec_ejtag_debug
, 0x80);
134 flush_icache_range((unsigned long)base
,
135 (unsigned long)base
+ 0x80);
138 void __init
prom_init(void)
140 board_nmi_handler_setup
= mips_nmi_setup
;
141 board_ejtag_handler_setup
= mips_ejtag_setup
;
145 register_cps_smp_ops();
147 pr_info("SoC Type: %s\n", get_system_type());
150 void __init
prom_free_prom_memory(void)
154 void __init
device_tree_init(void)
156 if (!initial_boot_params
)
159 unflatten_and_copy_device_tree();