arch/mips/pistachio/init.c

   1 /*
   2  * Pistachio platform setup
   3  *
   4  * Copyright (C) 2014 Google, Inc.
   5  * Copyright (C) 2016 Imagination Technologies
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_fdt.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/dma-coherence.h>
  20 #include <asm/fw/fw.h>
  21 #include <asm/mips-boards/generic.h>
  22 #include <asm/mips-cm.h>
  23 #include <asm/mips-cpc.h>
  24 #include <asm/prom.h>
  25 #include <asm/smp-ops.h>
  26 #include <asm/traps.h>
  27
  28 /*
  29  * Core revision register decoding
  30  * Bits 23 to 20: Major rev
  31  * Bits 15 to 8: Minor rev
  32  * Bits 7 to 0: Maintenance rev
  33  */
  34 #define PISTACHIO_CORE_REV_REG  0xB81483D0
  35 #define PISTACHIO_CORE_REV_A1   0x00100006
  36 #define PISTACHIO_CORE_REV_B0   0x00100106
  37
  38 const char *get_system_type(void)
  39 {
  40         u32 core_rev;
  41         const char *sys_type;
  42
  43         core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
  44
  45         switch (core_rev) {
  46         case PISTACHIO_CORE_REV_B0:
  47                 sys_type = "IMG Pistachio SoC (B0)";
  48                 break;
  49
  50         case PISTACHIO_CORE_REV_A1:
  51                 sys_type = "IMG Pistachio SoC (A1)";
  52                 break;
  53
  54         default:
  55                 sys_type = "IMG Pistachio SoC";
  56                 break;
  57         }
  58
  59         return sys_type;
  60 }
  61
  62 static void __init plat_setup_iocoherency(void)
  63 {
  64         /*
  65          * Kernel has been configured with software coherency
  66          * but we might choose to turn it off and use hardware
  67          * coherency instead.
  68          */
  69         if (mips_cm_numiocu() != 0) {
  70                 /* Nothing special needs to be done to enable coherency */
  71                 pr_info("CMP IOCU detected\n");
  72                 hw_coherentio = 1;
  73                 if (coherentio == 0)
  74                         pr_info("Hardware DMA cache coherency disabled\n");
  75                 else
  76                         pr_info("Hardware DMA cache coherency enabled\n");
  77         } else {
  78                 if (coherentio == 1)
  79                         pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
  80                 else
  81                         pr_info("Software DMA cache coherency enabled\n");
  82         }
  83 }
  84
  85 void __init *plat_get_fdt(void)
  86 {
  87         if (fw_arg0 != -2)
  88                 panic("Device-tree not present");
  89         return (void *)fw_arg1;
  90 }
  91
  92 void __init plat_mem_setup(void)
  93 {
  94         __dt_setup_arch(plat_get_fdt());
  95
  96         plat_setup_iocoherency();
  97 }
  98
  99 #define DEFAULT_CPC_BASE_ADDR   0x1bde0000
 100 #define DEFAULT_CDMM_BASE_ADDR  0x1bdd0000
 101
 102 phys_addr_t mips_cpc_default_phys_base(void)
 103 {
 104         return DEFAULT_CPC_BASE_ADDR;
 105 }
 106
 107 phys_addr_t mips_cdmm_phys_base(void)
 108 {
 109         return DEFAULT_CDMM_BASE_ADDR;
 110 }
 111
 112 static void __init mips_nmi_setup(void)
 113 {
 114         void *base;
 115         extern char except_vec_nmi;
 116
 117         base = cpu_has_veic ?
 118                 (void *)(CAC_BASE + 0xa80) :
 119                 (void *)(CAC_BASE + 0x380);
 120         memcpy(base, &except_vec_nmi, 0x80);
 121         flush_icache_range((unsigned long)base,
 122                            (unsigned long)base + 0x80);
 123 }
 124
 125 static void __init mips_ejtag_setup(void)
 126 {
 127         void *base;
 128         extern char except_vec_ejtag_debug;
 129
 130         base = cpu_has_veic ?
 131                 (void *)(CAC_BASE + 0xa00) :
 132                 (void *)(CAC_BASE + 0x300);
 133         memcpy(base, &except_vec_ejtag_debug, 0x80);
 134         flush_icache_range((unsigned long)base,
 135                            (unsigned long)base + 0x80);
 136 }
 137
 138 void __init prom_init(void)
 139 {
 140         board_nmi_handler_setup = mips_nmi_setup;
 141         board_ejtag_handler_setup = mips_ejtag_setup;
 142
 143         mips_cm_probe();
 144         mips_cpc_probe();
 145         register_cps_smp_ops();
 146
 147         pr_info("SoC Type: %s\n", get_system_type());
 148 }
 149
 150 void __init prom_free_prom_memory(void)
 151 {
 152 }
 153
 154 void __init device_tree_init(void)
 155 {
 156         if (!initial_boot_params)
 157                 return;
 158
 159         unflatten_and_copy_device_tree();
 160 }