arch/mips/ralink/rt305x.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify it
   3  * under the terms of the GNU General Public License version 2 as published
   4  * by the Free Software Foundation.
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   9  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  10  * Copyright (C) 2013 John Crispin <john@phrozen.org>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mipsregs.h>
  18 #include <asm/mach-ralink/ralink_regs.h>
  19 #include <asm/mach-ralink/rt305x.h>
  20 #include <asm/mach-ralink/pinmux.h>
  21
  22 #include "common.h"
  23
  24 static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
  25 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  26 static struct rt2880_pmx_func uartf_func[] = {
  27         FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
  28         FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
  29         FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
  30         FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
  31         FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
  32         FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
  33         FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
  34 };
  35 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
  36 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  37 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  38 static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
  39 static struct rt2880_pmx_func rt5350_cs1_func[] = {
  40         FUNC("spi_cs1", 0, 27, 1),
  41         FUNC("wdg_cs1", 1, 27, 1),
  42 };
  43 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  44 static struct rt2880_pmx_func rt3352_rgmii_func[] = {
  45         FUNC("rgmii", 0, 24, 12)
  46 };
  47 static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
  48 static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
  49 static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
  50 static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
  51
  52 static struct rt2880_pmx_group rt3050_pinmux_data[] = {
  53         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  54         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  55         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  56                 RT305X_GPIO_MODE_UART0_SHIFT),
  57         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  58         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  59         GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  60         GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  61         GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
  62         { 0 }
  63 };
  64
  65 static struct rt2880_pmx_group rt3352_pinmux_data[] = {
  66         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  67         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  68         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  69                 RT305X_GPIO_MODE_UART0_SHIFT),
  70         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  71         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  72         GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  73         GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  74         GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
  75         GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
  76         GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  77         { 0 }
  78 };
  79
  80 static struct rt2880_pmx_group rt5350_pinmux_data[] = {
  81         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  82         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  83         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  84                 RT305X_GPIO_MODE_UART0_SHIFT),
  85         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  86         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  87         GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  88         GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
  89         { 0 }
  90 };
  91
  92 static void rt305x_wdt_reset(void)
  93 {
  94         u32 t;
  95
  96         /* enable WDT reset output on pin SRAM_CS_N */
  97         t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  98         t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
  99                 RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
 100         rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
 101 }
 102
 103 static unsigned long rt5350_get_mem_size(void)
 104 {
 105         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 106         unsigned long ret;
 107         u32 t;
 108
 109         t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
 110         t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
 111                 RT5350_SYSCFG0_DRAM_SIZE_MASK;
 112
 113         switch (t) {
 114         case RT5350_SYSCFG0_DRAM_SIZE_2M:
 115                 ret = 2;
 116                 break;
 117         case RT5350_SYSCFG0_DRAM_SIZE_8M:
 118                 ret = 8;
 119                 break;
 120         case RT5350_SYSCFG0_DRAM_SIZE_16M:
 121                 ret = 16;
 122                 break;
 123         case RT5350_SYSCFG0_DRAM_SIZE_32M:
 124                 ret = 32;
 125                 break;
 126         case RT5350_SYSCFG0_DRAM_SIZE_64M:
 127                 ret = 64;
 128                 break;
 129         default:
 130                 panic("rt5350: invalid DRAM size: %u", t);
 131                 break;
 132         }
 133
 134         return ret;
 135 }
 136
 137 void __init ralink_clk_init(void)
 138 {
 139         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
 140         unsigned long wmac_rate = 40000000;
 141
 142         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 143
 144         if (soc_is_rt305x() || soc_is_rt3350()) {
 145                 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
 146                      RT305X_SYSCFG_CPUCLK_MASK;
 147                 switch (t) {
 148                 case RT305X_SYSCFG_CPUCLK_LOW:
 149                         cpu_rate = 320000000;
 150                         break;
 151                 case RT305X_SYSCFG_CPUCLK_HIGH:
 152                         cpu_rate = 384000000;
 153                         break;
 154                 }
 155                 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
 156         } else if (soc_is_rt3352()) {
 157                 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
 158                      RT3352_SYSCFG0_CPUCLK_MASK;
 159                 switch (t) {
 160                 case RT3352_SYSCFG0_CPUCLK_LOW:
 161                         cpu_rate = 384000000;
 162                         break;
 163                 case RT3352_SYSCFG0_CPUCLK_HIGH:
 164                         cpu_rate = 400000000;
 165                         break;
 166                 }
 167                 sys_rate = wdt_rate = cpu_rate / 3;
 168                 uart_rate = 40000000;
 169         } else if (soc_is_rt5350()) {
 170                 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
 171                      RT5350_SYSCFG0_CPUCLK_MASK;
 172                 switch (t) {
 173                 case RT5350_SYSCFG0_CPUCLK_360:
 174                         cpu_rate = 360000000;
 175                         sys_rate = cpu_rate / 3;
 176                         break;
 177                 case RT5350_SYSCFG0_CPUCLK_320:
 178                         cpu_rate = 320000000;
 179                         sys_rate = cpu_rate / 4;
 180                         break;
 181                 case RT5350_SYSCFG0_CPUCLK_300:
 182                         cpu_rate = 300000000;
 183                         sys_rate = cpu_rate / 3;
 184                         break;
 185                 default:
 186                         BUG();
 187                 }
 188                 uart_rate = 40000000;
 189                 wdt_rate = sys_rate;
 190         } else {
 191                 BUG();
 192         }
 193
 194         if (soc_is_rt3352() || soc_is_rt5350()) {
 195                 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
 196
 197                 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
 198                         wmac_rate = 20000000;
 199         }
 200
 201         ralink_clk_add("cpu", cpu_rate);
 202         ralink_clk_add("sys", sys_rate);
 203         ralink_clk_add("10000b00.spi", sys_rate);
 204         ralink_clk_add("10000b40.spi", sys_rate);
 205         ralink_clk_add("10000100.timer", wdt_rate);
 206         ralink_clk_add("10000120.watchdog", wdt_rate);
 207         ralink_clk_add("10000500.uart", uart_rate);
 208         ralink_clk_add("10000c00.uartlite", uart_rate);
 209         ralink_clk_add("10100000.ethernet", sys_rate);
 210         ralink_clk_add("10180000.wmac", wmac_rate);
 211 }
 212
 213 void __init ralink_of_remap(void)
 214 {
 215         rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
 216         rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
 217
 218         if (!rt_sysc_membase || !rt_memc_membase)
 219                 panic("Failed to remap core resources");
 220 }
 221
 222 void prom_soc_init(struct ralink_soc_info *soc_info)
 223 {
 224         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 225         unsigned char *name;
 226         u32 n0;
 227         u32 n1;
 228         u32 id;
 229
 230         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 231         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 232
 233         if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
 234                 unsigned long icache_sets;
 235
 236                 icache_sets = (read_c0_config1() >> 22) & 7;
 237                 if (icache_sets == 1) {
 238                         ralink_soc = RT305X_SOC_RT3050;
 239                         name = "RT3050";
 240                         soc_info->compatible = "ralink,rt3050-soc";
 241                 } else {
 242                         ralink_soc = RT305X_SOC_RT3052;
 243                         name = "RT3052";
 244                         soc_info->compatible = "ralink,rt3052-soc";
 245                 }
 246         } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
 247                 ralink_soc = RT305X_SOC_RT3350;
 248                 name = "RT3350";
 249                 soc_info->compatible = "ralink,rt3350-soc";
 250         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
 251                 ralink_soc = RT305X_SOC_RT3352;
 252                 name = "RT3352";
 253                 soc_info->compatible = "ralink,rt3352-soc";
 254         } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
 255                 ralink_soc = RT305X_SOC_RT5350;
 256                 name = "RT5350";
 257                 soc_info->compatible = "ralink,rt5350-soc";
 258         } else {
 259                 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 260         }
 261
 262         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 263
 264         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 265                 "Ralink %s id:%u rev:%u",
 266                 name,
 267                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 268                 (id & CHIP_ID_REV_MASK));
 269
 270         soc_info->mem_base = RT305X_SDRAM_BASE;
 271         if (soc_is_rt5350()) {
 272                 soc_info->mem_size = rt5350_get_mem_size();
 273                 rt2880_pinmux_data = rt5350_pinmux_data;
 274         } else if (soc_is_rt305x() || soc_is_rt3350()) {
 275                 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
 276                 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
 277                 rt2880_pinmux_data = rt3050_pinmux_data;
 278         } else if (soc_is_rt3352()) {
 279                 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
 280                 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
 281                 rt2880_pinmux_data = rt3352_pinmux_data;
 282         }
 283 }