arch/mips/sgi-ip32/ip32-irq.c

   1 /*
   2  * Code to handle IP32 IRQs
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  * Copyright (C) 2001 Keith M Wesolowski
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/bitops.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/mm.h>
  20 #include <linux/random.h>
  21 #include <linux/sched.h>
  22
  23 #include <asm/mipsregs.h>
  24 #include <asm/signal.h>
  25 #include <asm/system.h>
  26 #include <asm/time.h>
  27 #include <asm/ip32/crime.h>
  28 #include <asm/ip32/mace.h>
  29 #include <asm/ip32/ip32_ints.h>
  30
  31 /* issue a PIO read to make sure no PIO writes are pending */
  32 static void inline flush_crime_bus(void)
  33 {
  34         crime->control;
  35 }
  36
  37 static void inline flush_mace_bus(void)
  38 {
  39         mace->perif.ctrl.misc;
  40 }
  41
  42 #undef DEBUG_IRQ
  43 #ifdef DEBUG_IRQ
  44 #define DBG(x...) printk(x)
  45 #else
  46 #define DBG(x...)
  47 #endif
  48
  49 /* O2 irq map
  50  *
  51  * IP0 -> software (ignored)
  52  * IP1 -> software (ignored)
  53  * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
  54  * IP3 -> (irq1) X unknown
  55  * IP4 -> (irq2) X unknown
  56  * IP5 -> (irq3) X unknown
  57  * IP6 -> (irq4) X unknown
  58  * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
  59  *
  60  * crime: (C)
  61  *
  62  * CRIME_INT_STAT 31:0:
  63  *
  64  * 0  -> 1  Video in 1
  65  * 1  -> 2  Video in 2
  66  * 2  -> 3  Video out
  67  * 3  -> 4  Mace ethernet
  68  * 4  -> S  SuperIO sub-interrupt
  69  * 5  -> M  Miscellaneous sub-interrupt
  70  * 6  -> A  Audio sub-interrupt
  71  * 7  -> 8  PCI bridge errors
  72  * 8  -> 9  PCI SCSI aic7xxx 0
  73  * 9  -> 10 PCI SCSI aic7xxx 1
  74  * 10 -> 11 PCI slot 0
  75  * 11 -> 12 unused (PCI slot 1)
  76  * 12 -> 13 unused (PCI slot 2)
  77  * 13 -> 14 unused (PCI shared 0)
  78  * 14 -> 15 unused (PCI shared 1)
  79  * 15 -> 16 unused (PCI shared 2)
  80  * 16 -> 17 GBE0 (E)
  81  * 17 -> 18 GBE1 (E)
  82  * 18 -> 19 GBE2 (E)
  83  * 19 -> 20 GBE3 (E)
  84  * 20 -> 21 CPU errors
  85  * 21 -> 22 Memory errors
  86  * 22 -> 23 RE empty edge (E)
  87  * 23 -> 24 RE full edge (E)
  88  * 24 -> 25 RE idle edge (E)
  89  * 25 -> 26 RE empty level
  90  * 26 -> 27 RE full level
  91  * 27 -> 28 RE idle level
  92  * 28 -> 29 unused (software 0) (E)
  93  * 29 -> 30 unused (software 1) (E)
  94  * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
  95  * 31 -> 32 VICE
  96  *
  97  * S, M, A: Use the MACE ISA interrupt register
  98  * MACE_ISA_INT_STAT 31:0
  99  *
 100  * 0-7 -> 33-40 Audio
 101  * 8 -> 41 RTC
 102  * 9 -> 42 Keyboard
 103  * 10 -> X Keyboard polled
 104  * 11 -> 44 Mouse
 105  * 12 -> X Mouse polled
 106  * 13-15 -> 46-48 Count/compare timers
 107  * 16-19 -> 49-52 Parallel (16 E)
 108  * 20-25 -> 53-58 Serial 1 (22 E)
 109  * 26-31 -> 59-64 Serial 2 (28 E)
 110  *
 111  * Note that this means IRQs 5-7, 43, and 45 do not exist.  This is a
 112  * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 113  * is quite different anyway.
 114  */
 115
 116 /* Some initial interrupts to set up */
 117 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
 118 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
 119
 120 struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
 121                         CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
 122 struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
 123                         CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
 124
 125 /*
 126  * For interrupts wired from a single device to the CPU.  Only the clock
 127  * uses this it seems, which is IRQ 0 and IP7.
 128  */
 129
 130 static void enable_cpu_irq(unsigned int irq)
 131 {
 132         set_c0_status(STATUSF_IP7);
 133 }
 134
 135 static void disable_cpu_irq(unsigned int irq)
 136 {
 137         clear_c0_status(STATUSF_IP7);
 138 }
 139
 140 static void end_cpu_irq(unsigned int irq)
 141 {
 142         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 143                 enable_cpu_irq (irq);
 144 }
 145
 146 static struct irq_chip ip32_cpu_interrupt = {
 147         .typename = "IP32 CPU",
 148         .ack = disable_cpu_irq,
 149         .mask = disable_cpu_irq,
 150         .mask_ack = disable_cpu_irq,
 151         .unmask = enable_cpu_irq,
 152         .end = end_cpu_irq,
 153 };
 154
 155 /*
 156  * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 157  * We get to split the register in half and do faster lookups.
 158  */
 159
 160 static uint64_t crime_mask;
 161
 162 static void enable_crime_irq(unsigned int irq)
 163 {
 164         crime_mask |= 1 << (irq - 1);
 165         crime->imask = crime_mask;
 166 }
 167
 168 static void disable_crime_irq(unsigned int irq)
 169 {
 170         crime_mask &= ~(1 << (irq - 1));
 171         crime->imask = crime_mask;
 172         flush_crime_bus();
 173 }
 174
 175 static void mask_and_ack_crime_irq(unsigned int irq)
 176 {
 177         /* Edge triggered interrupts must be cleared. */
 178         if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
 179             || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
 180             || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
 181                 uint64_t crime_int;
 182                 crime_int = crime->hard_int;
 183                 crime_int &= ~(1 << (irq - 1));
 184                 crime->hard_int = crime_int;
 185         }
 186         disable_crime_irq(irq);
 187 }
 188
 189 static void end_crime_irq(unsigned int irq)
 190 {
 191         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 192                 enable_crime_irq(irq);
 193 }
 194
 195 static struct irq_chip ip32_crime_interrupt = {
 196         .typename = "IP32 CRIME",
 197         .ack = mask_and_ack_crime_irq,
 198         .mask = disable_crime_irq,
 199         .mask_ack = mask_and_ack_crime_irq,
 200         .unmask = enable_crime_irq,
 201         .end = end_crime_irq,
 202 };
 203
 204 /*
 205  * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 206  * as close to the source as possible.  This also means we can take the
 207  * next chunk of the CRIME register in one piece.
 208  */
 209
 210 static unsigned long macepci_mask;
 211
 212 static void enable_macepci_irq(unsigned int irq)
 213 {
 214         macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
 215         mace->pci.control = macepci_mask;
 216         crime_mask |= 1 << (irq - 1);
 217         crime->imask = crime_mask;
 218 }
 219
 220 static void disable_macepci_irq(unsigned int irq)
 221 {
 222         crime_mask &= ~(1 << (irq - 1));
 223         crime->imask = crime_mask;
 224         flush_crime_bus();
 225         macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
 226         mace->pci.control = macepci_mask;
 227         flush_mace_bus();
 228 }
 229
 230 static void end_macepci_irq(unsigned int irq)
 231 {
 232         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 233                 enable_macepci_irq(irq);
 234 }
 235
 236 static struct irq_chip ip32_macepci_interrupt = {
 237         .typename = "IP32 MACE PCI",
 238         .ack = disable_macepci_irq,
 239         .mask = disable_macepci_irq,
 240         .mask_ack = disable_macepci_irq,
 241         .unmask = enable_macepci_irq,
 242         .end = end_macepci_irq,
 243 };
 244
 245 /* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 246  * CRIME register.
 247  */
 248
 249 #define MACEISA_AUDIO_INT       (MACEISA_AUDIO_SW_INT |         \
 250                                  MACEISA_AUDIO_SC_INT |         \
 251                                  MACEISA_AUDIO1_DMAT_INT |      \
 252                                  MACEISA_AUDIO1_OF_INT |        \
 253                                  MACEISA_AUDIO2_DMAT_INT |      \
 254                                  MACEISA_AUDIO2_MERR_INT |      \
 255                                  MACEISA_AUDIO3_DMAT_INT |      \
 256                                  MACEISA_AUDIO3_MERR_INT)
 257 #define MACEISA_MISC_INT        (MACEISA_RTC_INT |              \
 258                                  MACEISA_KEYB_INT |             \
 259                                  MACEISA_KEYB_POLL_INT |        \
 260                                  MACEISA_MOUSE_INT |            \
 261                                  MACEISA_MOUSE_POLL_INT |       \
 262                                  MACEISA_TIMER0_INT |           \
 263                                  MACEISA_TIMER1_INT |           \
 264                                  MACEISA_TIMER2_INT)
 265 #define MACEISA_SUPERIO_INT     (MACEISA_PARALLEL_INT |         \
 266                                  MACEISA_PAR_CTXA_INT |         \
 267                                  MACEISA_PAR_CTXB_INT |         \
 268                                  MACEISA_PAR_MERR_INT |         \
 269                                  MACEISA_SERIAL1_INT |          \
 270                                  MACEISA_SERIAL1_TDMAT_INT |    \
 271                                  MACEISA_SERIAL1_TDMAPR_INT |   \
 272                                  MACEISA_SERIAL1_TDMAME_INT |   \
 273                                  MACEISA_SERIAL1_RDMAT_INT |    \
 274                                  MACEISA_SERIAL1_RDMAOR_INT |   \
 275                                  MACEISA_SERIAL2_INT |          \
 276                                  MACEISA_SERIAL2_TDMAT_INT |    \
 277                                  MACEISA_SERIAL2_TDMAPR_INT |   \
 278                                  MACEISA_SERIAL2_TDMAME_INT |   \
 279                                  MACEISA_SERIAL2_RDMAT_INT |    \
 280                                  MACEISA_SERIAL2_RDMAOR_INT)
 281
 282 static unsigned long maceisa_mask;
 283
 284 static void enable_maceisa_irq (unsigned int irq)
 285 {
 286         unsigned int crime_int = 0;
 287
 288         DBG ("maceisa enable: %u\n", irq);
 289
 290         switch (irq) {
 291         case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
 292                 crime_int = MACE_AUDIO_INT;
 293                 break;
 294         case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
 295                 crime_int = MACE_MISC_INT;
 296                 break;
 297         case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
 298                 crime_int = MACE_SUPERIO_INT;
 299                 break;
 300         }
 301         DBG ("crime_int %08x enabled\n", crime_int);
 302         crime_mask |= crime_int;
 303         crime->imask = crime_mask;
 304         maceisa_mask |= 1 << (irq - 33);
 305         mace->perif.ctrl.imask = maceisa_mask;
 306 }
 307
 308 static void disable_maceisa_irq(unsigned int irq)
 309 {
 310         unsigned int crime_int = 0;
 311
 312         maceisa_mask &= ~(1 << (irq - 33));
 313         if(!(maceisa_mask & MACEISA_AUDIO_INT))
 314                 crime_int |= MACE_AUDIO_INT;
 315         if(!(maceisa_mask & MACEISA_MISC_INT))
 316                 crime_int |= MACE_MISC_INT;
 317         if(!(maceisa_mask & MACEISA_SUPERIO_INT))
 318                 crime_int |= MACE_SUPERIO_INT;
 319         crime_mask &= ~crime_int;
 320         crime->imask = crime_mask;
 321         flush_crime_bus();
 322         mace->perif.ctrl.imask = maceisa_mask;
 323         flush_mace_bus();
 324 }
 325
 326 static void mask_and_ack_maceisa_irq(unsigned int irq)
 327 {
 328         unsigned long mace_int;
 329
 330         switch (irq) {
 331         case MACEISA_PARALLEL_IRQ:
 332         case MACEISA_SERIAL1_TDMAPR_IRQ:
 333         case MACEISA_SERIAL2_TDMAPR_IRQ:
 334                 /* edge triggered */
 335                 mace_int = mace->perif.ctrl.istat;
 336                 mace_int &= ~(1 << (irq - 33));
 337                 mace->perif.ctrl.istat = mace_int;
 338                 break;
 339         }
 340         disable_maceisa_irq(irq);
 341 }
 342
 343 static void end_maceisa_irq(unsigned irq)
 344 {
 345         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 346                 enable_maceisa_irq(irq);
 347 }
 348
 349 static struct irq_chip ip32_maceisa_interrupt = {
 350         .typename = "IP32 MACE ISA",
 351         .ack = mask_and_ack_maceisa_irq,
 352         .mask = disable_maceisa_irq,
 353         .mask_ack = mask_and_ack_maceisa_irq,
 354         .unmask = enable_maceisa_irq,
 355         .end = end_maceisa_irq,
 356 };
 357
 358 /* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 359  * bits 0-3 and 7 in the CRIME register.
 360  */
 361
 362 static void enable_mace_irq(unsigned int irq)
 363 {
 364         crime_mask |= 1 << (irq - 1);
 365         crime->imask = crime_mask;
 366 }
 367
 368 static void disable_mace_irq(unsigned int irq)
 369 {
 370         crime_mask &= ~(1 << (irq - 1));
 371         crime->imask = crime_mask;
 372         flush_crime_bus();
 373 }
 374
 375 static void end_mace_irq(unsigned int irq)
 376 {
 377         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 378                 enable_mace_irq(irq);
 379 }
 380
 381 static struct irq_chip ip32_mace_interrupt = {
 382         .typename = "IP32 MACE",
 383         .ack = disable_mace_irq,
 384         .mask = disable_mace_irq,
 385         .mask_ack = disable_mace_irq,
 386         .unmask = enable_mace_irq,
 387         .end = end_mace_irq,
 388 };
 389
 390 static void ip32_unknown_interrupt(void)
 391 {
 392         printk ("Unknown interrupt occurred!\n");
 393         printk ("cp0_status: %08x\n", read_c0_status());
 394         printk ("cp0_cause: %08x\n", read_c0_cause());
 395         printk ("CRIME intr mask: %016lx\n", crime->imask);
 396         printk ("CRIME intr status: %016lx\n", crime->istat);
 397         printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
 398         printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
 399         printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
 400         printk ("MACE PCI control register: %08x\n", mace->pci.control);
 401
 402         printk("Register dump:\n");
 403         show_regs(get_irq_regs());
 404
 405         printk("Please mail this report to linux-mips@linux-mips.org\n");
 406         printk("Spinning...");
 407         while(1) ;
 408 }
 409
 410 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */
 411 /* change this to loop over all edge-triggered irqs, exception masked out ones */
 412 static void ip32_irq0(void)
 413 {
 414         uint64_t crime_int;
 415         int irq = 0;
 416
 417         crime_int = crime->istat & crime_mask;
 418         irq = __ffs(crime_int);
 419         crime_int = 1 << irq;
 420
 421         if (crime_int & CRIME_MACEISA_INT_MASK) {
 422                 unsigned long mace_int = mace->perif.ctrl.istat;
 423                 irq = __ffs(mace_int & maceisa_mask) + 32;
 424         }
 425         irq++;
 426         DBG("*irq %u*\n", irq);
 427         do_IRQ(irq);
 428 }
 429
 430 static void ip32_irq1(void)
 431 {
 432         ip32_unknown_interrupt();
 433 }
 434
 435 static void ip32_irq2(void)
 436 {
 437         ip32_unknown_interrupt();
 438 }
 439
 440 static void ip32_irq3(void)
 441 {
 442         ip32_unknown_interrupt();
 443 }
 444
 445 static void ip32_irq4(void)
 446 {
 447         ip32_unknown_interrupt();
 448 }
 449
 450 static void ip32_irq5(void)
 451 {
 452         ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
 453 }
 454
 455 asmlinkage void plat_irq_dispatch(void)
 456 {
 457         unsigned int pending = read_c0_cause();
 458
 459         if (likely(pending & IE_IRQ0))
 460                 ip32_irq0();
 461         else if (unlikely(pending & IE_IRQ1))
 462                 ip32_irq1();
 463         else if (unlikely(pending & IE_IRQ2))
 464                 ip32_irq2();
 465         else if (unlikely(pending & IE_IRQ3))
 466                 ip32_irq3();
 467         else if (unlikely(pending & IE_IRQ4))
 468                 ip32_irq4();
 469         else if (likely(pending & IE_IRQ5))
 470                 ip32_irq5();
 471 }
 472
 473 void __init arch_init_irq(void)
 474 {
 475         unsigned int irq;
 476
 477         /* Install our interrupt handler, then clear and disable all
 478          * CRIME and MACE interrupts. */
 479         crime->imask = 0;
 480         crime->hard_int = 0;
 481         crime->soft_int = 0;
 482         mace->perif.ctrl.istat = 0;
 483         mace->perif.ctrl.imask = 0;
 484
 485         for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
 486                 struct irq_chip *controller;
 487
 488                 if (irq == IP32_R4K_TIMER_IRQ)
 489                         controller = &ip32_cpu_interrupt;
 490                 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
 491                         controller = &ip32_mace_interrupt;
 492                 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
 493                         controller = &ip32_macepci_interrupt;
 494                 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
 495                         controller = &ip32_crime_interrupt;
 496                 else
 497                         controller = &ip32_maceisa_interrupt;
 498
 499                 set_irq_chip(irq, controller);
 500         }
 501         setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
 502         setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
 503
 504 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 505         change_c0_status(ST0_IM, ALLINTS);
 506 }