arch/mips/sni/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Linus Torvalds
   7  * Copyright (C) 1994 - 2000 Ralf Baechle
   8  */
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14
  15 #include <asm/i8259.h>
  16 #include <asm/io.h>
  17 #include <asm/sni.h>
  18
  19 static void enable_pciasic_irq(unsigned int irq)
  20 {
  21         unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
  22
  23         *(volatile u8 *) PCIMT_IRQSEL |= mask;
  24 }
  25
  26 void disable_pciasic_irq(unsigned int irq)
  27 {
  28         unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
  29
  30         *(volatile u8 *) PCIMT_IRQSEL &= mask;
  31 }
  32
  33 static void end_pciasic_irq(unsigned int irq)
  34 {
  35         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  36                 enable_pciasic_irq(irq);
  37 }
  38
  39 static struct irq_chip pciasic_irq_type = {
  40         .name = "ASIC-PCI",
  41         .ack = disable_pciasic_irq,
  42         .mask = disable_pciasic_irq,
  43         .mask_ack = disable_pciasic_irq,
  44         .unmask = enable_pciasic_irq,
  45         .end = end_pciasic_irq,
  46 };
  47
  48 /*
  49  * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
  50  * button interrupts.  Later ...
  51  */
  52 static void pciasic_hwint0(void)
  53 {
  54         panic("Received int0 but no handler yet ...");
  55 }
  56
  57 /* This interrupt was used for the com1 console on the first prototypes.  */
  58 static void pciasic_hwint2(void)
  59 {
  60         /* I think this shouldn't happen on production machines.  */
  61         panic("hwint2 and no handler yet");
  62 }
  63
  64 /* hwint5 is the r4k count / compare interrupt  */
  65 static void pciasic_hwint5(void)
  66 {
  67         panic("hwint5 and no handler yet");
  68 }
  69
  70 static unsigned int ls1bit8(unsigned int x)
  71 {
  72         int b = 7, s;
  73
  74         s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
  75         s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
  76         s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
  77
  78         return b;
  79 }
  80
  81 /*
  82  * hwint 1 deals with EISA and SCSI interrupts,
  83  *
  84  * The EISA_INT bit in CSITPEND is high active, all others are low active.
  85  */
  86 static void pciasic_hwint1(void)
  87 {
  88         u8 pend = *(volatile char *)PCIMT_CSITPEND;
  89         unsigned long flags;
  90
  91         if (pend & IT_EISA) {
  92                 int irq;
  93                 /*
  94                  * Note: ASIC PCI's builtin interrupt achknowledge feature is
  95                  * broken.  Using it may result in loss of some or all i8259
  96                  * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
  97                  */
  98                 irq = i8259_irq();
  99                 if (unlikely(irq < 0))
 100                         return;
 101
 102                 do_IRQ(irq);
 103         }
 104
 105         if (!(pend & IT_SCSI)) {
 106                 flags = read_c0_status();
 107                 clear_c0_status(ST0_IM);
 108                 do_IRQ(PCIMT_IRQ_SCSI);
 109                 write_c0_status(flags);
 110         }
 111 }
 112
 113 /*
 114  * hwint 3 should deal with the PCI A - D interrupts,
 115  */
 116 static void pciasic_hwint3(void)
 117 {
 118         u8 pend = *(volatile char *)PCIMT_CSITPEND;
 119         int irq;
 120
 121         pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
 122         clear_c0_status(IE_IRQ3);
 123         irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
 124         do_IRQ(irq);
 125         set_c0_status(IE_IRQ3);
 126 }
 127
 128 /*
 129  * hwint 4 is used for only the onboard PCnet 32.
 130  */
 131 static void pciasic_hwint4(void)
 132 {
 133         clear_c0_status(IE_IRQ4);
 134         do_IRQ(PCIMT_IRQ_ETHERNET);
 135         set_c0_status(IE_IRQ4);
 136 }
 137
 138 asmlinkage void plat_irq_dispatch(void)
 139 {
 140         unsigned int pending = read_c0_status() & read_c0_cause();
 141         static unsigned char led_cache;
 142
 143         *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
 144
 145         if (pending & 0x0800)
 146                 pciasic_hwint1();
 147         else if (pending & 0x4000)
 148                 pciasic_hwint4();
 149         else if (pending & 0x2000)
 150                 pciasic_hwint3();
 151         else if (pending & 0x1000)
 152                 pciasic_hwint2();
 153         else if (pending & 0x8000)
 154                 pciasic_hwint5();
 155         else if (pending & 0x0400)
 156                 pciasic_hwint0();
 157 }
 158
 159 void __init init_pciasic(void)
 160 {
 161         * (volatile u8 *) PCIMT_IRQSEL =
 162                 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
 163 }
 164
 165 /*
 166  * On systems with i8259-style interrupt controllers we assume for
 167  * driver compatibility reasons interrupts 0 - 15 to be the i8295
 168  * interrupts even if the hardware uses a different interrupt numbering.
 169  */
 170 void __init arch_init_irq(void)
 171 {
 172         int i;
 173
 174         init_i8259_irqs();                      /* Integrated i8259  */
 175         init_pciasic();
 176
 177         /* Actually we've got more interrupts to handle ...  */
 178         for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
 179                 set_irq_chip(i, &pciasic_irq_type);
 180
 181         change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
 182 }