2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
49 #include <linux/swap.h>
50 #include <linux/ioport.h>
51 #include <linux/sched.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/timex.h>
56 #include <linux/platform_device.h>
58 #include <asm/bootinfo.h>
62 #include <asm/irq_regs.h>
63 #include <asm/processor.h>
64 #include <asm/reboot.h>
66 #include <linux/bootmem.h>
67 #include <linux/blkdev.h>
68 #ifdef CONFIG_TOSHIBA_FPCIB0
69 #include <asm/tx4927/smsc_fdc37m81x.h>
71 #include <asm/tx4927/toshiba_rbtx4927.h>
73 #include <asm/tx4927/tx4927_pci.h>
75 #ifdef CONFIG_BLK_DEV_IDEPCI
76 #include <linux/hdreg.h>
77 #include <linux/ide.h>
79 #ifdef CONFIG_SERIAL_TXX9
80 #include <linux/tty.h>
81 #include <linux/serial.h>
82 #include <linux/serial_core.h>
85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
88 #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
90 #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
91 #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
92 #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
94 #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
98 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
99 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
100 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
101 #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
103 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
106 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
107 static const u32 toshiba_rbtx4927_setup_debug_flag
=
108 (TOSHIBA_RBTX4927_SETUP_NONE
| TOSHIBA_RBTX4927_SETUP_INFO
|
109 TOSHIBA_RBTX4927_SETUP_WARN
| TOSHIBA_RBTX4927_SETUP_EROR
|
110 TOSHIBA_RBTX4927_SETUP_EFWFU
| TOSHIBA_RBTX4927_SETUP_SETUP
|
111 TOSHIBA_RBTX4927_SETUP_TIME_INIT
| TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
112 | TOSHIBA_RBTX4927_SETUP_PCIBIOS
| TOSHIBA_RBTX4927_SETUP_PCI1
|
113 TOSHIBA_RBTX4927_SETUP_PCI2
| TOSHIBA_RBTX4927_SETUP_PCI66
);
116 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
117 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
118 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
121 sprintf( tmp, str ); \
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
125 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
128 /* These functions are used for rebooting or halting the machine*/
129 extern void toshiba_rbtx4927_restart(char *command
);
130 extern void toshiba_rbtx4927_halt(void);
131 extern void toshiba_rbtx4927_power_off(void);
133 int tx4927_using_backplane
= 0;
135 extern void gt64120_time_init(void);
136 extern void toshiba_rbtx4927_irq_setup(void);
138 char *prom_getcmdline(void);
141 #undef TX4927_SUPPORT_COMMAND_IO
142 #undef TX4927_SUPPORT_PCI_66
143 int tx4927_cpu_clock
= 100000000; /* 100MHz */
144 unsigned long mips_pci_io_base
;
145 unsigned long mips_pci_io_size
;
146 unsigned long mips_pci_mem_base
;
147 unsigned long mips_pci_mem_size
;
148 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
149 unsigned long mips_pci_io_pciaddr
= 0;
150 unsigned long mips_memory_upper
;
151 static int tx4927_ccfg_toeon
= 1;
152 static int tx4927_pcic_trdyto
= 0; /* default: disabled */
153 unsigned long tx4927_ce_base
[8];
154 void tx4927_pci_setup(void);
155 void tx4927_reset_pci_pcic(void);
156 int tx4927_pci66
= 0; /* 0:auto */
159 char *toshiba_name
= "";
162 static void tx4927_pcierr_interrupt(int irq
, void *dev_id
)
164 #ifdef CONFIG_BLK_DEV_IDEPCI
165 /* ignore MasterAbort for ide probing... */
166 if (irq
== TX4927_IRQ_IRC_PCIERR
&&
167 ((tx4927_pcicptr
->pcistatus
>> 16) & 0xf900) ==
168 PCI_STATUS_REC_MASTER_ABORT
) {
169 tx4927_pcicptr
->pcistatus
=
171 pcistatus
& 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
177 printk("PCI error interrupt (irq 0x%x).\n", irq
);
179 printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
180 (unsigned short) (tx4927_pcicptr
->pcistatus
>> 16),
181 tx4927_pcicptr
->g2pstatus
, tx4927_pcicptr
->pcicstatus
);
182 printk("ccfg:%08lx, tear:%02lx_%08lx\n",
183 (unsigned long) tx4927_ccfgptr
->ccfg
,
184 (unsigned long) (tx4927_ccfgptr
->tear
>> 32),
185 (unsigned long) tx4927_ccfgptr
->tear
);
186 show_regs(get_irq_regs());
189 void __init
toshiba_rbtx4927_pci_irq_init(void)
194 void tx4927_reset_pci_pcic(void)
197 *tx4927_pcireset_ptr
= 1;
199 tx4927_ccfgptr
->clkctr
|= TX4927_CLKCTR_PCIRST
;
201 /* clear PCIC reset */
202 tx4927_ccfgptr
->clkctr
&= ~TX4927_CLKCTR_PCIRST
;
203 *tx4927_pcireset_ptr
= 0;
205 #endif /* CONFIG_PCI */
208 void print_pci_status(void)
210 printk("PCI STATUS %lx\n", tx4927_pcicptr
->pcistatus
);
211 printk("PCIC STATUS %lx\n", tx4927_pcicptr
->pcicstatus
);
214 extern struct pci_controller tx4927_controller
;
216 static struct pci_dev
*fake_pci_dev(struct pci_controller
*hose
,
217 int top_bus
, int busnr
, int devfn
)
219 static struct pci_dev dev
;
220 static struct pci_bus bus
;
222 dev
.sysdata
= (void *)hose
;
225 bus
.ops
= hose
->pci_ops
;
232 #define EARLY_PCI_OP(rw, size, type) \
233 static int early_##rw##_config_##size(struct pci_controller *hose, \
234 int top_bus, int bus, int devfn, int offset, type value) \
236 return pci_##rw##_config_##size( \
237 fake_pci_dev(hose, top_bus, bus, devfn), \
241 EARLY_PCI_OP(read
, byte
, u8
*)
242 EARLY_PCI_OP(read
, word
, u16
*)
243 EARLY_PCI_OP(read
, dword
, u32
*)
244 EARLY_PCI_OP(write
, byte
, u8
)
245 EARLY_PCI_OP(write
, word
, u16
)
246 EARLY_PCI_OP(write
, dword
, u32
)
248 static int __init
tx4927_pcibios_init(void)
253 int devfn_stop
= 0xff;
254 int busno
= 0; /* One bus on the Toshiba */
255 struct pci_controller
*hose
= &tx4927_controller
;
257 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
260 for (pci_devfn
= devfn_start
; pci_devfn
< devfn_stop
; pci_devfn
++) {
261 early_read_config_dword(hose
, busno
, busno
, pci_devfn
,
264 if (id
== 0xffffffff) {
268 if (id
== 0x94601055) {
272 char *s
= " sb/isa --";
274 TOSHIBA_RBTX4927_SETUP_DPRINTK
275 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
, ":%s beg\n",
278 early_read_config_byte(hose
, busno
, busno
,
279 pci_devfn
, 0x64, &v08_64
);
280 early_read_config_dword(hose
, busno
, busno
,
281 pci_devfn
, 0xb0, &v32_b0
);
282 early_read_config_byte(hose
, busno
, busno
,
283 pci_devfn
, 0xe1, &v08_e1
);
285 TOSHIBA_RBTX4927_SETUP_DPRINTK
286 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
287 ":%s beg 0x64 = 0x%02x\n", s
, v08_64
);
288 TOSHIBA_RBTX4927_SETUP_DPRINTK
289 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
290 ":%s beg 0xb0 = 0x%02x\n", s
, v32_b0
);
291 TOSHIBA_RBTX4927_SETUP_DPRINTK
292 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
293 ":%s beg 0xe1 = 0x%02x\n", s
, v08_e1
);
295 /* serial irq control */
299 v32_b0
|= 0x00010000;
301 /* ide irq on isa14 */
305 TOSHIBA_RBTX4927_SETUP_DPRINTK
306 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
307 ":%s mid 0x64 = 0x%02x\n", s
, v08_64
);
308 TOSHIBA_RBTX4927_SETUP_DPRINTK
309 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
310 ":%s mid 0xb0 = 0x%02x\n", s
, v32_b0
);
311 TOSHIBA_RBTX4927_SETUP_DPRINTK
312 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
313 ":%s mid 0xe1 = 0x%02x\n", s
, v08_e1
);
315 early_write_config_byte(hose
, busno
, busno
,
316 pci_devfn
, 0x64, v08_64
);
317 early_write_config_dword(hose
, busno
, busno
,
318 pci_devfn
, 0xb0, v32_b0
);
319 early_write_config_byte(hose
, busno
, busno
,
320 pci_devfn
, 0xe1, v08_e1
);
322 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
324 early_read_config_byte(hose
, busno
, busno
,
327 early_read_config_dword(hose
, busno
, busno
,
330 early_read_config_byte(hose
, busno
, busno
,
334 TOSHIBA_RBTX4927_SETUP_DPRINTK
335 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
336 ":%s end 0x64 = 0x%02x\n", s
, v08_64
);
337 TOSHIBA_RBTX4927_SETUP_DPRINTK
338 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
339 ":%s end 0xb0 = 0x%02x\n", s
, v32_b0
);
340 TOSHIBA_RBTX4927_SETUP_DPRINTK
341 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
342 ":%s end 0xe1 = 0x%02x\n", s
, v08_e1
);
346 TOSHIBA_RBTX4927_SETUP_DPRINTK
347 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
, ":%s end\n",
351 if (id
== 0x91301055) {
357 char *s
= " sb/ide --";
359 TOSHIBA_RBTX4927_SETUP_DPRINTK
360 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
, ":%s beg\n",
363 early_read_config_byte(hose
, busno
, busno
,
364 pci_devfn
, 0x04, &v08_04
);
365 early_read_config_byte(hose
, busno
, busno
,
366 pci_devfn
, 0x09, &v08_09
);
367 early_read_config_byte(hose
, busno
, busno
,
368 pci_devfn
, 0x41, &v08_41
);
369 early_read_config_byte(hose
, busno
, busno
,
370 pci_devfn
, 0x43, &v08_43
);
371 early_read_config_byte(hose
, busno
, busno
,
372 pci_devfn
, 0x5c, &v08_5c
);
374 TOSHIBA_RBTX4927_SETUP_DPRINTK
375 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
376 ":%s beg 0x04 = 0x%02x\n", s
, v08_04
);
377 TOSHIBA_RBTX4927_SETUP_DPRINTK
378 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
379 ":%s beg 0x09 = 0x%02x\n", s
, v08_09
);
380 TOSHIBA_RBTX4927_SETUP_DPRINTK
381 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
382 ":%s beg 0x41 = 0x%02x\n", s
, v08_41
);
383 TOSHIBA_RBTX4927_SETUP_DPRINTK
384 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
385 ":%s beg 0x43 = 0x%02x\n", s
, v08_43
);
386 TOSHIBA_RBTX4927_SETUP_DPRINTK
387 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
388 ":%s beg 0x5c = 0x%02x\n", s
, v08_5c
);
390 /* enable ide master/io */
391 v08_04
|= (PCI_COMMAND_MASTER
| PCI_COMMAND_IO
);
393 /* enable ide native mode */
396 /* enable primary ide */
399 /* enable secondary ide */
403 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
405 * This line of code is intended to provide the user with a work
406 * around solution to the anomalies cited in SMSC's anomaly sheet
407 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
409 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
413 TOSHIBA_RBTX4927_SETUP_DPRINTK
414 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
415 ":%s mid 0x04 = 0x%02x\n", s
, v08_04
);
416 TOSHIBA_RBTX4927_SETUP_DPRINTK
417 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
418 ":%s mid 0x09 = 0x%02x\n", s
, v08_09
);
419 TOSHIBA_RBTX4927_SETUP_DPRINTK
420 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
421 ":%s mid 0x41 = 0x%02x\n", s
, v08_41
);
422 TOSHIBA_RBTX4927_SETUP_DPRINTK
423 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
424 ":%s mid 0x43 = 0x%02x\n", s
, v08_43
);
425 TOSHIBA_RBTX4927_SETUP_DPRINTK
426 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
427 ":%s mid 0x5c = 0x%02x\n", s
, v08_5c
);
429 early_write_config_byte(hose
, busno
, busno
,
430 pci_devfn
, 0x5c, v08_5c
);
431 early_write_config_byte(hose
, busno
, busno
,
432 pci_devfn
, 0x04, v08_04
);
433 early_write_config_byte(hose
, busno
, busno
,
434 pci_devfn
, 0x09, v08_09
);
435 early_write_config_byte(hose
, busno
, busno
,
436 pci_devfn
, 0x41, v08_41
);
437 early_write_config_byte(hose
, busno
, busno
,
438 pci_devfn
, 0x43, v08_43
);
440 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
442 early_read_config_byte(hose
, busno
, busno
,
445 early_read_config_byte(hose
, busno
, busno
,
448 early_read_config_byte(hose
, busno
, busno
,
451 early_read_config_byte(hose
, busno
, busno
,
454 early_read_config_byte(hose
, busno
, busno
,
458 TOSHIBA_RBTX4927_SETUP_DPRINTK
459 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
460 ":%s end 0x04 = 0x%02x\n", s
, v08_04
);
461 TOSHIBA_RBTX4927_SETUP_DPRINTK
462 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
463 ":%s end 0x09 = 0x%02x\n", s
, v08_09
);
464 TOSHIBA_RBTX4927_SETUP_DPRINTK
465 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
466 ":%s end 0x41 = 0x%02x\n", s
, v08_41
);
467 TOSHIBA_RBTX4927_SETUP_DPRINTK
468 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
469 ":%s end 0x43 = 0x%02x\n", s
, v08_43
);
470 TOSHIBA_RBTX4927_SETUP_DPRINTK
471 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
472 ":%s end 0x5c = 0x%02x\n", s
, v08_5c
);
476 TOSHIBA_RBTX4927_SETUP_DPRINTK
477 (TOSHIBA_RBTX4927_SETUP_PCIBIOS
, ":%s end\n",
483 register_pci_controller(&tx4927_controller
);
484 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS
,
490 arch_initcall(tx4927_pcibios_init
);
492 extern struct resource pci_io_resource
;
493 extern struct resource pci_mem_resource
;
495 void tx4927_pci_setup(void)
497 static int called
= 0;
498 extern unsigned int tx4927_get_mem_size(void);
500 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
, "-\n");
502 mips_memory_upper
= tx4927_get_mem_size() << 20;
503 mips_memory_upper
+= KSEG0
;
504 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
505 "0x%08lx=mips_memory_upper\n",
507 mips_pci_io_base
= TX4927_PCIIO
;
508 mips_pci_io_size
= TX4927_PCIIO_SIZE
;
509 mips_pci_mem_base
= TX4927_PCIMEM
;
510 mips_pci_mem_size
= TX4927_PCIMEM_SIZE
;
512 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
513 "0x%08lx=mips_pci_io_base\n",
515 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
516 "0x%08lx=mips_pci_io_size\n",
518 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
519 "0x%08lx=mips_pci_mem_base\n",
521 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
522 "0x%08lx=mips_pci_mem_size\n",
524 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
525 "0x%08lx=pci_io_resource.start\n",
526 pci_io_resource
.start
);
527 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
528 "0x%08lx=pci_io_resource.end\n",
529 pci_io_resource
.end
);
530 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
531 "0x%08lx=pci_mem_resource.start\n",
532 pci_mem_resource
.start
);
533 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
534 "0x%08lx=pci_mem_resource.end\n",
535 pci_mem_resource
.end
);
536 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
537 "0x%08lx=mips_io_port_base",
541 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
543 (unsigned short) (tx4927_pcicptr
->pciid
>> 16),
544 (unsigned short) (tx4927_pcicptr
->pciid
& 0xffff),
545 (unsigned short) (tx4927_pcicptr
->pciccrev
& 0xff),
547 ccfg
& TX4927_CCFG_PCIXARB
)) ? "External" :
551 printk("%s PCIC --%s PCICLK:",toshiba_name
,
552 (tx4927_ccfgptr
->ccfg
& TX4927_CCFG_PCI66
) ? " PCI66" : "");
553 if (tx4927_ccfgptr
->pcfg
& TX4927_PCFG_PCICLKEN_ALL
) {
555 if (mips_machtype
== MACH_TOSHIBA_RBTX4937
)
556 switch ((unsigned long) tx4927_ccfgptr
->
557 ccfg
& TX4937_CCFG_PCIDIVMODE_MASK
) {
558 case TX4937_CCFG_PCIDIVMODE_4
:
559 pciclk
= tx4927_cpu_clock
/ 4;
561 case TX4937_CCFG_PCIDIVMODE_4_5
:
562 pciclk
= tx4927_cpu_clock
* 2 / 9;
564 case TX4937_CCFG_PCIDIVMODE_5
:
565 pciclk
= tx4927_cpu_clock
/ 5;
567 case TX4937_CCFG_PCIDIVMODE_5_5
:
568 pciclk
= tx4927_cpu_clock
* 2 / 11;
570 case TX4937_CCFG_PCIDIVMODE_8
:
571 pciclk
= tx4927_cpu_clock
/ 8;
573 case TX4937_CCFG_PCIDIVMODE_9
:
574 pciclk
= tx4927_cpu_clock
/ 9;
576 case TX4937_CCFG_PCIDIVMODE_10
:
577 pciclk
= tx4927_cpu_clock
/ 10;
579 case TX4937_CCFG_PCIDIVMODE_11
:
580 pciclk
= tx4927_cpu_clock
/ 11;
585 switch ((unsigned long) tx4927_ccfgptr
->
586 ccfg
& TX4927_CCFG_PCIDIVMODE_MASK
) {
587 case TX4927_CCFG_PCIDIVMODE_2_5
:
588 pciclk
= tx4927_cpu_clock
* 2 / 5;
590 case TX4927_CCFG_PCIDIVMODE_3
:
591 pciclk
= tx4927_cpu_clock
/ 3;
593 case TX4927_CCFG_PCIDIVMODE_5
:
594 pciclk
= tx4927_cpu_clock
/ 5;
596 case TX4927_CCFG_PCIDIVMODE_6
:
597 pciclk
= tx4927_cpu_clock
/ 6;
601 printk("Internal(%dMHz)", pciclk
/ 1000000);
604 int pciclk_setting
= *tx4927_pci_clk_ptr
;
605 switch (pciclk_setting
& TX4927_PCI_CLK_MASK
) {
606 case TX4927_PCI_CLK_33
:
609 case TX4927_PCI_CLK_25
:
612 case TX4927_PCI_CLK_66
:
615 case TX4927_PCI_CLK_50
:
619 printk("External(%dMHz)", pciclk
/ 1000000);
625 /* GB->PCI mappings */
626 tx4927_pcicptr
->g2piomask
= (mips_pci_io_size
- 1) >> 4;
627 tx4927_pcicptr
->g2piogbase
= mips_pci_io_base
|
629 TX4927_PCIC_G2PIOGBASE_ECHG
631 TX4927_PCIC_G2PIOGBASE_BSDIS
635 tx4927_pcicptr
->g2piopbase
= 0;
637 tx4927_pcicptr
->g2pmmask
[0] = (mips_pci_mem_size
- 1) >> 4;
638 tx4927_pcicptr
->g2pmgbase
[0] = mips_pci_mem_base
|
640 TX4927_PCIC_G2PMnGBASE_ECHG
642 TX4927_PCIC_G2PMnGBASE_BSDIS
645 tx4927_pcicptr
->g2pmpbase
[0] = mips_pci_mem_base
;
647 tx4927_pcicptr
->g2pmmask
[1] = 0;
648 tx4927_pcicptr
->g2pmgbase
[1] = 0;
649 tx4927_pcicptr
->g2pmpbase
[1] = 0;
650 tx4927_pcicptr
->g2pmmask
[2] = 0;
651 tx4927_pcicptr
->g2pmgbase
[2] = 0;
652 tx4927_pcicptr
->g2pmpbase
[2] = 0;
655 /* PCI->GB mappings (I/O 256B) */
656 tx4927_pcicptr
->p2giopbase
= 0; /* 256B */
658 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
659 tx4927_pcicptr
->p2gm0plbase
= 0;
660 tx4927_pcicptr
->p2gm0pubase
= 0;
661 tx4927_pcicptr
->p2gmgbase
[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN
|
663 TX4927_PCIC_P2GMnGBASE_TECHG
665 TX4927_PCIC_P2GMnGBASE_TBSDIS
669 /* PCI->GB mappings (MEM 16MB) -not used */
670 tx4927_pcicptr
->p2gm1plbase
= 0xffffffff;
671 tx4927_pcicptr
->p2gm1pubase
= 0xffffffff;
672 tx4927_pcicptr
->p2gmgbase
[1] = 0;
674 /* PCI->GB mappings (MEM 1MB) -not used */
675 tx4927_pcicptr
->p2gm2pbase
= 0xffffffff;
676 tx4927_pcicptr
->p2gmgbase
[2] = 0;
679 /* Enable Initiator Memory 0 Space, I/O Space, Config */
680 tx4927_pcicptr
->pciccfg
&= TX4927_PCIC_PCICCFG_LBWC_MASK
;
681 tx4927_pcicptr
->pciccfg
|=
682 TX4927_PCIC_PCICCFG_IMSE0
| TX4927_PCIC_PCICCFG_IISE
|
683 TX4927_PCIC_PCICCFG_ICAE
| TX4927_PCIC_PCICCFG_ATR
;
686 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
687 tx4927_pcicptr
->pcicfg1
= 0;
689 if (tx4927_pcic_trdyto
>= 0) {
690 tx4927_pcicptr
->g2ptocnt
&= ~0xff;
691 tx4927_pcicptr
->g2ptocnt
|= (tx4927_pcic_trdyto
& 0xff);
694 /* Clear All Local Bus Status */
695 tx4927_pcicptr
->pcicstatus
= TX4927_PCIC_PCICSTATUS_ALL
;
696 /* Enable All Local Bus Interrupts */
697 tx4927_pcicptr
->pcicmask
= TX4927_PCIC_PCICSTATUS_ALL
;
698 /* Clear All Initiator Status */
699 tx4927_pcicptr
->g2pstatus
= TX4927_PCIC_G2PSTATUS_ALL
;
700 /* Enable All Initiator Interrupts */
701 tx4927_pcicptr
->g2pmask
= TX4927_PCIC_G2PSTATUS_ALL
;
702 /* Clear All PCI Status Error */
703 tx4927_pcicptr
->pcistatus
=
704 (tx4927_pcicptr
->pcistatus
& 0x0000ffff) |
705 (TX4927_PCIC_PCISTATUS_ALL
<< 16);
706 /* Enable All PCI Status Error Interrupts */
707 tx4927_pcicptr
->pcimask
= TX4927_PCIC_PCISTATUS_ALL
;
709 /* PCIC Int => IRC IRQ16 */
710 tx4927_pcicptr
->pcicfg2
=
711 (tx4927_pcicptr
->pcicfg2
& 0xffffff00) | TX4927_IR_PCIC
;
713 if (!(tx4927_ccfgptr
->ccfg
& TX4927_CCFG_PCIXARB
)) {
716 /* Reset Bus Arbiter */
717 tx4927_pcicptr
->pbacfg
= TX4927_PCIC_PBACFG_RPBA
;
718 /* Enable Bus Arbiter */
719 tx4927_pcicptr
->pbacfg
= TX4927_PCIC_PBACFG_PBAEN
;
722 tx4927_pcicptr
->pcistatus
= PCI_COMMAND_MASTER
|
724 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
726 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
,
727 ":pci setup complete:\n");
728 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2
, "+\n");
731 #endif /* CONFIG_PCI */
733 void toshiba_rbtx4927_restart(char *command
)
735 printk(KERN_NOTICE
"System Rebooting...\n");
737 /* enable the s/w reset register */
738 reg_wr08(RBTX4927_SW_RESET_ENABLE
, RBTX4927_SW_RESET_ENABLE_SET
);
740 /* wait for enable to be seen */
741 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE
) &
742 RBTX4927_SW_RESET_ENABLE_SET
) == 0x00);
745 reg_wr08(RBTX4927_SW_RESET_DO
, RBTX4927_SW_RESET_DO_SET
);
747 /* do something passive while waiting for reset */
756 void toshiba_rbtx4927_halt(void)
758 printk(KERN_NOTICE
"System Halted\n");
766 void toshiba_rbtx4927_power_off(void)
768 toshiba_rbtx4927_halt();
772 void __init
toshiba_rbtx4927_setup(void)
777 printk("CPU is %s\n", toshiba_name
);
779 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
782 /* f/w leaves this on at startup */
783 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
784 ":Clearing STO_ERL.\n");
785 clear_c0_status(ST0_ERL
);
787 /* enable caches -- HCP5 does this, pmon does not */
788 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
789 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
790 cp0_config
= read_c0_config();
791 cp0_config
= cp0_config
& ~(TX49_CONF_IC
| TX49_CONF_DC
);
792 write_c0_config(cp0_config
);
794 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
796 extern void dump_cp0(char *);
797 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
801 /* setup irq stuff */
802 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
803 ":Setting up tx4927 pic.\n");
804 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
805 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
807 /* setup serial stuff */
808 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
809 ":Setting up tx4927 sio.\n");
810 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
811 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
813 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
816 set_io_port_base(KSEG1
+ TBTX4927_ISA_IO_OFFSET
);
817 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
818 ":mips_io_port_base=0x%08lx\n",
821 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
823 ioport_resource
.end
= 0xffffffff;
824 iomem_resource
.end
= 0xffffffff;
826 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
828 _machine_restart
= toshiba_rbtx4927_restart
;
829 _machine_halt
= toshiba_rbtx4927_halt
;
830 pm_power_off
= toshiba_rbtx4927_power_off
;
836 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
839 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
840 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
841 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
842 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
843 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
844 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
847 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
848 * PCIDIVMODE[10] is 0.
849 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
850 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
851 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
852 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
853 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
854 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
857 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1
,
858 "ccfg is %lx, PCIDIVMODE is %x\n",
859 (unsigned long) tx4927_ccfgptr
->ccfg
,
860 (unsigned long) tx4927_ccfgptr
->ccfg
&
861 (mips_machtype
== MACH_TOSHIBA_RBTX4937
?
862 TX4937_CCFG_PCIDIVMODE_MASK
:
863 TX4927_CCFG_PCIDIVMODE_MASK
));
865 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1
,
866 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
867 (unsigned long) tx4927_ccfgptr
->
868 ccfg
& TX4927_CCFG_PCI66
,
869 (unsigned long) tx4927_ccfgptr
->
870 ccfg
& TX4927_CCFG_PCIMIDE
,
871 (unsigned long) tx4927_ccfgptr
->
872 ccfg
& TX4927_CCFG_PCIXARB
);
874 if (mips_machtype
== MACH_TOSHIBA_RBTX4937
)
875 switch ((unsigned long)tx4927_ccfgptr
->
876 ccfg
& TX4937_CCFG_PCIDIVMODE_MASK
) {
877 case TX4937_CCFG_PCIDIVMODE_8
:
878 case TX4937_CCFG_PCIDIVMODE_4
:
879 tx4927_cpu_clock
= 266666666; /* 266MHz */
881 case TX4937_CCFG_PCIDIVMODE_9
:
882 case TX4937_CCFG_PCIDIVMODE_4_5
:
883 tx4927_cpu_clock
= 300000000; /* 300MHz */
886 tx4927_cpu_clock
= 333333333; /* 333MHz */
889 switch ((unsigned long)tx4927_ccfgptr
->
890 ccfg
& TX4927_CCFG_PCIDIVMODE_MASK
) {
891 case TX4927_CCFG_PCIDIVMODE_2_5
:
892 case TX4927_CCFG_PCIDIVMODE_5
:
893 tx4927_cpu_clock
= 166666666; /* 166MHz */
896 tx4927_cpu_clock
= 200000000; /* 200MHz */
900 /* enable Timeout BusError */
901 if (tx4927_ccfg_toeon
)
902 tx4927_ccfgptr
->ccfg
|= TX4927_CCFG_TOE
;
905 if (tx4927_using_backplane
== 1)
906 printk("backplane board IS installed\n");
908 printk("No Backplane \n");
910 /* this is on ISA bus behind PCI bus, so need PCI up first */
911 #ifdef CONFIG_TOSHIBA_FPCIB0
913 if (tx4927_using_backplane
) {
914 TOSHIBA_RBTX4927_SETUP_DPRINTK
915 (TOSHIBA_RBTX4927_SETUP_SETUP
,
918 TOSHIBA_RBTX4927_SETUP_DPRINTK
919 (TOSHIBA_RBTX4927_SETUP_SETUP
,
920 ":smsc_fdc37m81x_init()\n");
921 smsc_fdc37m81x_init(0x3f0);
923 TOSHIBA_RBTX4927_SETUP_DPRINTK
924 (TOSHIBA_RBTX4927_SETUP_SETUP
,
925 ":smsc_fdc37m81x_config_beg()\n");
926 smsc_fdc37m81x_config_beg();
928 TOSHIBA_RBTX4927_SETUP_DPRINTK
929 (TOSHIBA_RBTX4927_SETUP_SETUP
,
930 ":smsc_fdc37m81x_config_set(KBD)\n");
931 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM
,
933 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT
, 1);
934 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2
, 12);
935 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE
,
938 smsc_fdc37m81x_config_end();
939 TOSHIBA_RBTX4927_SETUP_DPRINTK
940 (TOSHIBA_RBTX4927_SETUP_SETUP
,
941 ":smsc_fdc37m81x_config_end()\n");
943 TOSHIBA_RBTX4927_SETUP_DPRINTK
944 (TOSHIBA_RBTX4927_SETUP_SETUP
,
945 ":fpcibo=not_found\n");
950 TOSHIBA_RBTX4927_SETUP_DPRINTK
951 (TOSHIBA_RBTX4927_SETUP_SETUP
, ":fpcibo=no\n");
955 #endif /* CONFIG_PCI */
957 #ifdef CONFIG_SERIAL_TXX9
959 extern int early_serial_txx9_setup(struct uart_port
*port
);
961 struct uart_port req
;
962 for(i
= 0; i
< 2; i
++) {
963 memset(&req
, 0, sizeof(req
));
965 req
.iotype
= UPIO_MEM
;
966 req
.membase
= (char *)(0xff1ff300 + i
* 0x100);
967 req
.mapbase
= 0xff1ff300 + i
* 0x100;
969 req
.flags
|= UPF_BUGGY_UART
/*HAVE_CTS_LINE*/;
970 req
.uartclk
= 50000000;
971 early_serial_txx9_setup(&req
);
974 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
975 argptr
= prom_getcmdline();
976 if (strstr(argptr
, "console=") == NULL
) {
977 strcat(argptr
, " console=ttyS0,38400");
982 #ifdef CONFIG_ROOT_NFS
983 argptr
= prom_getcmdline();
984 if (strstr(argptr
, "root=") == NULL
) {
985 strcat(argptr
, " root=/dev/nfs rw");
991 argptr
= prom_getcmdline();
992 if (strstr(argptr
, "ip=") == NULL
) {
993 strcat(argptr
, " ip=any");
998 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP
,
1003 toshiba_rbtx4927_time_init(void)
1005 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT
, "-\n");
1007 mips_hpt_frequency
= tx4927_cpu_clock
/ 2;
1009 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT
, "+\n");
1013 void __init
toshiba_rbtx4927_timer_setup(struct irqaction
*irq
)
1015 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
,
1017 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
,
1021 static int __init
toshiba_rbtx4927_rtc_init(void)
1023 struct resource res
= {
1024 .start
= 0x1c010000,
1025 .end
= 0x1c010000 + 0x800 - 1,
1026 .flags
= IORESOURCE_MEM
,
1028 struct platform_device
*dev
=
1029 platform_device_register_simple("ds1742", -1, &res
, 1);
1030 return IS_ERR(dev
) ? PTR_ERR(dev
) : 0;
1032 device_initcall(toshiba_rbtx4927_rtc_init
);
1034 static int __init
rbtx4927_ne_init(void)
1036 static struct resource __initdata res
[] = {
1038 .start
= RBTX4927_RTL_8019_BASE
,
1039 .end
= RBTX4927_RTL_8019_BASE
+ 0x20 - 1,
1040 .flags
= IORESOURCE_IO
,
1042 .start
= RBTX4927_RTL_8019_IRQ
,
1043 .flags
= IORESOURCE_IRQ
,
1046 struct platform_device
*dev
=
1047 platform_device_register_simple("ne", -1,
1048 res
, ARRAY_SIZE(res
));
1049 return IS_ERR(dev
) ? PTR_ERR(dev
) : 0;
1051 device_initcall(rbtx4927_ne_init
);