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[MTD] [NAND] TXx9: add NDFMC support
[deliverable/linux.git] / arch / mips / txx9 / generic / setup_tx4939.c
1 /*
2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/netdevice.h>
17 #include <linux/notifier.h>
18 #include <linux/sysdev.h>
19 #include <linux/ethtool.h>
20 #include <linux/param.h>
21 #include <linux/ptrace.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/platform_device.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
26 #include <asm/traps.h>
27 #include <asm/txx9irq.h>
28 #include <asm/txx9tmr.h>
29 #include <asm/txx9/generic.h>
30 #include <asm/txx9/ndfmc.h>
31 #include <asm/txx9/tx4939.h>
32
33 static void __init tx4939_wdr_init(void)
34 {
35 /* report watchdog reset status */
36 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
37 pr_warning("Watchdog reset detected at 0x%lx\n",
38 read_c0_errorepc());
39 /* clear WatchDogReset (W1C) */
40 tx4939_ccfg_set(TX4939_CCFG_WDRST);
41 /* do reset on watchdog */
42 tx4939_ccfg_set(TX4939_CCFG_WR);
43 }
44
45 void __init tx4939_wdt_init(void)
46 {
47 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
48 }
49
50 static void tx4939_machine_restart(char *command)
51 {
52 local_irq_disable();
53 pr_emerg("Rebooting (with %s watchdog reset)...\n",
54 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
55 "external" : "internal");
56 /* clear watchdog status */
57 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
58 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
59 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
60 ;
61 mdelay(10);
62 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
63 pr_emerg("Rebooting (with internal watchdog reset)...\n");
64 /* External WDRST failed. Do internal watchdog reset */
65 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
66 }
67 /* fallback */
68 (*_machine_halt)();
69 }
70
71 void show_registers(struct pt_regs *regs);
72 static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
73 {
74 int data = regs->cp0_cause & 4;
75 console_verbose();
76 pr_err("%cBE exception at %#lx\n",
77 data ? 'D' : 'I', regs->cp0_epc);
78 pr_err("ccfg:%llx, toea:%llx\n",
79 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
80 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
81 #ifdef CONFIG_PCI
82 tx4927_report_pcic_status();
83 #endif
84 show_registers(regs);
85 panic("BusError!");
86 }
87 static void __init tx4939_be_init(void)
88 {
89 board_be_handler = tx4939_be_handler;
90 }
91
92 static struct resource tx4939_sdram_resource[4];
93 static struct resource tx4939_sram_resource;
94 #define TX4939_SRAM_SIZE 0x800
95
96 void __init tx4939_add_memory_regions(void)
97 {
98 int i;
99 unsigned long start, size;
100 u64 win;
101
102 for (i = 0; i < 4; i++) {
103 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
104 continue;
105 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
106 start = (unsigned long)(win >> 48);
107 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
108 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
109 }
110 }
111
112 void __init tx4939_setup(void)
113 {
114 int i;
115 __u32 divmode;
116 __u64 pcfg;
117 int cpuclk = 0;
118
119 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
120 TX4939_REG_SIZE);
121 set_c0_config(TX49_CONF_CWFON);
122
123 /* SDRAMC,EBUSC are configured by PROM */
124 for (i = 0; i < 4; i++) {
125 if (!(TX4939_EBUSC_CR(i) & 0x8))
126 continue; /* disabled */
127 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
128 txx9_ce_res[i].end =
129 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
130 request_resource(&iomem_resource, &txx9_ce_res[i]);
131 }
132
133 /* clocks */
134 if (txx9_master_clock) {
135 /* calculate cpu_clock from master_clock */
136 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
137 TX4939_CCFG_MULCLK_MASK;
138 cpuclk = txx9_master_clock * 20 / 2;
139 switch (divmode) {
140 case TX4939_CCFG_MULCLK_8:
141 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
142 case TX4939_CCFG_MULCLK_9:
143 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
144 case TX4939_CCFG_MULCLK_10:
145 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
146 case TX4939_CCFG_MULCLK_11:
147 cpuclk = cpuclk / 6 * 11; break;
148 case TX4939_CCFG_MULCLK_12:
149 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
150 case TX4939_CCFG_MULCLK_13:
151 cpuclk = cpuclk / 6 * 13; break;
152 case TX4939_CCFG_MULCLK_14:
153 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
154 case TX4939_CCFG_MULCLK_15:
155 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
156 }
157 txx9_cpu_clock = cpuclk;
158 } else {
159 if (txx9_cpu_clock == 0)
160 txx9_cpu_clock = 400000000; /* 400MHz */
161 /* calculate master_clock from cpu_clock */
162 cpuclk = txx9_cpu_clock;
163 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
164 TX4939_CCFG_MULCLK_MASK;
165 switch (divmode) {
166 case TX4939_CCFG_MULCLK_8:
167 txx9_master_clock = cpuclk * 6 / 8; break;
168 case TX4939_CCFG_MULCLK_9:
169 txx9_master_clock = cpuclk * 6 / 9; break;
170 case TX4939_CCFG_MULCLK_10:
171 txx9_master_clock = cpuclk * 6 / 10; break;
172 case TX4939_CCFG_MULCLK_11:
173 txx9_master_clock = cpuclk * 6 / 11; break;
174 case TX4939_CCFG_MULCLK_12:
175 txx9_master_clock = cpuclk * 6 / 12; break;
176 case TX4939_CCFG_MULCLK_13:
177 txx9_master_clock = cpuclk * 6 / 13; break;
178 case TX4939_CCFG_MULCLK_14:
179 txx9_master_clock = cpuclk * 6 / 14; break;
180 case TX4939_CCFG_MULCLK_15:
181 txx9_master_clock = cpuclk * 6 / 15; break;
182 }
183 txx9_master_clock /= 10; /* * 2 / 20 */
184 }
185 /* calculate gbus_clock from cpu_clock */
186 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
187 TX4939_CCFG_YDIVMODE_MASK;
188 txx9_gbus_clock = txx9_cpu_clock;
189 switch (divmode) {
190 case TX4939_CCFG_YDIVMODE_2:
191 txx9_gbus_clock /= 2; break;
192 case TX4939_CCFG_YDIVMODE_3:
193 txx9_gbus_clock /= 3; break;
194 case TX4939_CCFG_YDIVMODE_5:
195 txx9_gbus_clock /= 5; break;
196 case TX4939_CCFG_YDIVMODE_6:
197 txx9_gbus_clock /= 6; break;
198 }
199 /* change default value to udelay/mdelay take reasonable time */
200 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
201
202 /* CCFG */
203 tx4939_wdr_init();
204 /* clear BusErrorOnWrite flag (W1C) */
205 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
206 /* enable Timeout BusError */
207 if (txx9_ccfg_toeon)
208 tx4939_ccfg_set(TX4939_CCFG_TOE);
209
210 /* DMA selection */
211 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
212
213 /* Use external clock for external arbiter */
214 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
215 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
216
217 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
218 txx9_pcode_str,
219 (cpuclk + 500000) / 1000000,
220 (txx9_master_clock + 500000) / 1000000,
221 (txx9_gbus_clock + 500000) / 1000000,
222 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
223 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
224 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
225
226 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
227 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
228 for (i = 0; i < 4; i++) {
229 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
230 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
231 continue; /* disabled */
232 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
233 tx4939_sdram_resource[i].name = "DDR SDRAM";
234 tx4939_sdram_resource[i].start =
235 (unsigned long)(win >> 48) << 20;
236 tx4939_sdram_resource[i].end =
237 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
238 20) - 1;
239 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
240 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
241 }
242 printk(KERN_CONT "\n");
243
244 /* SRAM */
245 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
246 unsigned int size = TX4939_SRAM_SIZE;
247 tx4939_sram_resource.name = "SRAM";
248 tx4939_sram_resource.start =
249 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
250 & ~(size - 1);
251 tx4939_sram_resource.end =
252 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
253 tx4939_sram_resource.flags = IORESOURCE_MEM;
254 request_resource(&iomem_resource, &tx4939_sram_resource);
255 }
256
257 /* TMR */
258 /* disable all timers */
259 for (i = 0; i < TX4939_NR_TMR; i++)
260 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
261
262 /* DMA */
263 for (i = 0; i < 2; i++)
264 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
265 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
266
267 /* set PCIC1 reset (required to prevent hangup on BIST) */
268 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
269 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
270 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
271 mdelay(1); /* at least 128 cpu clock */
272 /* clear PCIC1 reset */
273 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
274 } else {
275 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
276 /* stop PCIC1 */
277 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
278 }
279 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
280 pr_info("%s: stop ETH0\n", txx9_pcode_str);
281 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
282 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
283 }
284 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
285 pr_info("%s: stop ETH1\n", txx9_pcode_str);
286 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
287 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
288 }
289
290 _machine_restart = tx4939_machine_restart;
291 board_be_init = tx4939_be_init;
292 }
293
294 void __init tx4939_time_init(unsigned int tmrnr)
295 {
296 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
297 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
298 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
299 TXX9_IMCLK);
300 }
301
302 void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
303 {
304 int i;
305 unsigned int ch_mask = 0;
306 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
307
308 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
309 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
310 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
311 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
312 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
313 if (pcfg & TX4939_PCFG_SIO3MODE)
314 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
315 for (i = 0; i < 4; i++) {
316 if ((1 << i) & ch_mask)
317 continue;
318 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
319 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
320 i, sclk, (1 << i) & cts_mask);
321 }
322 }
323
324 #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
325 static int tx4939_get_eth_speed(struct net_device *dev)
326 {
327 struct ethtool_cmd cmd = { ETHTOOL_GSET };
328 int speed = 100; /* default 100Mbps */
329 int err;
330 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
331 return speed;
332 err = dev->ethtool_ops->get_settings(dev, &cmd);
333 if (err < 0)
334 return speed;
335 speed = cmd.speed == SPEED_100 ? 100 : 10;
336 return speed;
337 }
338 static int tx4939_netdev_event(struct notifier_block *this,
339 unsigned long event,
340 void *ptr)
341 {
342 struct net_device *dev = ptr;
343 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
344 __u64 bit = 0;
345 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
346 bit = TX4939_PCFG_SPEED0;
347 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
348 bit = TX4939_PCFG_SPEED1;
349 if (bit) {
350 int speed = tx4939_get_eth_speed(dev);
351 if (speed == 100)
352 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
353 else
354 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
355 }
356 }
357 return NOTIFY_DONE;
358 }
359
360 static struct notifier_block tx4939_netdev_notifier = {
361 .notifier_call = tx4939_netdev_event,
362 .priority = 1,
363 };
364
365 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
366 {
367 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
368
369 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
370 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
371 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
372 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
373 register_netdevice_notifier(&tx4939_netdev_notifier);
374 }
375 #else
376 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
377 {
378 }
379 #endif
380
381 void __init tx4939_mtd_init(int ch)
382 {
383 struct physmap_flash_data pdata = {
384 .width = TX4939_EBUSC_WIDTH(ch) / 8,
385 };
386 unsigned long start = txx9_ce_res[ch].start;
387 unsigned long size = txx9_ce_res[ch].end - start + 1;
388
389 if (!(TX4939_EBUSC_CR(ch) & 0x8))
390 return; /* disabled */
391 txx9_physmap_flash_init(ch, start, size, &pdata);
392 }
393
394 #define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
395 void __init tx4939_ata_init(void)
396 {
397 static struct resource ata0_res[] = {
398 {
399 .start = TX4939_ATA_REG_PHYS(0),
400 .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
401 .flags = IORESOURCE_MEM,
402 }, {
403 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
404 .flags = IORESOURCE_IRQ,
405 },
406 };
407 static struct resource ata1_res[] = {
408 {
409 .start = TX4939_ATA_REG_PHYS(1),
410 .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
411 .flags = IORESOURCE_MEM,
412 }, {
413 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
414 .flags = IORESOURCE_IRQ,
415 },
416 };
417 static struct platform_device ata0_dev = {
418 .name = "tx4939ide",
419 .id = 0,
420 .num_resources = ARRAY_SIZE(ata0_res),
421 .resource = ata0_res,
422 };
423 static struct platform_device ata1_dev = {
424 .name = "tx4939ide",
425 .id = 1,
426 .num_resources = ARRAY_SIZE(ata1_res),
427 .resource = ata1_res,
428 };
429 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
430
431 if (pcfg & TX4939_PCFG_ATA0MODE)
432 platform_device_register(&ata0_dev);
433 if ((pcfg & (TX4939_PCFG_ATA1MODE |
434 TX4939_PCFG_ET1MODE |
435 TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
436 platform_device_register(&ata1_dev);
437 }
438
439 void __init tx4939_rtc_init(void)
440 {
441 static struct resource res[] = {
442 {
443 .start = TX4939_RTC_REG & 0xfffffffffULL,
444 .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
445 .flags = IORESOURCE_MEM,
446 }, {
447 .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
448 .flags = IORESOURCE_IRQ,
449 },
450 };
451 static struct platform_device rtc_dev = {
452 .name = "tx4939rtc",
453 .id = -1,
454 .num_resources = ARRAY_SIZE(res),
455 .resource = res,
456 };
457
458 platform_device_register(&rtc_dev);
459 }
460
461 void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
462 unsigned char ch_mask, unsigned char wide_mask)
463 {
464 struct txx9ndfmc_platform_data plat_data = {
465 .shift = 1,
466 .gbus_clock = txx9_gbus_clock,
467 .hold = hold,
468 .spw = spw,
469 .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
470 NDFMC_PLAT_FLAG_DUMMYWRITE,
471 .ch_mask = ch_mask,
472 .wide_mask = wide_mask,
473 };
474 txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
475 }
476
477 static void __init tx4939_stop_unused_modules(void)
478 {
479 __u64 pcfg, rst = 0, ckd = 0;
480 char buf[128];
481
482 buf[0] = '\0';
483 local_irq_disable();
484 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
485 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
486 TX4939_PCFG_I2SMODE_ACLC) {
487 rst |= TX4939_CLKCTR_ACLRST;
488 ckd |= TX4939_CLKCTR_ACLCKD;
489 strcat(buf, " ACLC");
490 }
491 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
492 TX4939_PCFG_I2SMODE_I2S &&
493 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
494 TX4939_PCFG_I2SMODE_I2S_ALT) {
495 rst |= TX4939_CLKCTR_I2SRST;
496 ckd |= TX4939_CLKCTR_I2SCKD;
497 strcat(buf, " I2S");
498 }
499 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
500 rst |= TX4939_CLKCTR_ATA0RST;
501 ckd |= TX4939_CLKCTR_ATA0CKD;
502 strcat(buf, " ATA0");
503 }
504 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
505 rst |= TX4939_CLKCTR_ATA1RST;
506 ckd |= TX4939_CLKCTR_ATA1CKD;
507 strcat(buf, " ATA1");
508 }
509 if (pcfg & TX4939_PCFG_SPIMODE) {
510 rst |= TX4939_CLKCTR_SPIRST;
511 ckd |= TX4939_CLKCTR_SPICKD;
512 strcat(buf, " SPI");
513 }
514 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
515 rst |= TX4939_CLKCTR_VPCRST;
516 ckd |= TX4939_CLKCTR_VPCCKD;
517 strcat(buf, " VPC");
518 }
519 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
520 rst |= TX4939_CLKCTR_SIO2RST;
521 ckd |= TX4939_CLKCTR_SIO2CKD;
522 strcat(buf, " SIO2");
523 }
524 if (pcfg & TX4939_PCFG_SIO3MODE) {
525 rst |= TX4939_CLKCTR_SIO3RST;
526 ckd |= TX4939_CLKCTR_SIO3CKD;
527 strcat(buf, " SIO3");
528 }
529 if (rst | ckd) {
530 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
531 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
532 }
533 local_irq_enable();
534 if (buf[0])
535 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
536 }
537
538 static int __init tx4939_late_init(void)
539 {
540 if (txx9_pcode != 0x4939)
541 return -ENODEV;
542 tx4939_stop_unused_modules();
543 return 0;
544 }
545 late_initcall(tx4939_late_init);
Linux kernel - Deliverables
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