arch/mips/txx9/jmr3927/setup.c

   1 /*
   2  *  This program is free software; you can redistribute  it and/or modify it
   3  *  under  the terms of  the GNU General  Public License as published by the
   4  *  Free Software Foundation;  either version 2 of the  License, or (at your
   5  *  option) any later version.
   6  *
   7  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
   8  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
   9  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  10  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  11  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  12  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  13  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  14  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  15  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  16  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  17  *
  18  *  You should have received a copy of the  GNU General Public License along
  19  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  20  *  675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Copyright 2001 MontaVista Software Inc.
  23  * Author: MontaVista Software, Inc.
  24  *              ahennessy@mvista.com
  25  *
  26  * Copyright (C) 2000-2001 Toshiba Corporation
  27  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/types.h>
  33 #include <linux/ioport.h>
  34 #include <linux/delay.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/gpio.h>
  37 #ifdef CONFIG_SERIAL_TXX9
  38 #include <linux/serial_core.h>
  39 #endif
  40 #include <asm/txx9tmr.h>
  41 #include <asm/txx9pio.h>
  42 #include <asm/reboot.h>
  43 #include <asm/txx9/generic.h>
  44 #include <asm/txx9/pci.h>
  45 #include <asm/txx9/jmr3927.h>
  46 #include <asm/mipsregs.h>
  47
  48 /* don't enable - see errata */
  49 static int jmr3927_ccfg_toeon;
  50
  51 static void jmr3927_machine_restart(char *command)
  52 {
  53         local_irq_disable();
  54 #if 1   /* Resetting PCI bus */
  55         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  56         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
  57         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
  58         mdelay(1);
  59         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  60 #endif
  61         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
  62         /* fallback */
  63         (*_machine_halt)();
  64 }
  65
  66 static void __init jmr3927_time_init(void)
  67 {
  68         txx9_clockevent_init(TX3927_TMR_REG(0),
  69                              JMR3927_IRQ_IRC_TMR(0),
  70                              JMR3927_IMCLK);
  71         txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
  72 }
  73
  74 #define DO_WRITE_THROUGH
  75 #define DO_ENABLE_CACHE
  76
  77 static void jmr3927_board_init(void);
  78
  79 static void __init jmr3927_mem_setup(void)
  80 {
  81         char *argptr;
  82
  83         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
  84
  85         _machine_restart = jmr3927_machine_restart;
  86
  87         /* Reboot on panic */
  88         panic_timeout = 180;
  89
  90         /* cache setup */
  91         {
  92                 unsigned int conf;
  93 #ifdef DO_ENABLE_CACHE
  94                 int mips_ic_disable = 0, mips_dc_disable = 0;
  95 #else
  96                 int mips_ic_disable = 1, mips_dc_disable = 1;
  97 #endif
  98 #ifdef DO_WRITE_THROUGH
  99                 int mips_config_cwfon = 0;
 100                 int mips_config_wbon = 0;
 101 #else
 102                 int mips_config_cwfon = 1;
 103                 int mips_config_wbon = 1;
 104 #endif
 105
 106                 conf = read_c0_conf();
 107                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 108                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 109                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 110                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 111                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 112
 113                 write_c0_conf(conf);
 114                 write_c0_cache(0);
 115         }
 116
 117         /* initialize board */
 118         jmr3927_board_init();
 119
 120         argptr = prom_getcmdline();
 121
 122         if ((argptr = strstr(argptr, "toeon")) != NULL)
 123                 jmr3927_ccfg_toeon = 1;
 124         argptr = prom_getcmdline();
 125         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 126                 argptr = prom_getcmdline();
 127                 strcat(argptr, " ip=bootp");
 128         }
 129
 130 #ifdef CONFIG_SERIAL_TXX9
 131         {
 132                 extern int early_serial_txx9_setup(struct uart_port *port);
 133                 int i;
 134                 struct uart_port req;
 135                 for(i = 0; i < 2; i++) {
 136                         memset(&req, 0, sizeof(req));
 137                         req.line = i;
 138                         req.iotype = UPIO_MEM;
 139                         req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
 140                         req.mapbase = TX3927_SIO_REG(i);
 141                         req.irq = i == 0 ?
 142                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 143                         if (i == 0)
 144                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 145                         req.uartclk = JMR3927_IMCLK;
 146                         early_serial_txx9_setup(&req);
 147                 }
 148         }
 149 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 150         argptr = prom_getcmdline();
 151         if ((argptr = strstr(argptr, "console=")) == NULL) {
 152                 argptr = prom_getcmdline();
 153                 strcat(argptr, " console=ttyS1,115200");
 154         }
 155 #endif
 156 #endif
 157 }
 158
 159 static void tx3927_setup(void);
 160
 161 static void __init jmr3927_pci_setup(void)
 162 {
 163 #ifdef CONFIG_PCI
 164         int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
 165         struct pci_controller *c;
 166
 167         c = txx9_alloc_pci_controller(&txx9_primary_pcic,
 168                                       JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
 169                                       JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
 170         register_pci_controller(c);
 171         if (!extarb) {
 172                 /* Reset PCI Bus */
 173                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 174                 udelay(100);
 175                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 176                                     JMR3927_IOC_RESET_ADDR);
 177                 udelay(100);
 178                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 179         }
 180         tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
 181         tx3927_setup_pcierr_irq();
 182 #endif /* CONFIG_PCI */
 183 }
 184
 185 static void __init jmr3927_board_init(void)
 186 {
 187         tx3927_setup();
 188         jmr3927_pci_setup();
 189
 190         /* SIO0 DTR on */
 191         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 192
 193         jmr3927_led_set(0);
 194
 195         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 196                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 197                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 198                jmr3927_dipsw1(), jmr3927_dipsw2(),
 199                jmr3927_dipsw3(), jmr3927_dipsw4());
 200 }
 201
 202 static void __init tx3927_setup(void)
 203 {
 204         int i;
 205
 206         txx9_cpu_clock = JMR3927_CORECLK;
 207         txx9_gbus_clock = JMR3927_GBUSCLK;
 208         /* SDRAMC are configured by PROM */
 209
 210         /* ROMC */
 211         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 212         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 213         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 214         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 215
 216         /* CCFG */
 217         /* enable Timeout BusError */
 218         if (jmr3927_ccfg_toeon)
 219                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 220
 221         /* clear BusErrorOnWrite flag */
 222         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 223         /* Disable PCI snoop */
 224         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 225         /* do reset on watchdog */
 226         tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
 227
 228 #ifdef DO_WRITE_THROUGH
 229         /* Enable PCI SNOOP - with write through only */
 230         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 231 #endif
 232
 233         /* Pin selection */
 234         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 235         tx3927_ccfgptr->pcfg |=
 236                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 237                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 238
 239         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 240                tx3927_ccfgptr->crir,
 241                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 242
 243         /* TMR */
 244         for (i = 0; i < TX3927_NR_TMR; i++)
 245                 txx9_tmr_init(TX3927_TMR_REG(i));
 246
 247         /* DMA */
 248         tx3927_dmaptr->mcr = 0;
 249         for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
 250                 /* reset channel */
 251                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 252                 tx3927_dmaptr->ch[i].ccr = 0;
 253         }
 254         /* enable DMA */
 255 #ifdef __BIG_ENDIAN
 256         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 257 #else
 258         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 259 #endif
 260
 261         /* PIO */
 262         /* PIO[15:12] connected to LEDs */
 263         __raw_writel(0x0000f000, &tx3927_pioptr->dir);
 264         __raw_writel(0, &tx3927_pioptr->maskcpu);
 265         __raw_writel(0, &tx3927_pioptr->maskext);
 266         txx9_gpio_init(TX3927_PIO_REG, 0, 16);
 267         gpio_request(11, "dipsw1");
 268         gpio_request(10, "dipsw2");
 269         {
 270                 unsigned int conf;
 271
 272         conf = read_c0_conf();
 273                if (!(conf & TX39_CONF_ICE))
 274                        printk("TX3927 I-Cache disabled.\n");
 275                if (!(conf & TX39_CONF_DCE))
 276                        printk("TX3927 D-Cache disabled.\n");
 277                else if (!(conf & TX39_CONF_WBON))
 278                        printk("TX3927 D-Cache WriteThrough.\n");
 279                else if (!(conf & TX39_CONF_CWFON))
 280                        printk("TX3927 D-Cache WriteBack.\n");
 281                else
 282                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 283         }
 284 }
 285
 286 /* This trick makes rtc-ds1742 driver usable as is. */
 287 static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
 288 {
 289         if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
 290                 return port;
 291         port = (port & 0xffff0000) | (port & 0x7fff << 1);
 292 #ifdef __BIG_ENDIAN
 293         return port;
 294 #else
 295         return port | 1;
 296 #endif
 297 }
 298
 299 static int __init jmr3927_rtc_init(void)
 300 {
 301         static struct resource __initdata res = {
 302                 .start  = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
 303                 .end    = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
 304                 .flags  = IORESOURCE_MEM,
 305         };
 306         struct platform_device *dev;
 307         dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 308         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 309 }
 310
 311 /* Watchdog support */
 312
 313 static int __init txx9_wdt_init(unsigned long base)
 314 {
 315         struct resource res = {
 316                 .start  = base,
 317                 .end    = base + 0x100 - 1,
 318                 .flags  = IORESOURCE_MEM,
 319         };
 320         struct platform_device *dev =
 321                 platform_device_register_simple("txx9wdt", -1, &res, 1);
 322         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 323 }
 324
 325 static int __init jmr3927_wdt_init(void)
 326 {
 327         return txx9_wdt_init(TX3927_TMR_REG(2));
 328 }
 329
 330 static void __init jmr3927_device_init(void)
 331 {
 332         __swizzle_addr_b = jmr3927_swizzle_addr_b;
 333         jmr3927_rtc_init();
 334         jmr3927_wdt_init();
 335 }
 336
 337 struct txx9_board_vec jmr3927_vec __initdata = {
 338         .system = "Toshiba JMR_TX3927",
 339         .prom_init = jmr3927_prom_init,
 340         .mem_setup = jmr3927_mem_setup,
 341         .irq_setup = jmr3927_irq_setup,
 342         .time_init = jmr3927_time_init,
 343         .device_init = jmr3927_device_init,
 344 #ifdef CONFIG_PCI
 345         .pci_map_irq = jmr3927_pci_map_irq,
 346 #endif
 347 };