arch/mips/txx9/rbtx4927/irq.c

   1 /*
   2  * Toshiba RBTX4927 specific interrupt handlers
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  19  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  20  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  21  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  22  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  23  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the GNU General Public License along
  26  *  with this program; if not, write to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29 /*
  30 IRQ  Device
  31 00   RBTX4927-ISA/00
  32 01   RBTX4927-ISA/01 PS2/Keyboard
  33 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
  34 03   RBTX4927-ISA/03
  35 04   RBTX4927-ISA/04
  36 05   RBTX4927-ISA/05
  37 06   RBTX4927-ISA/06
  38 07   RBTX4927-ISA/07
  39 08   RBTX4927-ISA/08
  40 09   RBTX4927-ISA/09
  41 10   RBTX4927-ISA/10
  42 11   RBTX4927-ISA/11
  43 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
  44 13   RBTX4927-ISA/13
  45 14   RBTX4927-ISA/14 IDE
  46 15   RBTX4927-ISA/15
  47
  48 16   TX4927-CP0/00 Software 0
  49 17   TX4927-CP0/01 Software 1
  50 18   TX4927-CP0/02 Cascade TX4927-CP0
  51 19   TX4927-CP0/03 Multiplexed -- do not use
  52 20   TX4927-CP0/04 Multiplexed -- do not use
  53 21   TX4927-CP0/05 Multiplexed -- do not use
  54 22   TX4927-CP0/06 Multiplexed -- do not use
  55 23   TX4927-CP0/07 CPU TIMER
  56
  57 24   TX4927-PIC/00
  58 25   TX4927-PIC/01
  59 26   TX4927-PIC/02
  60 27   TX4927-PIC/03 Cascade RBTX4927-IOC
  61 28   TX4927-PIC/04
  62 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
  63 30   TX4927-PIC/06
  64 31   TX4927-PIC/07
  65 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
  66 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
  67 34   TX4927-PIC/10
  68 35   TX4927-PIC/11
  69 36   TX4927-PIC/12
  70 37   TX4927-PIC/13
  71 38   TX4927-PIC/14
  72 39   TX4927-PIC/15
  73 40   TX4927-PIC/16 TX4927 PCI PCI-C
  74 41   TX4927-PIC/17
  75 42   TX4927-PIC/18
  76 43   TX4927-PIC/19
  77 44   TX4927-PIC/20
  78 45   TX4927-PIC/21
  79 46   TX4927-PIC/22 TX4927 PCI PCI-ERR
  80 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
  81 48   TX4927-PIC/24
  82 49   TX4927-PIC/25
  83 50   TX4927-PIC/26
  84 51   TX4927-PIC/27
  85 52   TX4927-PIC/28
  86 53   TX4927-PIC/29
  87 54   TX4927-PIC/30
  88 55   TX4927-PIC/31
  89
  90 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
  91 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
  92 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
  93 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
  94 60 RBTX4927-IOC/04
  95 61 RBTX4927-IOC/05
  96 62 RBTX4927-IOC/06
  97 63 RBTX4927-IOC/07
  98
  99 NOTES:
 100 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
 101 SouthBridge/ISA/pin=0 no pci irq used by this device
 102 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
 103 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
 104 SouthBridge/PMC/pin=0 no pci irq used by this device
 105 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
 106 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
 107 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
 108 */
 109
 110 #include <linux/init.h>
 111 #include <linux/types.h>
 112 #include <linux/interrupt.h>
 113 #include <asm/io.h>
 114 #include <asm/mipsregs.h>
 115 #include <asm/txx9/generic.h>
 116 #include <asm/txx9/rbtx4927.h>
 117
 118 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
 119 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
 120
 121 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
 122 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
 123         .name = TOSHIBA_RBTX4927_IOC_NAME,
 124         .ack = toshiba_rbtx4927_irq_ioc_disable,
 125         .mask = toshiba_rbtx4927_irq_ioc_disable,
 126         .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
 127         .unmask = toshiba_rbtx4927_irq_ioc_enable,
 128 };
 129
 130 static int toshiba_rbtx4927_irq_nested(int sw_irq)
 131 {
 132         u8 level3;
 133
 134         level3 = readb(rbtx4927_imstat_addr) & 0x1f;
 135         if (level3)
 136                 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
 137         return (sw_irq);
 138 }
 139
 140 static void __init toshiba_rbtx4927_irq_ioc_init(void)
 141 {
 142         int i;
 143
 144         for (i = RBTX4927_IRQ_IOC;
 145              i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
 146                 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
 147                                          handle_level_irq);
 148         set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
 149 }
 150
 151 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
 152 {
 153         unsigned char v;
 154
 155         v = readb(rbtx4927_imask_addr);
 156         v |= (1 << (irq - RBTX4927_IRQ_IOC));
 157         writeb(v, rbtx4927_imask_addr);
 158 }
 159
 160 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
 161 {
 162         unsigned char v;
 163
 164         v = readb(rbtx4927_imask_addr);
 165         v &= ~(1 << (irq - RBTX4927_IRQ_IOC));
 166         writeb(v, rbtx4927_imask_addr);
 167         mmiowb();
 168 }
 169
 170
 171 static int rbtx4927_irq_dispatch(int pending)
 172 {
 173         int irq;
 174
 175         if (pending & STATUSF_IP7)                      /* cpu timer */
 176                 irq = MIPS_CPU_IRQ_BASE + 7;
 177         else if (pending & STATUSF_IP2) {               /* tx4927 pic */
 178                 irq = txx9_irq();
 179                 if (irq == RBTX4927_IRQ_IOCINT)
 180                         irq = toshiba_rbtx4927_irq_nested(irq);
 181         } else if (pending & STATUSF_IP0)               /* user line 0 */
 182                 irq = MIPS_CPU_IRQ_BASE + 0;
 183         else if (pending & STATUSF_IP1)                 /* user line 1 */
 184                 irq = MIPS_CPU_IRQ_BASE + 1;
 185         else
 186                 irq = -1;
 187         return irq;
 188 }
 189
 190 void __init rbtx4927_irq_setup(void)
 191 {
 192         txx9_irq_dispatch = rbtx4927_irq_dispatch;
 193         tx4927_irq_init();
 194         toshiba_rbtx4927_irq_ioc_init();
 195         /* Onboard 10M Ether: High Active */
 196         set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
 197 }