arch/mips/txx9/rbtx4938/setup.c

   1 /*
   2  * Setup pointers to hardware-dependent routines.
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/ioport.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/console.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/gpio.h>
  20
  21 #include <asm/reboot.h>
  22 #include <asm/io.h>
  23 #include <asm/txx9/generic.h>
  24 #include <asm/txx9/pci.h>
  25 #include <asm/txx9/rbtx4938.h>
  26 #include <linux/spi/spi.h>
  27 #include <asm/txx9/spi.h>
  28 #include <asm/txx9pio.h>
  29
  30 static void rbtx4938_machine_restart(char *command)
  31 {
  32         local_irq_disable();
  33         writeb(1, rbtx4938_softresetlock_addr);
  34         writeb(1, rbtx4938_sfvol_addr);
  35         writeb(1, rbtx4938_softreset_addr);
  36         /* fallback */
  37         (*_machine_halt)();
  38 }
  39
  40 static void __init rbtx4938_pci_setup(void)
  41 {
  42 #ifdef CONFIG_PCI
  43         int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
  44         struct pci_controller *c = &txx9_primary_pcic;
  45
  46         register_pci_controller(c);
  47
  48         if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
  49                 txx9_pci_option =
  50                         (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
  51                         TXX9_PCI_OPT_CLK_66; /* already configured */
  52
  53         /* Reset PCI Bus */
  54         writeb(0, rbtx4938_pcireset_addr);
  55         /* Reset PCIC */
  56         txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  57         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  58             TXX9_PCI_OPT_CLK_66)
  59                 tx4938_pciclk66_setup();
  60         mdelay(10);
  61         /* clear PCIC reset */
  62         txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  63         writeb(1, rbtx4938_pcireset_addr);
  64         iob();
  65
  66         tx4938_report_pciclk();
  67         tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  68         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  69             TXX9_PCI_OPT_CLK_AUTO &&
  70             txx9_pci66_check(c, 0, 0)) {
  71                 /* Reset PCI Bus */
  72                 writeb(0, rbtx4938_pcireset_addr);
  73                 /* Reset PCIC */
  74                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  75                 tx4938_pciclk66_setup();
  76                 mdelay(10);
  77                 /* clear PCIC reset */
  78                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  79                 writeb(1, rbtx4938_pcireset_addr);
  80                 iob();
  81                 /* Reinitialize PCIC */
  82                 tx4938_report_pciclk();
  83                 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  84         }
  85
  86         if (__raw_readq(&tx4938_ccfgptr->pcfg) &
  87             (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
  88                 /* Reset PCIC1 */
  89                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  90                 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
  91                 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
  92                       & TX4938_CCFG_PCI1DMD))
  93                         tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
  94                 mdelay(10);
  95                 /* clear PCIC1 reset */
  96                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  97                 tx4938_report_pci1clk();
  98
  99                 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
 100                 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
 101                 register_pci_controller(c);
 102                 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
 103         }
 104         tx4938_setup_pcierr_irq();
 105 #endif /* CONFIG_PCI */
 106 }
 107
 108 /* SPI support */
 109
 110 /* chip select for SPI devices */
 111 #define SEEPROM1_CS     7       /* PIO7 */
 112 #define SEEPROM2_CS     0       /* IOC */
 113 #define SEEPROM3_CS     1       /* IOC */
 114 #define SRTC_CS 2       /* IOC */
 115
 116 static int __init rbtx4938_ethaddr_init(void)
 117 {
 118 #ifdef CONFIG_PCI
 119         unsigned char dat[17];
 120         unsigned char sum;
 121         int i;
 122
 123         /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
 124         if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
 125                 printk(KERN_ERR "seeprom: read error.\n");
 126                 return -ENODEV;
 127         } else {
 128                 if (strcmp(dat, "MAC") != 0)
 129                         printk(KERN_WARNING "seeprom: bad signature.\n");
 130                 for (i = 0, sum = 0; i < sizeof(dat); i++)
 131                         sum += dat[i];
 132                 if (sum)
 133                         printk(KERN_WARNING "seeprom: bad checksum.\n");
 134         }
 135         tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
 136 #endif /* CONFIG_PCI */
 137         return 0;
 138 }
 139
 140 static void __init rbtx4938_spi_setup(void)
 141 {
 142         /* set SPI_SEL */
 143         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
 144 }
 145
 146 static struct resource rbtx4938_fpga_resource;
 147
 148 static void __init rbtx4938_time_init(void)
 149 {
 150         tx4938_time_init(0);
 151 }
 152
 153 static void __init rbtx4938_mem_setup(void)
 154 {
 155         unsigned long long pcfg;
 156         char *argptr;
 157
 158         if (txx9_master_clock == 0)
 159                 txx9_master_clock = 25000000; /* 25MHz */
 160
 161         tx4938_setup();
 162
 163 #ifdef CONFIG_PCI
 164         txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
 165         txx9_board_pcibios_setup = tx4927_pcibios_setup;
 166 #else
 167         set_io_port_base(RBTX4938_ETHER_BASE);
 168 #endif
 169
 170         tx4938_setup_serial();
 171 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 172         argptr = prom_getcmdline();
 173         if (strstr(argptr, "console=") == NULL) {
 174                 strcat(argptr, " console=ttyS0,38400");
 175         }
 176 #endif
 177
 178 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
 179         printk("PIOSEL: disabling both ata and nand selection\n");
 180         local_irq_disable();
 181         txx9_clear64(&tx4938_ccfgptr->pcfg,
 182                      TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
 183 #endif
 184
 185 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
 186         printk("PIOSEL: enabling nand selection\n");
 187         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 188         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 189 #endif
 190
 191 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
 192         printk("PIOSEL: enabling ata selection\n");
 193         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 194         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 195 #endif
 196
 197 #ifdef CONFIG_IP_PNP
 198         argptr = prom_getcmdline();
 199         if (strstr(argptr, "ip=") == NULL) {
 200                 strcat(argptr, " ip=any");
 201         }
 202 #endif
 203
 204
 205 #ifdef CONFIG_FB
 206         {
 207                 conswitchp = &dummy_con;
 208         }
 209 #endif
 210
 211         rbtx4938_spi_setup();
 212         pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);    /* updated */
 213         /* fixup piosel */
 214         if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 215             TX4938_PCFG_ATA_SEL)
 216                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
 217                        rbtx4938_piosel_addr);
 218         else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 219                  TX4938_PCFG_NDF_SEL)
 220                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
 221                        rbtx4938_piosel_addr);
 222         else
 223                 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
 224                        rbtx4938_piosel_addr);
 225
 226         rbtx4938_fpga_resource.name = "FPGA Registers";
 227         rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
 228         rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
 229         rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 230         if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
 231                 printk("request resource for fpga failed\n");
 232
 233         _machine_restart = rbtx4938_machine_restart;
 234
 235         writeb(0xff, rbtx4938_led_addr);
 236         printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
 237                readb(rbtx4938_fpga_rev_addr),
 238                readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
 239 }
 240
 241 static int __init rbtx4938_ne_init(void)
 242 {
 243         struct resource res[] = {
 244                 {
 245                         .start  = RBTX4938_RTL_8019_BASE,
 246                         .end    = RBTX4938_RTL_8019_BASE + 0x20 - 1,
 247                         .flags  = IORESOURCE_IO,
 248                 }, {
 249                         .start  = RBTX4938_RTL_8019_IRQ,
 250                         .flags  = IORESOURCE_IRQ,
 251                 }
 252         };
 253         struct platform_device *dev =
 254                 platform_device_register_simple("ne", -1,
 255                                                 res, ARRAY_SIZE(res));
 256         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 257 }
 258
 259 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
 260
 261 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
 262                                   int value)
 263 {
 264         u8 val;
 265         unsigned long flags;
 266         spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
 267         val = readb(rbtx4938_spics_addr);
 268         if (value)
 269                 val |= 1 << offset;
 270         else
 271                 val &= ~(1 << offset);
 272         writeb(val, rbtx4938_spics_addr);
 273         mmiowb();
 274         spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
 275 }
 276
 277 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
 278                                      unsigned int offset, int value)
 279 {
 280         rbtx4938_spi_gpio_set(chip, offset, value);
 281         return 0;
 282 }
 283
 284 static struct gpio_chip rbtx4938_spi_gpio_chip = {
 285         .set = rbtx4938_spi_gpio_set,
 286         .direction_output = rbtx4938_spi_gpio_dir_out,
 287         .label = "RBTX4938-SPICS",
 288         .base = 16,
 289         .ngpio = 3,
 290 };
 291
 292 static int __init rbtx4938_spi_init(void)
 293 {
 294         struct spi_board_info srtc_info = {
 295                 .modalias = "rtc-rs5c348",
 296                 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
 297                 .bus_num = 0,
 298                 .chip_select = 16 + SRTC_CS,
 299                 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
 300                 .mode = SPI_MODE_1 | SPI_CS_HIGH,
 301         };
 302         spi_register_board_info(&srtc_info, 1);
 303         spi_eeprom_register(SEEPROM1_CS);
 304         spi_eeprom_register(16 + SEEPROM2_CS);
 305         spi_eeprom_register(16 + SEEPROM3_CS);
 306         gpio_request(16 + SRTC_CS, "rtc-rs5c348");
 307         gpio_direction_output(16 + SRTC_CS, 0);
 308         gpio_request(SEEPROM1_CS, "seeprom1");
 309         gpio_direction_output(SEEPROM1_CS, 1);
 310         gpio_request(16 + SEEPROM2_CS, "seeprom2");
 311         gpio_direction_output(16 + SEEPROM2_CS, 1);
 312         gpio_request(16 + SEEPROM3_CS, "seeprom3");
 313         gpio_direction_output(16 + SEEPROM3_CS, 1);
 314         tx4938_spi_init(0);
 315         return 0;
 316 }
 317
 318 static void __init rbtx4938_arch_init(void)
 319 {
 320         gpiochip_add(&rbtx4938_spi_gpio_chip);
 321         rbtx4938_pci_setup();
 322         rbtx4938_spi_init();
 323 }
 324
 325 static void __init rbtx4938_device_init(void)
 326 {
 327         rbtx4938_ethaddr_init();
 328         rbtx4938_ne_init();
 329         tx4938_wdt_init();
 330 }
 331
 332 struct txx9_board_vec rbtx4938_vec __initdata = {
 333         .system = "Toshiba RBTX4938",
 334         .prom_init = rbtx4938_prom_init,
 335         .mem_setup = rbtx4938_mem_setup,
 336         .irq_setup = rbtx4938_irq_setup,
 337         .time_init = rbtx4938_time_init,
 338         .device_init = rbtx4938_device_init,
 339         .arch_init = rbtx4938_arch_init,
 340 #ifdef CONFIG_PCI
 341         .pci_map_irq = rbtx4938_pci_map_irq,
 342 #endif
 343 };