arch/mn10300/boot/compressed/head.S

   1 /* Boot entry point for a compressed MN10300 kernel
   2  *
   3  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public Licence
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the Licence, or (at your option) any later version.
  10  */
  11         .section        .text
  12
  13 #define DEBUG
  14
  15 #include <linux/linkage.h>
  16 #include <asm/cpu-regs.h>
  17 #include <asm/cache.h>
  18 #ifdef CONFIG_SMP
  19 #include <proc/smp-regs.h>
  20 #endif
  21
  22         .globl startup_32
  23 startup_32:
  24 #ifdef CONFIG_SMP
  25         #
  26         # Secondary CPUs jump directly to the kernel entry point
  27         #
  28         # Must save primary CPU's D0-D2 registers as they hold boot parameters
  29         #
  30         mov     (CPUID), d3
  31         and     CPUID_MASK,d3
  32         beq     startup_primary
  33         mov     CONFIG_KERNEL_TEXT_ADDRESS,a0
  34         jmp     (a0)
  35
  36 startup_primary:
  37 #endif /* CONFIG_SMP */
  38
  39         # first save parameters from bootloader
  40         mov     param_save_area,a0
  41         mov     d0,(a0)
  42         mov     d1,(4,a0)
  43         mov     d2,(8,a0)
  44
  45         mov     sp,a3
  46         mov     decomp_stack+0x2000-4,a0
  47         mov     a0,sp
  48
  49         # invalidate and enable both of the caches
  50         mov     CHCTR,a0
  51         clr     d0
  52         movhu   d0,(a0)                                 # turn off first
  53         mov     CHCTR_ICINV|CHCTR_DCINV,d0
  54         movhu   d0,(a0)
  55         setlb
  56         mov     (a0),d0
  57         btst    CHCTR_ICBUSY|CHCTR_DCBUSY,d0            # wait till not busy
  58         lne
  59
  60 #ifdef CONFIG_MN10300_CACHE_ENABLED
  61 #ifdef CONFIG_MN10300_CACHE_WBACK
  62         mov     CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
  63 #else
  64         mov     CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
  65 #endif /* WBACK */
  66         movhu   d0,(a0)                                 # enable
  67 #endif /* !ENABLED */
  68
  69         # clear the BSS area
  70         mov     __bss_start,a0
  71         mov     _end,a1
  72         clr     d0
  73 bssclear:
  74         cmp     a1,a0
  75         bge     bssclear_end
  76         movbu   d0,(a0)
  77         inc     a0
  78         bra     bssclear
  79 bssclear_end:
  80
  81         # decompress the kernel
  82         call    decompress_kernel[],0
  83 #ifdef CONFIG_MN10300_CACHE_WBACK
  84         call    mn10300_dcache_flush_inv[],0
  85 #endif
  86
  87         # disable caches again
  88         mov     CHCTR,a0
  89         clr     d0
  90         movhu   d0,(a0)
  91         setlb
  92         mov     (a0),d0
  93         btst    CHCTR_ICBUSY|CHCTR_DCBUSY,d0            # wait till not busy
  94         lne
  95
  96         mov     param_save_area,a0
  97         mov     (a0),d0
  98         mov     (4,a0),d1
  99         mov     (8,a0),d2
 100
 101         # jump to the kernel proper entry point
 102         mov     a3,sp
 103         mov     CONFIG_KERNEL_TEXT_ADDRESS,a0
 104         jmp     (a0)
 105
 106
 107 ###############################################################################
 108 #
 109 # Cache flush routines
 110 #
 111 ###############################################################################
 112 #ifdef CONFIG_MN10300_CACHE_WBACK
 113 mn10300_dcache_flush_inv:
 114         movhu   (CHCTR),d0
 115         btst    CHCTR_DCEN,d0
 116         beq     mn10300_dcache_flush_inv_end
 117
 118         mov     L1_CACHE_NENTRIES,d1
 119         clr     a1
 120
 121 mn10300_dcache_flush_inv_loop:
 122         mov     (DCACHE_PURGE_WAY0(0),a1),d0    # unconditional purge
 123         mov     (DCACHE_PURGE_WAY1(0),a1),d0    # unconditional purge
 124         mov     (DCACHE_PURGE_WAY2(0),a1),d0    # unconditional purge
 125         mov     (DCACHE_PURGE_WAY3(0),a1),d0    # unconditional purge
 126
 127         add     L1_CACHE_BYTES,a1
 128         add     -1,d1
 129         bne     mn10300_dcache_flush_inv_loop
 130
 131 mn10300_dcache_flush_inv_end:
 132         ret     [],0
 133 #endif /* CONFIG_MN10300_CACHE_WBACK */
 134
 135
 136 ###############################################################################
 137 #
 138 # Data areas
 139 #
 140 ###############################################################################
 141         .data
 142         .align          4
 143 param_save_area:
 144         .rept 3
 145         .word           0
 146         .endr
 147
 148         .section        .bss
 149         .align          4
 150 decomp_stack:
 151         .space          0x2000