arch/parisc/include/asm/pgtable.h

   1 #ifndef _PARISC_PGTABLE_H
   2 #define _PARISC_PGTABLE_H
   3
   4 #include <asm-generic/4level-fixup.h>
   5
   6 #include <asm/fixmap.h>
   7
   8 #ifndef __ASSEMBLY__
   9 /*
  10  * we simulate an x86-style page table for the linux mm code
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/mm_types.h>
  16 #include <asm/processor.h>
  17 #include <asm/cache.h>
  18
  19 extern spinlock_t pa_dbit_lock;
  20
  21 /*
  22  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
  23  * memory.  For the return value to be meaningful, ADDR must be >=
  24  * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
  25  * require a hash-, or multi-level tree-lookup or something of that
  26  * sort) but it guarantees to return TRUE only if accessing the page
  27  * at that address does not cause an error.  Note that there may be
  28  * addresses for which kern_addr_valid() returns FALSE even though an
  29  * access would not cause an error (e.g., this is typically true for
  30  * memory mapped I/O regions.
  31  *
  32  * XXX Need to implement this for parisc.
  33  */
  34 #define kern_addr_valid(addr)   (1)
  35
  36 /* Certain architectures need to do special things when PTEs
  37  * within a page table are directly modified.  Thus, the following
  38  * hook is made available.
  39  */
  40 #define set_pte(pteptr, pteval)                                 \
  41         do{                                                     \
  42                 *(pteptr) = (pteval);                           \
  43         } while(0)
  44
  45 extern void purge_tlb_entries(struct mm_struct *, unsigned long);
  46
  47 #define set_pte_at(mm, addr, ptep, pteval)                      \
  48         do {                                                    \
  49                 unsigned long flags;                            \
  50                 spin_lock_irqsave(&pa_dbit_lock, flags);        \
  51                 set_pte(ptep, pteval);                          \
  52                 purge_tlb_entries(mm, addr);                    \
  53                 spin_unlock_irqrestore(&pa_dbit_lock, flags);   \
  54         } while (0)
  55
  56 #endif /* !__ASSEMBLY__ */
  57
  58 #include <asm/page.h>
  59
  60 #define pte_ERROR(e) \
  61         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
  62 #define pmd_ERROR(e) \
  63         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
  64 #define pgd_ERROR(e) \
  65         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
  66
  67 /* This is the size of the initially mapped kernel memory */
  68 #define KERNEL_INITIAL_ORDER    24      /* 0 to 1<<24 = 16MB */
  69 #define KERNEL_INITIAL_SIZE     (1 << KERNEL_INITIAL_ORDER)
  70
  71 #if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
  72 #define PT_NLEVELS      3
  73 #define PGD_ORDER       1 /* Number of pages per pgd */
  74 #define PMD_ORDER       1 /* Number of pages per pmd */
  75 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
  76 #else
  77 #define PT_NLEVELS      2
  78 #define PGD_ORDER       1 /* Number of pages per pgd */
  79 #define PGD_ALLOC_ORDER PGD_ORDER
  80 #endif
  81
  82 /* Definitions for 3rd level (we use PLD here for Page Lower directory
  83  * because PTE_SHIFT is used lower down to mean shift that has to be
  84  * done to get usable bits out of the PTE) */
  85 #define PLD_SHIFT       PAGE_SHIFT
  86 #define PLD_SIZE        PAGE_SIZE
  87 #define BITS_PER_PTE    (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
  88 #define PTRS_PER_PTE    (1UL << BITS_PER_PTE)
  89
  90 /* Definitions for 2nd level */
  91 #define pgtable_cache_init()    do { } while (0)
  92
  93 #define PMD_SHIFT       (PLD_SHIFT + BITS_PER_PTE)
  94 #define PMD_SIZE        (1UL << PMD_SHIFT)
  95 #define PMD_MASK        (~(PMD_SIZE-1))
  96 #if PT_NLEVELS == 3
  97 #define BITS_PER_PMD    (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
  98 #else
  99 #define __PAGETABLE_PMD_FOLDED
 100 #define BITS_PER_PMD    0
 101 #endif
 102 #define PTRS_PER_PMD    (1UL << BITS_PER_PMD)
 103
 104 /* Definitions for 1st level */
 105 #define PGDIR_SHIFT     (PMD_SHIFT + BITS_PER_PMD)
 106 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
 107 #define BITS_PER_PGD    (BITS_PER_LONG - PGDIR_SHIFT)
 108 #else
 109 #define BITS_PER_PGD    (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
 110 #endif
 111 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 112 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 113 #define PTRS_PER_PGD    (1UL << BITS_PER_PGD)
 114 #define USER_PTRS_PER_PGD       PTRS_PER_PGD
 115
 116 #ifdef CONFIG_64BIT
 117 #define MAX_ADDRBITS    (PGDIR_SHIFT + BITS_PER_PGD)
 118 #define MAX_ADDRESS     (1UL << MAX_ADDRBITS)
 119 #define SPACEID_SHIFT   (MAX_ADDRBITS - 32)
 120 #else
 121 #define MAX_ADDRBITS    (BITS_PER_LONG)
 122 #define MAX_ADDRESS     (1UL << MAX_ADDRBITS)
 123 #define SPACEID_SHIFT   0
 124 #endif
 125
 126 /* This calculates the number of initial pages we need for the initial
 127  * page tables */
 128 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
 129 # define PT_INITIAL     (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
 130 #else
 131 # define PT_INITIAL     (1)  /* all initial PTEs fit into one page */
 132 #endif
 133
 134 /*
 135  * pgd entries used up by user/kernel:
 136  */
 137
 138 #define FIRST_USER_ADDRESS      0UL
 139
 140 /* NB: The tlb miss handlers make certain assumptions about the order */
 141 /*     of the following bits, so be careful (One example, bits 25-31  */
 142 /*     are moved together in one instruction).                        */
 143
 144 #define _PAGE_READ_BIT     31   /* (0x001) read access allowed */
 145 #define _PAGE_WRITE_BIT    30   /* (0x002) write access allowed */
 146 #define _PAGE_EXEC_BIT     29   /* (0x004) execute access allowed */
 147 #define _PAGE_GATEWAY_BIT  28   /* (0x008) privilege promotion allowed */
 148 #define _PAGE_DMB_BIT      27   /* (0x010) Data Memory Break enable (B bit) */
 149 #define _PAGE_DIRTY_BIT    26   /* (0x020) Page Dirty (D bit) */
 150 #define _PAGE_REFTRAP_BIT  25   /* (0x040) Page Ref. Trap enable (T bit) */
 151 #define _PAGE_NO_CACHE_BIT 24   /* (0x080) Uncached Page (U bit) */
 152 #define _PAGE_ACCESSED_BIT 23   /* (0x100) Software: Page Accessed */
 153 #define _PAGE_PRESENT_BIT  22   /* (0x200) Software: translation valid */
 154 /* bit 21 was formerly the FLUSH bit but is now unused */
 155 #define _PAGE_USER_BIT     20   /* (0x800) Software: User accessible page */
 156
 157 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
 158 /*      following macro is ok for both 32 and 64 bit.                */
 159
 160 #define xlate_pabit(x) (31 - x)
 161
 162 /* this defines the shift to the usable bits in the PTE it is set so
 163  * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
 164  * to zero */
 165 #define PTE_SHIFT               xlate_pabit(_PAGE_USER_BIT)
 166
 167 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
 168 #define PFN_PTE_SHIFT           12
 169
 170 #define _PAGE_READ     (1 << xlate_pabit(_PAGE_READ_BIT))
 171 #define _PAGE_WRITE    (1 << xlate_pabit(_PAGE_WRITE_BIT))
 172 #define _PAGE_RW       (_PAGE_READ | _PAGE_WRITE)
 173 #define _PAGE_EXEC     (1 << xlate_pabit(_PAGE_EXEC_BIT))
 174 #define _PAGE_GATEWAY  (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
 175 #define _PAGE_DMB      (1 << xlate_pabit(_PAGE_DMB_BIT))
 176 #define _PAGE_DIRTY    (1 << xlate_pabit(_PAGE_DIRTY_BIT))
 177 #define _PAGE_REFTRAP  (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
 178 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
 179 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
 180 #define _PAGE_PRESENT  (1 << xlate_pabit(_PAGE_PRESENT_BIT))
 181 #define _PAGE_USER     (1 << xlate_pabit(_PAGE_USER_BIT))
 182
 183 #define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_ACCESSED)
 184 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 185 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
 186 #define _PAGE_KERNEL_EXEC       (_PAGE_KERNEL_RO | _PAGE_EXEC)
 187 #define _PAGE_KERNEL_RWX        (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
 188 #define _PAGE_KERNEL            (_PAGE_KERNEL_RO | _PAGE_WRITE)
 189
 190 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
 191  * are page-aligned, we don't care about the PAGE_OFFSET bits, except
 192  * for a few meta-information bits, so we shift the address to be
 193  * able to effectively address 40/42/44-bits of physical address space
 194  * depending on 4k/16k/64k PAGE_SIZE */
 195 #define _PxD_PRESENT_BIT   31
 196 #define _PxD_ATTACHED_BIT  30
 197 #define _PxD_VALID_BIT     29
 198
 199 #define PxD_FLAG_PRESENT  (1 << xlate_pabit(_PxD_PRESENT_BIT))
 200 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
 201 #define PxD_FLAG_VALID    (1 << xlate_pabit(_PxD_VALID_BIT))
 202 #define PxD_FLAG_MASK     (0xf)
 203 #define PxD_FLAG_SHIFT    (4)
 204 #define PxD_VALUE_SHIFT   (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
 205
 206 #ifndef __ASSEMBLY__
 207
 208 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
 209 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
 210 /* Others seem to make this executable, I don't know if that's correct
 211    or not.  The stack is mapped this way though so this is necessary
 212    in the short term - dhd@linuxcare.com, 2000-08-08 */
 213 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
 214 #define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
 215 #define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
 216 #define PAGE_COPY       PAGE_EXECREAD
 217 #define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
 218 #define PAGE_KERNEL     __pgprot(_PAGE_KERNEL)
 219 #define PAGE_KERNEL_EXEC        __pgprot(_PAGE_KERNEL_EXEC)
 220 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
 221 #define PAGE_KERNEL_RO  __pgprot(_PAGE_KERNEL_RO)
 222 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
 223 #define PAGE_GATEWAY    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
 224
 225
 226 /*
 227  * We could have an execute only page using "gateway - promote to priv
 228  * level 3", but that is kind of silly. So, the way things are defined
 229  * now, we must always have read permission for pages with execute
 230  * permission. For the fun of it we'll go ahead and support write only
 231  * pages.
 232  */
 233
 234          /*xwr*/
 235 #define __P000  PAGE_NONE
 236 #define __P001  PAGE_READONLY
 237 #define __P010  __P000 /* copy on write */
 238 #define __P011  __P001 /* copy on write */
 239 #define __P100  PAGE_EXECREAD
 240 #define __P101  PAGE_EXECREAD
 241 #define __P110  __P100 /* copy on write */
 242 #define __P111  __P101 /* copy on write */
 243
 244 #define __S000  PAGE_NONE
 245 #define __S001  PAGE_READONLY
 246 #define __S010  PAGE_WRITEONLY
 247 #define __S011  PAGE_SHARED
 248 #define __S100  PAGE_EXECREAD
 249 #define __S101  PAGE_EXECREAD
 250 #define __S110  PAGE_RWX
 251 #define __S111  PAGE_RWX
 252
 253
 254 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
 255
 256 /* initial page tables for 0-8MB for kernel */
 257
 258 extern pte_t pg0[];
 259
 260 /* zero page used for uninitialized stuff */
 261
 262 extern unsigned long *empty_zero_page;
 263
 264 /*
 265  * ZERO_PAGE is a global shared page that is always zero: used
 266  * for zero-mapped memory areas etc..
 267  */
 268
 269 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 270
 271 #define pte_none(x)     (pte_val(x) == 0)
 272 #define pte_present(x)  (pte_val(x) & _PAGE_PRESENT)
 273 #define pte_clear(mm,addr,xp)   do { pte_val(*(xp)) = 0; } while (0)
 274
 275 #define pmd_flag(x)     (pmd_val(x) & PxD_FLAG_MASK)
 276 #define pmd_address(x)  ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
 277 #define pgd_flag(x)     (pgd_val(x) & PxD_FLAG_MASK)
 278 #define pgd_address(x)  ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
 279
 280 #if PT_NLEVELS == 3
 281 /* The first entry of the permanent pmd is not there if it contains
 282  * the gateway marker */
 283 #define pmd_none(x)     (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
 284 #else
 285 #define pmd_none(x)     (!pmd_val(x))
 286 #endif
 287 #define pmd_bad(x)      (!(pmd_flag(x) & PxD_FLAG_VALID))
 288 #define pmd_present(x)  (pmd_flag(x) & PxD_FLAG_PRESENT)
 289 static inline void pmd_clear(pmd_t *pmd) {
 290 #if PT_NLEVELS == 3
 291         if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
 292                 /* This is the entry pointing to the permanent pmd
 293                  * attached to the pgd; cannot clear it */
 294                 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
 295         else
 296 #endif
 297                 __pmd_val_set(*pmd,  0);
 298 }
 299
 300
 301
 302 #if PT_NLEVELS == 3
 303 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
 304 #define pgd_page(pgd)   virt_to_page((void *)pgd_page_vaddr(pgd))
 305
 306 /* For 64 bit we have three level tables */
 307
 308 #define pgd_none(x)     (!pgd_val(x))
 309 #define pgd_bad(x)      (!(pgd_flag(x) & PxD_FLAG_VALID))
 310 #define pgd_present(x)  (pgd_flag(x) & PxD_FLAG_PRESENT)
 311 static inline void pgd_clear(pgd_t *pgd) {
 312 #if PT_NLEVELS == 3
 313         if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
 314                 /* This is the permanent pmd attached to the pgd; cannot
 315                  * free it */
 316                 return;
 317 #endif
 318         __pgd_val_set(*pgd, 0);
 319 }
 320 #else
 321 /*
 322  * The "pgd_xxx()" functions here are trivial for a folded two-level
 323  * setup: the pgd is never bad, and a pmd always exists (as it's folded
 324  * into the pgd entry)
 325  */
 326 static inline int pgd_none(pgd_t pgd)           { return 0; }
 327 static inline int pgd_bad(pgd_t pgd)            { return 0; }
 328 static inline int pgd_present(pgd_t pgd)        { return 1; }
 329 static inline void pgd_clear(pgd_t * pgdp)      { }
 330 #endif
 331
 332 /*
 333  * The following only work if pte_present() is true.
 334  * Undefined behaviour if not..
 335  */
 336 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 337 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 338 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_WRITE; }
 339 static inline int pte_special(pte_t pte)        { return 0; }
 340
 341 static inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
 342 static inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 343 static inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
 344 static inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 345 static inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 346 static inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) |= _PAGE_WRITE; return pte; }
 347 static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
 348
 349 /*
 350  * Conversion functions: convert a page and protection to a page entry,
 351  * and a page entry and page directory to the page they refer to.
 352  */
 353 #define __mk_pte(addr,pgprot) \
 354 ({                                                                      \
 355         pte_t __pte;                                                    \
 356                                                                         \
 357         pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot));  \
 358                                                                         \
 359         __pte;                                                          \
 360 })
 361
 362 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 363
 364 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 365 {
 366         pte_t pte;
 367         pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
 368         return pte;
 369 }
 370
 371 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 372 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
 373
 374 /* Permanent address of a page.  On parisc we don't have highmem. */
 375
 376 #define pte_pfn(x)              (pte_val(x) >> PFN_PTE_SHIFT)
 377
 378 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 379
 380 #define pmd_page_vaddr(pmd)     ((unsigned long) __va(pmd_address(pmd)))
 381
 382 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
 383 #define pmd_page(pmd)   virt_to_page((void *)__pmd_page(pmd))
 384
 385 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
 386
 387 /* to find an entry in a page-table-directory */
 388 #define pgd_offset(mm, address) \
 389 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
 390
 391 /* to find an entry in a kernel page-table-directory */
 392 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 393
 394 /* Find an entry in the second-level page table.. */
 395
 396 #if PT_NLEVELS == 3
 397 #define pmd_offset(dir,address) \
 398 ((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
 399 #else
 400 #define pmd_offset(dir,addr) ((pmd_t *) dir)
 401 #endif
 402
 403 /* Find an entry in the third-level page table.. */
 404 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
 405 #define pte_offset_kernel(pmd, address) \
 406         ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
 407 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
 408 #define pte_unmap(pte) do { } while (0)
 409
 410 #define pte_unmap(pte)                  do { } while (0)
 411 #define pte_unmap_nested(pte)           do { } while (0)
 412
 413 extern void paging_init (void);
 414
 415 /* Used for deferring calls to flush_dcache_page() */
 416
 417 #define PG_dcache_dirty         PG_arch_1
 418
 419 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 420
 421 /* Encode and de-code a swap entry */
 422
 423 #define __swp_type(x)                     ((x).val & 0x1f)
 424 #define __swp_offset(x)                   ( (((x).val >> 6) &  0x7) | \
 425                                           (((x).val >> 8) & ~0x7) )
 426 #define __swp_entry(type, offset)         ((swp_entry_t) { (type) | \
 427                                             ((offset &  0x7) << 6) | \
 428                                             ((offset & ~0x7) << 8) })
 429 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 430 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 431
 432 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 433 {
 434         pte_t pte;
 435         unsigned long flags;
 436
 437         if (!pte_young(*ptep))
 438                 return 0;
 439
 440         spin_lock_irqsave(&pa_dbit_lock, flags);
 441         pte = *ptep;
 442         if (!pte_young(pte)) {
 443                 spin_unlock_irqrestore(&pa_dbit_lock, flags);
 444                 return 0;
 445         }
 446         set_pte(ptep, pte_mkold(pte));
 447         purge_tlb_entries(vma->vm_mm, addr);
 448         spin_unlock_irqrestore(&pa_dbit_lock, flags);
 449         return 1;
 450 }
 451
 452 struct mm_struct;
 453 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 454 {
 455         pte_t old_pte;
 456         unsigned long flags;
 457
 458         spin_lock_irqsave(&pa_dbit_lock, flags);
 459         old_pte = *ptep;
 460         pte_clear(mm,addr,ptep);
 461         purge_tlb_entries(mm, addr);
 462         spin_unlock_irqrestore(&pa_dbit_lock, flags);
 463
 464         return old_pte;
 465 }
 466
 467 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 468 {
 469         unsigned long flags;
 470         spin_lock_irqsave(&pa_dbit_lock, flags);
 471         set_pte(ptep, pte_wrprotect(*ptep));
 472         purge_tlb_entries(mm, addr);
 473         spin_unlock_irqrestore(&pa_dbit_lock, flags);
 474 }
 475
 476 #define pte_same(A,B)   (pte_val(A) == pte_val(B))
 477
 478 #endif /* !__ASSEMBLY__ */
 479
 480
 481 /* TLB page size encoding - see table 3-1 in parisc20.pdf */
 482 #define _PAGE_SIZE_ENCODING_4K          0
 483 #define _PAGE_SIZE_ENCODING_16K         1
 484 #define _PAGE_SIZE_ENCODING_64K         2
 485 #define _PAGE_SIZE_ENCODING_256K        3
 486 #define _PAGE_SIZE_ENCODING_1M          4
 487 #define _PAGE_SIZE_ENCODING_4M          5
 488 #define _PAGE_SIZE_ENCODING_16M         6
 489 #define _PAGE_SIZE_ENCODING_64M         7
 490
 491 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
 492 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
 493 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
 494 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
 495 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
 496 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
 497 #endif
 498
 499
 500 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
 501
 502 /* We provide our own get_unmapped_area to provide cache coherency */
 503
 504 #define HAVE_ARCH_UNMAPPED_AREA
 505 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 506
 507 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 508 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 509 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 510 #define __HAVE_ARCH_PTE_SAME
 511 #include <asm-generic/pgtable.h>
 512
 513 #endif /* _PARISC_PGTABLE_H */