arch/parisc/kernel/entry.S

   1 /*
   2  * Linux/PA-RISC Project (http://www.parisc-linux.org/)
   3  *
   4  * kernel entry points (interruptions, system call wrappers)
   5  *  Copyright (C) 1999,2000 Philipp Rumpf
   6  *  Copyright (C) 1999 SuSE GmbH Nuernberg
   7  *  Copyright (C) 2000 Hewlett-Packard (John Marvin)
   8  *  Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
   9  *
  10  *    This program is free software; you can redistribute it and/or modify
  11  *    it under the terms of the GNU General Public License as published by
  12  *    the Free Software Foundation; either version 2, or (at your option)
  13  *    any later version.
  14  *
  15  *    This program is distributed in the hope that it will be useful,
  16  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *    GNU General Public License for more details.
  19  *
  20  *    You should have received a copy of the GNU General Public License
  21  *    along with this program; if not, write to the Free Software
  22  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <asm/asm-offsets.h>
  26
  27 /* we have the following possibilities to act on an interruption:
  28  *  - handle in assembly and use shadowed registers only
  29  *  - save registers to kernel stack and handle in assembly or C */
  30
  31
  32 #include <asm/psw.h>
  33 #include <asm/cache.h>          /* for L1_CACHE_SHIFT */
  34 #include <asm/assembly.h>       /* for LDREG/STREG defines */
  35 #include <asm/pgtable.h>
  36 #include <asm/signal.h>
  37 #include <asm/unistd.h>
  38 #include <asm/thread_info.h>
  39
  40 #include <linux/linkage.h>
  41
  42 #ifdef CONFIG_64BIT
  43         .level 2.0w
  44 #else
  45         .level 2.0
  46 #endif
  47
  48         .import         pa_dbit_lock,data
  49
  50         /* space_to_prot macro creates a prot id from a space id */
  51
  52 #if (SPACEID_SHIFT) == 0
  53         .macro  space_to_prot spc prot
  54         depd,z  \spc,62,31,\prot
  55         .endm
  56 #else
  57         .macro  space_to_prot spc prot
  58         extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
  59         .endm
  60 #endif
  61
  62         /* Switch to virtual mapping, trashing only %r1 */
  63         .macro  virt_map
  64         /* pcxt_ssm_bug */
  65         rsm     PSW_SM_I, %r0   /* barrier for "Relied upon Translation */
  66         mtsp    %r0, %sr4
  67         mtsp    %r0, %sr5
  68         mfsp    %sr7, %r1
  69         or,=    %r0,%r1,%r0     /* Only save sr7 in sr3 if sr7 != 0 */
  70         mtsp    %r1, %sr3
  71         tovirt_r1 %r29
  72         load32  KERNEL_PSW, %r1
  73
  74         rsm     PSW_SM_QUIET,%r0        /* second "heavy weight" ctl op */
  75         mtsp    %r0, %sr6
  76         mtsp    %r0, %sr7
  77         mtctl   %r0, %cr17      /* Clear IIASQ tail */
  78         mtctl   %r0, %cr17      /* Clear IIASQ head */
  79         mtctl   %r1, %ipsw
  80         load32  4f, %r1
  81         mtctl   %r1, %cr18      /* Set IIAOQ tail */
  82         ldo     4(%r1), %r1
  83         mtctl   %r1, %cr18      /* Set IIAOQ head */
  84         rfir
  85         nop
  86 4:
  87         .endm
  88
  89         /*
  90          * The "get_stack" macros are responsible for determining the
  91          * kernel stack value.
  92          *
  93          *      If sr7 == 0
  94          *          Already using a kernel stack, so call the
  95          *          get_stack_use_r30 macro to push a pt_regs structure
  96          *          on the stack, and store registers there.
  97          *      else
  98          *          Need to set up a kernel stack, so call the
  99          *          get_stack_use_cr30 macro to set up a pointer
 100          *          to the pt_regs structure contained within the
 101          *          task pointer pointed to by cr30. Set the stack
 102          *          pointer to point to the end of the task structure.
 103          *
 104          * Note that we use shadowed registers for temps until
 105          * we can save %r26 and %r29. %r26 is used to preserve
 106          * %r8 (a shadowed register) which temporarily contained
 107          * either the fault type ("code") or the eirr. We need
 108          * to use a non-shadowed register to carry the value over
 109          * the rfir in virt_map. We use %r26 since this value winds
 110          * up being passed as the argument to either do_cpu_irq_mask
 111          * or handle_interruption. %r29 is used to hold a pointer
 112          * the register save area, and once again, it needs to
 113          * be a non-shadowed register so that it survives the rfir.
 114          *
 115          * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
 116          */
 117
 118         .macro  get_stack_use_cr30
 119
 120         /* we save the registers in the task struct */
 121
 122         mfctl   %cr30, %r1
 123         tophys  %r1,%r9
 124         LDREG   TI_TASK(%r9), %r1       /* thread_info -> task_struct */
 125         tophys  %r1,%r9
 126         ldo     TASK_REGS(%r9),%r9
 127         STREG   %r30, PT_GR30(%r9)
 128         STREG   %r29,PT_GR29(%r9)
 129         STREG   %r26,PT_GR26(%r9)
 130         copy    %r9,%r29
 131         mfctl   %cr30, %r1
 132         ldo     THREAD_SZ_ALGN(%r1), %r30
 133         .endm
 134
 135         .macro  get_stack_use_r30
 136
 137         /* we put a struct pt_regs on the stack and save the registers there */
 138
 139         tophys  %r30,%r9
 140         STREG   %r30,PT_GR30(%r9)
 141         ldo     PT_SZ_ALGN(%r30),%r30
 142         STREG   %r29,PT_GR29(%r9)
 143         STREG   %r26,PT_GR26(%r9)
 144         copy    %r9,%r29
 145         .endm
 146
 147         .macro  rest_stack
 148         LDREG   PT_GR1(%r29), %r1
 149         LDREG   PT_GR30(%r29),%r30
 150         LDREG   PT_GR29(%r29),%r29
 151         .endm
 152
 153         /* default interruption handler
 154          * (calls traps.c:handle_interruption) */
 155         .macro  def code
 156         b       intr_save
 157         ldi     \code, %r8
 158         .align  32
 159         .endm
 160
 161         /* Interrupt interruption handler
 162          * (calls irq.c:do_cpu_irq_mask) */
 163         .macro  extint code
 164         b       intr_extint
 165         mfsp    %sr7,%r16
 166         .align  32
 167         .endm
 168
 169         .import os_hpmc, code
 170
 171         /* HPMC handler */
 172         .macro  hpmc code
 173         nop                     /* must be a NOP, will be patched later */
 174         load32  PA(os_hpmc), %r3
 175         bv,n    0(%r3)
 176         nop
 177         .word   0               /* checksum (will be patched) */
 178         .word   PA(os_hpmc)     /* address of handler */
 179         .word   0               /* length of handler */
 180         .endm
 181
 182         /*
 183          * Performance Note: Instructions will be moved up into
 184          * this part of the code later on, once we are sure
 185          * that the tlb miss handlers are close to final form.
 186          */
 187
 188         /* Register definitions for tlb miss handler macros */
 189
 190         va  = r8        /* virtual address for which the trap occurred */
 191         spc = r24       /* space for which the trap occurred */
 192
 193 #ifndef CONFIG_64BIT
 194
 195         /*
 196          * itlb miss interruption handler (parisc 1.1 - 32 bit)
 197          */
 198
 199         .macro  itlb_11 code
 200
 201         mfctl   %pcsq, spc
 202         b       itlb_miss_11
 203         mfctl   %pcoq, va
 204
 205         .align          32
 206         .endm
 207 #endif
 208
 209         /*
 210          * itlb miss interruption handler (parisc 2.0)
 211          */
 212
 213         .macro  itlb_20 code
 214         mfctl   %pcsq, spc
 215 #ifdef CONFIG_64BIT
 216         b       itlb_miss_20w
 217 #else
 218         b       itlb_miss_20
 219 #endif
 220         mfctl   %pcoq, va
 221
 222         .align          32
 223         .endm
 224
 225 #ifndef CONFIG_64BIT
 226         /*
 227          * naitlb miss interruption handler (parisc 1.1 - 32 bit)
 228          */
 229
 230         .macro  naitlb_11 code
 231
 232         mfctl   %isr,spc
 233         b       naitlb_miss_11
 234         mfctl   %ior,va
 235
 236         .align          32
 237         .endm
 238 #endif
 239
 240         /*
 241          * naitlb miss interruption handler (parisc 2.0)
 242          */
 243
 244         .macro  naitlb_20 code
 245
 246         mfctl   %isr,spc
 247 #ifdef CONFIG_64BIT
 248         b       naitlb_miss_20w
 249 #else
 250         b       naitlb_miss_20
 251 #endif
 252         mfctl   %ior,va
 253
 254         .align          32
 255         .endm
 256
 257 #ifndef CONFIG_64BIT
 258         /*
 259          * dtlb miss interruption handler (parisc 1.1 - 32 bit)
 260          */
 261
 262         .macro  dtlb_11 code
 263
 264         mfctl   %isr, spc
 265         b       dtlb_miss_11
 266         mfctl   %ior, va
 267
 268         .align          32
 269         .endm
 270 #endif
 271
 272         /*
 273          * dtlb miss interruption handler (parisc 2.0)
 274          */
 275
 276         .macro  dtlb_20 code
 277
 278         mfctl   %isr, spc
 279 #ifdef CONFIG_64BIT
 280         b       dtlb_miss_20w
 281 #else
 282         b       dtlb_miss_20
 283 #endif
 284         mfctl   %ior, va
 285
 286         .align          32
 287         .endm
 288
 289 #ifndef CONFIG_64BIT
 290         /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
 291
 292         .macro  nadtlb_11 code
 293
 294         mfctl   %isr,spc
 295         b       nadtlb_miss_11
 296         mfctl   %ior,va
 297
 298         .align          32
 299         .endm
 300 #endif
 301
 302         /* nadtlb miss interruption handler (parisc 2.0) */
 303
 304         .macro  nadtlb_20 code
 305
 306         mfctl   %isr,spc
 307 #ifdef CONFIG_64BIT
 308         b       nadtlb_miss_20w
 309 #else
 310         b       nadtlb_miss_20
 311 #endif
 312         mfctl   %ior,va
 313
 314         .align          32
 315         .endm
 316
 317 #ifndef CONFIG_64BIT
 318         /*
 319          * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
 320          */
 321
 322         .macro  dbit_11 code
 323
 324         mfctl   %isr,spc
 325         b       dbit_trap_11
 326         mfctl   %ior,va
 327
 328         .align          32
 329         .endm
 330 #endif
 331
 332         /*
 333          * dirty bit trap interruption handler (parisc 2.0)
 334          */
 335
 336         .macro  dbit_20 code
 337
 338         mfctl   %isr,spc
 339 #ifdef CONFIG_64BIT
 340         b       dbit_trap_20w
 341 #else
 342         b       dbit_trap_20
 343 #endif
 344         mfctl   %ior,va
 345
 346         .align          32
 347         .endm
 348
 349         /* In LP64, the space contains part of the upper 32 bits of the
 350          * fault.  We have to extract this and place it in the va,
 351          * zeroing the corresponding bits in the space register */
 352         .macro          space_adjust    spc,va,tmp
 353 #ifdef CONFIG_64BIT
 354         extrd,u         \spc,63,SPACEID_SHIFT,\tmp
 355         depd            %r0,63,SPACEID_SHIFT,\spc
 356         depd            \tmp,31,SPACEID_SHIFT,\va
 357 #endif
 358         .endm
 359
 360         .import         swapper_pg_dir,code
 361
 362         /* Get the pgd.  For faults on space zero (kernel space), this
 363          * is simply swapper_pg_dir.  For user space faults, the
 364          * pgd is stored in %cr25 */
 365         .macro          get_pgd         spc,reg
 366         ldil            L%PA(swapper_pg_dir),\reg
 367         ldo             R%PA(swapper_pg_dir)(\reg),\reg
 368         or,COND(=)      %r0,\spc,%r0
 369         mfctl           %cr25,\reg
 370         .endm
 371
 372         /*
 373                 space_check(spc,tmp,fault)
 374
 375                 spc - The space we saw the fault with.
 376                 tmp - The place to store the current space.
 377                 fault - Function to call on failure.
 378
 379                 Only allow faults on different spaces from the
 380                 currently active one if we're the kernel
 381
 382         */
 383         .macro          space_check     spc,tmp,fault
 384         mfsp            %sr7,\tmp
 385         or,COND(<>)     %r0,\spc,%r0    /* user may execute gateway page
 386                                          * as kernel, so defeat the space
 387                                          * check if it is */
 388         copy            \spc,\tmp
 389         or,COND(=)      %r0,\tmp,%r0    /* nullify if executing as kernel */
 390         cmpb,COND(<>),n \tmp,\spc,\fault
 391         .endm
 392
 393         /* Look up a PTE in a 2-Level scheme (faulting at each
 394          * level if the entry isn't present
 395          *
 396          * NOTE: we use ldw even for LP64, since the short pointers
 397          * can address up to 1TB
 398          */
 399         .macro          L2_ptep pmd,pte,index,va,fault
 400 #if PT_NLEVELS == 3
 401         extru           \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
 402 #else
 403         extru           \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
 404 #endif
 405         dep             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
 406         copy            %r0,\pte
 407         ldw,s           \index(\pmd),\pmd
 408         bb,>=,n         \pmd,_PxD_PRESENT_BIT,\fault
 409         dep             %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
 410         copy            \pmd,%r9
 411         SHLREG          %r9,PxD_VALUE_SHIFT,\pmd
 412         extru           \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
 413         dep             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
 414         shladd          \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
 415         LDREG           %r0(\pmd),\pte          /* pmd is now pte */
 416         bb,>=,n         \pte,_PAGE_PRESENT_BIT,\fault
 417         .endm
 418
 419         /* Look up PTE in a 3-Level scheme.
 420          *
 421          * Here we implement a Hybrid L2/L3 scheme: we allocate the
 422          * first pmd adjacent to the pgd.  This means that we can
 423          * subtract a constant offset to get to it.  The pmd and pgd
 424          * sizes are arranged so that a single pmd covers 4GB (giving
 425          * a full LP64 process access to 8TB) so our lookups are
 426          * effectively L2 for the first 4GB of the kernel (i.e. for
 427          * all ILP32 processes and all the kernel for machines with
 428          * under 4GB of memory) */
 429         .macro          L3_ptep pgd,pte,index,va,fault
 430 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
 431         extrd,u         \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
 432         copy            %r0,\pte
 433         extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
 434         ldw,s           \index(\pgd),\pgd
 435         extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
 436         bb,>=,n         \pgd,_PxD_PRESENT_BIT,\fault
 437         extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
 438         shld            \pgd,PxD_VALUE_SHIFT,\index
 439         extrd,u,*=      \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
 440         copy            \index,\pgd
 441         extrd,u,*<>     \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
 442         ldo             ASM_PGD_PMD_OFFSET(\pgd),\pgd
 443 #endif
 444         L2_ptep         \pgd,\pte,\index,\va,\fault
 445         .endm
 446
 447         /* Set the _PAGE_ACCESSED bit of the PTE.  Be clever and
 448          * don't needlessly dirty the cache line if it was already set */
 449         .macro          update_ptep     ptep,pte,tmp,tmp1
 450         ldi             _PAGE_ACCESSED,\tmp1
 451         or              \tmp1,\pte,\tmp
 452         and,COND(<>)    \tmp1,\pte,%r0
 453         STREG           \tmp,0(\ptep)
 454         .endm
 455
 456         /* Set the dirty bit (and accessed bit).  No need to be
 457          * clever, this is only used from the dirty fault */
 458         .macro          update_dirty    ptep,pte,tmp
 459         ldi             _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
 460         or              \tmp,\pte,\pte
 461         STREG           \pte,0(\ptep)
 462         .endm
 463
 464         /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
 465          * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
 466         #define PAGE_ADD_SHIFT  (PAGE_SHIFT-12)
 467
 468         /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
 469         .macro          convert_for_tlb_insert20 pte
 470         extrd,u         \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
 471                                 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
 472         depdi           _PAGE_SIZE_ENCODING_DEFAULT,63,\
 473                                 (63-58)+PAGE_ADD_SHIFT,\pte
 474         .endm
 475
 476         /* Convert the pte and prot to tlb insertion values.  How
 477          * this happens is quite subtle, read below */
 478         .macro          make_insert_tlb spc,pte,prot
 479         space_to_prot   \spc \prot        /* create prot id from space */
 480         /* The following is the real subtlety.  This is depositing
 481          * T <-> _PAGE_REFTRAP
 482          * D <-> _PAGE_DIRTY
 483          * B <-> _PAGE_DMB (memory break)
 484          *
 485          * Then incredible subtlety: The access rights are
 486          * _PAGE_GATEWAY _PAGE_EXEC _PAGE_READ
 487          * See 3-14 of the parisc 2.0 manual
 488          *
 489          * Finally, _PAGE_READ goes in the top bit of PL1 (so we
 490          * trigger an access rights trap in user space if the user
 491          * tries to read an unreadable page */
 492         depd            \pte,8,7,\prot
 493
 494         /* PAGE_USER indicates the page can be read with user privileges,
 495          * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
 496          * contains _PAGE_READ */
 497         extrd,u,*=      \pte,_PAGE_USER_BIT+32,1,%r0
 498         depdi           7,11,3,\prot
 499         /* If we're a gateway page, drop PL2 back to zero for promotion
 500          * to kernel privilege (so we can execute the page as kernel).
 501          * Any privilege promotion page always denys read and write */
 502         extrd,u,*=      \pte,_PAGE_GATEWAY_BIT+32,1,%r0
 503         depd            %r0,11,2,\prot  /* If Gateway, Set PL2 to 0 */
 504
 505         /* Enforce uncacheable pages.
 506          * This should ONLY be use for MMIO on PA 2.0 machines.
 507          * Memory/DMA is cache coherent on all PA2.0 machines we support
 508          * (that means T-class is NOT supported) and the memory controllers
 509          * on most of those machines only handles cache transactions.
 510          */
 511         extrd,u,*=      \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
 512         depdi           1,12,1,\prot
 513
 514         /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
 515         convert_for_tlb_insert20 \pte
 516         .endm
 517
 518         /* Identical macro to make_insert_tlb above, except it
 519          * makes the tlb entry for the differently formatted pa11
 520          * insertion instructions */
 521         .macro          make_insert_tlb_11      spc,pte,prot
 522         zdep            \spc,30,15,\prot
 523         dep             \pte,8,7,\prot
 524         extru,=         \pte,_PAGE_NO_CACHE_BIT,1,%r0
 525         depi            1,12,1,\prot
 526         extru,=         \pte,_PAGE_USER_BIT,1,%r0
 527         depi            7,11,3,\prot   /* Set for user space (1 rsvd for read) */
 528         extru,=         \pte,_PAGE_GATEWAY_BIT,1,%r0
 529         depi            0,11,2,\prot    /* If Gateway, Set PL2 to 0 */
 530
 531         /* Get rid of prot bits and convert to page addr for iitlba */
 532
 533         depi            0,31,ASM_PFN_PTE_SHIFT,\pte
 534         SHRREG          \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
 535         .endm
 536
 537         /* This is for ILP32 PA2.0 only.  The TLB insertion needs
 538          * to extend into I/O space if the address is 0xfXXXXXXX
 539          * so we extend the f's into the top word of the pte in
 540          * this case */
 541         .macro          f_extend        pte,tmp
 542         extrd,s         \pte,42,4,\tmp
 543         addi,<>         1,\tmp,%r0
 544         extrd,s         \pte,63,25,\pte
 545         .endm
 546
 547         /* The alias region is an 8MB aligned 16MB to do clear and
 548          * copy user pages at addresses congruent with the user
 549          * virtual address.
 550          *
 551          * To use the alias page, you set %r26 up with the to TLB
 552          * entry (identifying the physical page) and %r23 up with
 553          * the from tlb entry (or nothing if only a to entry---for
 554          * clear_user_page_asm) */
 555         .macro          do_alias        spc,tmp,tmp1,va,pte,prot,fault,patype
 556         cmpib,COND(<>),n 0,\spc,\fault
 557         ldil            L%(TMPALIAS_MAP_START),\tmp
 558 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
 559         /* on LP64, ldi will sign extend into the upper 32 bits,
 560          * which is behaviour we don't want */
 561         depdi           0,31,32,\tmp
 562 #endif
 563         copy            \va,\tmp1
 564         depi            0,31,23,\tmp1
 565         cmpb,COND(<>),n \tmp,\tmp1,\fault
 566         mfctl           %cr19,\tmp      /* iir */
 567         /* get the opcode (first six bits) into \tmp */
 568         extrw,u         \tmp,5,6,\tmp
 569         /*
 570          * Only setting the T bit prevents data cache movein
 571          * Setting access rights to zero prevents instruction cache movein
 572          *
 573          * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
 574          * to type field and _PAGE_READ goes to top bit of PL1
 575          */
 576         ldi             (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
 577         /*
 578          * so if the opcode is one (i.e. this is a memory management
 579          * instruction) nullify the next load so \prot is only T.
 580          * Otherwise this is a normal data operation
 581          */
 582         cmpiclr,=       0x01,\tmp,%r0
 583         ldi             (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
 584 .ifc \patype,20
 585         depd,z          \prot,8,7,\prot
 586 .else
 587 .ifc \patype,11
 588         depw,z          \prot,8,7,\prot
 589 .else
 590         .error "undefined PA type to do_alias"
 591 .endif
 592 .endif
 593         /*
 594          * OK, it is in the temp alias region, check whether "from" or "to".
 595          * Check "subtle" note in pacache.S re: r23/r26.
 596          */
 597 #ifdef CONFIG_64BIT
 598         extrd,u,*=      \va,41,1,%r0
 599 #else
 600         extrw,u,=       \va,9,1,%r0
 601 #endif
 602         or,COND(tr)     %r23,%r0,\pte
 603         or              %r26,%r0,\pte
 604         .endm
 605
 606
 607         /*
 608          * Align fault_vector_20 on 4K boundary so that both
 609          * fault_vector_11 and fault_vector_20 are on the
 610          * same page. This is only necessary as long as we
 611          * write protect the kernel text, which we may stop
 612          * doing once we use large page translations to cover
 613          * the static part of the kernel address space.
 614          */
 615
 616         .text
 617
 618         .align  PAGE_SIZE
 619
 620 ENTRY(fault_vector_20)
 621         /* First vector is invalid (0) */
 622         .ascii  "cows can fly"
 623         .byte 0
 624         .align 32
 625
 626         hpmc             1
 627         def              2
 628         def              3
 629         extint           4
 630         def              5
 631         itlb_20          6
 632         def              7
 633         def              8
 634         def              9
 635         def             10
 636         def             11
 637         def             12
 638         def             13
 639         def             14
 640         dtlb_20         15
 641         naitlb_20       16
 642         nadtlb_20       17
 643         def             18
 644         def             19
 645         dbit_20         20
 646         def             21
 647         def             22
 648         def             23
 649         def             24
 650         def             25
 651         def             26
 652         def             27
 653         def             28
 654         def             29
 655         def             30
 656         def             31
 657 END(fault_vector_20)
 658
 659 #ifndef CONFIG_64BIT
 660
 661         .align 2048
 662
 663 ENTRY(fault_vector_11)
 664         /* First vector is invalid (0) */
 665         .ascii  "cows can fly"
 666         .byte 0
 667         .align 32
 668
 669         hpmc             1
 670         def              2
 671         def              3
 672         extint           4
 673         def              5
 674         itlb_11          6
 675         def              7
 676         def              8
 677         def              9
 678         def             10
 679         def             11
 680         def             12
 681         def             13
 682         def             14
 683         dtlb_11         15
 684         naitlb_11       16
 685         nadtlb_11       17
 686         def             18
 687         def             19
 688         dbit_11         20
 689         def             21
 690         def             22
 691         def             23
 692         def             24
 693         def             25
 694         def             26
 695         def             27
 696         def             28
 697         def             29
 698         def             30
 699         def             31
 700 END(fault_vector_11)
 701
 702 #endif
 703         /* Fault vector is separately protected and *must* be on its own page */
 704         .align          PAGE_SIZE
 705 ENTRY(end_fault_vector)
 706
 707         .import         handle_interruption,code
 708         .import         do_cpu_irq_mask,code
 709
 710         /*
 711          * r26 = function to be called
 712          * r25 = argument to pass in
 713          * r24 = flags for do_fork()
 714          *
 715          * Kernel threads don't ever return, so they don't need
 716          * a true register context. We just save away the arguments
 717          * for copy_thread/ret_ to properly set up the child.
 718          */
 719
 720 #define CLONE_VM 0x100  /* Must agree with <linux/sched.h> */
 721 #define CLONE_UNTRACED 0x00800000
 722
 723         .import do_fork
 724 ENTRY(__kernel_thread)
 725         STREG   %r2, -RP_OFFSET(%r30)
 726
 727         copy    %r30, %r1
 728         ldo     PT_SZ_ALGN(%r30),%r30
 729 #ifdef CONFIG_64BIT
 730         /* Yo, function pointers in wide mode are little structs... -PB */
 731         ldd     24(%r26), %r2
 732         STREG   %r2, PT_GR27(%r1)       /* Store childs %dp */
 733         ldd     16(%r26), %r26
 734
 735         STREG   %r22, PT_GR22(%r1)      /* save r22 (arg5) */
 736         copy    %r0, %r22               /* user_tid */
 737 #endif
 738         STREG   %r26, PT_GR26(%r1)  /* Store function & argument for child */
 739         STREG   %r25, PT_GR25(%r1)
 740         ldil    L%CLONE_UNTRACED, %r26
 741         ldo     CLONE_VM(%r26), %r26   /* Force CLONE_VM since only init_mm */
 742         or      %r26, %r24, %r26      /* will have kernel mappings.      */
 743         ldi     1, %r25                 /* stack_start, signals kernel thread */
 744         stw     %r0, -52(%r30)          /* user_tid */
 745 #ifdef CONFIG_64BIT
 746         ldo     -16(%r30),%r29          /* Reference param save area */
 747 #endif
 748         BL      do_fork, %r2
 749         copy    %r1, %r24               /* pt_regs */
 750
 751         /* Parent Returns here */
 752
 753         LDREG   -PT_SZ_ALGN-RP_OFFSET(%r30), %r2
 754         ldo     -PT_SZ_ALGN(%r30), %r30
 755         bv      %r0(%r2)
 756         nop
 757 ENDPROC(__kernel_thread)
 758
 759         /*
 760          * Child Returns here
 761          *
 762          * copy_thread moved args from temp save area set up above
 763          * into task save area.
 764          */
 765
 766 ENTRY(ret_from_kernel_thread)
 767
 768         /* Call schedule_tail first though */
 769         BL      schedule_tail, %r2
 770         nop
 771
 772         LDREG   TI_TASK-THREAD_SZ_ALGN(%r30), %r1
 773         LDREG   TASK_PT_GR25(%r1), %r26
 774 #ifdef CONFIG_64BIT
 775         LDREG   TASK_PT_GR27(%r1), %r27
 776         LDREG   TASK_PT_GR22(%r1), %r22
 777 #endif
 778         LDREG   TASK_PT_GR26(%r1), %r1
 779         ble     0(%sr7, %r1)
 780         copy    %r31, %r2
 781
 782 #ifdef CONFIG_64BIT
 783         ldo     -16(%r30),%r29          /* Reference param save area */
 784         loadgp                          /* Thread could have been in a module */
 785 #endif
 786 #ifndef CONFIG_64BIT
 787         b       sys_exit
 788 #else
 789         load32  sys_exit, %r1
 790         bv      %r0(%r1)
 791 #endif
 792         ldi     0, %r26
 793 ENDPROC(ret_from_kernel_thread)
 794
 795         .import sys_execve, code
 796 ENTRY(__execve)
 797         copy    %r2, %r15
 798         copy    %r30, %r16
 799         ldo     PT_SZ_ALGN(%r30), %r30
 800         STREG   %r26, PT_GR26(%r16)
 801         STREG   %r25, PT_GR25(%r16)
 802         STREG   %r24, PT_GR24(%r16)
 803 #ifdef CONFIG_64BIT
 804         ldo     -16(%r30),%r29          /* Reference param save area */
 805 #endif
 806         BL      sys_execve, %r2
 807         copy    %r16, %r26
 808
 809         cmpib,=,n 0,%r28,intr_return    /* forward */
 810
 811         /* yes, this will trap and die. */
 812         copy    %r15, %r2
 813         copy    %r16, %r30
 814         bv      %r0(%r2)
 815         nop
 816 ENDPROC(__execve)
 817
 818
 819         /*
 820          * struct task_struct *_switch_to(struct task_struct *prev,
 821          *      struct task_struct *next)
 822          *
 823          * switch kernel stacks and return prev */
 824 ENTRY(_switch_to)
 825         STREG    %r2, -RP_OFFSET(%r30)
 826
 827         callee_save_float
 828         callee_save
 829
 830         load32  _switch_to_ret, %r2
 831
 832         STREG   %r2, TASK_PT_KPC(%r26)
 833         LDREG   TASK_PT_KPC(%r25), %r2
 834
 835         STREG   %r30, TASK_PT_KSP(%r26)
 836         LDREG   TASK_PT_KSP(%r25), %r30
 837         LDREG   TASK_THREAD_INFO(%r25), %r25
 838         bv      %r0(%r2)
 839         mtctl   %r25,%cr30
 840
 841 _switch_to_ret:
 842         mtctl   %r0, %cr0               /* Needed for single stepping */
 843         callee_rest
 844         callee_rest_float
 845
 846         LDREG   -RP_OFFSET(%r30), %r2
 847         bv      %r0(%r2)
 848         copy    %r26, %r28
 849 ENDPROC(_switch_to)
 850
 851         /*
 852          * Common rfi return path for interruptions, kernel execve, and
 853          * sys_rt_sigreturn (sometimes).  The sys_rt_sigreturn syscall will
 854          * return via this path if the signal was received when the process
 855          * was running; if the process was blocked on a syscall then the
 856          * normal syscall_exit path is used.  All syscalls for traced
 857          * proceses exit via intr_restore.
 858          *
 859          * XXX If any syscalls that change a processes space id ever exit
 860          * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
 861          * adjust IASQ[0..1].
 862          *
 863          */
 864
 865         .align  PAGE_SIZE
 866
 867 ENTRY(syscall_exit_rfi)
 868         mfctl   %cr30,%r16
 869         LDREG   TI_TASK(%r16), %r16     /* thread_info -> task_struct */
 870         ldo     TASK_REGS(%r16),%r16
 871         /* Force iaoq to userspace, as the user has had access to our current
 872          * context via sigcontext. Also Filter the PSW for the same reason.
 873          */
 874         LDREG   PT_IAOQ0(%r16),%r19
 875         depi    3,31,2,%r19
 876         STREG   %r19,PT_IAOQ0(%r16)
 877         LDREG   PT_IAOQ1(%r16),%r19
 878         depi    3,31,2,%r19
 879         STREG   %r19,PT_IAOQ1(%r16)
 880         LDREG   PT_PSW(%r16),%r19
 881         load32  USER_PSW_MASK,%r1
 882 #ifdef CONFIG_64BIT
 883         load32  USER_PSW_HI_MASK,%r20
 884         depd    %r20,31,32,%r1
 885 #endif
 886         and     %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
 887         load32  USER_PSW,%r1
 888         or      %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
 889         STREG   %r19,PT_PSW(%r16)
 890
 891         /*
 892          * If we aren't being traced, we never saved space registers
 893          * (we don't store them in the sigcontext), so set them
 894          * to "proper" values now (otherwise we'll wind up restoring
 895          * whatever was last stored in the task structure, which might
 896          * be inconsistent if an interrupt occurred while on the gateway
 897          * page). Note that we may be "trashing" values the user put in
 898          * them, but we don't support the user changing them.
 899          */
 900
 901         STREG   %r0,PT_SR2(%r16)
 902         mfsp    %sr3,%r19
 903         STREG   %r19,PT_SR0(%r16)
 904         STREG   %r19,PT_SR1(%r16)
 905         STREG   %r19,PT_SR3(%r16)
 906         STREG   %r19,PT_SR4(%r16)
 907         STREG   %r19,PT_SR5(%r16)
 908         STREG   %r19,PT_SR6(%r16)
 909         STREG   %r19,PT_SR7(%r16)
 910
 911 intr_return:
 912         /* NOTE: Need to enable interrupts incase we schedule. */
 913         ssm     PSW_SM_I, %r0
 914
 915 intr_check_resched:
 916
 917         /* check for reschedule */
 918         mfctl   %cr30,%r1
 919         LDREG   TI_FLAGS(%r1),%r19      /* sched.h: TIF_NEED_RESCHED */
 920         bb,<,n  %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
 921
 922         .import do_notify_resume,code
 923 intr_check_sig:
 924         /* As above */
 925         mfctl   %cr30,%r1
 926         LDREG   TI_FLAGS(%r1),%r19
 927         ldi     (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
 928         and,COND(<>)    %r19, %r20, %r0
 929         b,n     intr_restore    /* skip past if we've nothing to do */
 930
 931         /* This check is critical to having LWS
 932          * working. The IASQ is zero on the gateway
 933          * page and we cannot deliver any signals until
 934          * we get off the gateway page.
 935          *
 936          * Only do signals if we are returning to user space
 937          */
 938         LDREG   PT_IASQ0(%r16), %r20
 939         cmpib,COND(=),n 0,%r20,intr_restore /* backward */
 940         LDREG   PT_IASQ1(%r16), %r20
 941         cmpib,COND(=),n 0,%r20,intr_restore /* backward */
 942
 943         copy    %r0, %r25                       /* long in_syscall = 0 */
 944 #ifdef CONFIG_64BIT
 945         ldo     -16(%r30),%r29                  /* Reference param save area */
 946 #endif
 947
 948         BL      do_notify_resume,%r2
 949         copy    %r16, %r26                      /* struct pt_regs *regs */
 950
 951         b,n     intr_check_sig
 952
 953 intr_restore:
 954         copy            %r16,%r29
 955         ldo             PT_FR31(%r29),%r1
 956         rest_fp         %r1
 957         rest_general    %r29
 958
 959         /* inverse of virt_map */
 960         pcxt_ssm_bug
 961         rsm             PSW_SM_QUIET,%r0        /* prepare for rfi */
 962         tophys_r1       %r29
 963
 964         /* Restore space id's and special cr's from PT_REGS
 965          * structure pointed to by r29
 966          */
 967         rest_specials   %r29
 968
 969         /* IMPORTANT: rest_stack restores r29 last (we are using it)!
 970          * It also restores r1 and r30.
 971          */
 972         rest_stack
 973
 974         rfi
 975         nop
 976
 977 #ifndef CONFIG_PREEMPT
 978 # define intr_do_preempt        intr_restore
 979 #endif /* !CONFIG_PREEMPT */
 980
 981         .import schedule,code
 982 intr_do_resched:
 983         /* Only call schedule on return to userspace. If we're returning
 984          * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
 985          * we jump back to intr_restore.
 986          */
 987         LDREG   PT_IASQ0(%r16), %r20
 988         cmpib,COND(=)   0, %r20, intr_do_preempt
 989         nop
 990         LDREG   PT_IASQ1(%r16), %r20
 991         cmpib,COND(=)   0, %r20, intr_do_preempt
 992         nop
 993
 994 #ifdef CONFIG_64BIT
 995         ldo     -16(%r30),%r29          /* Reference param save area */
 996 #endif
 997
 998         ldil    L%intr_check_sig, %r2
 999 #ifndef CONFIG_64BIT
1000         b       schedule
1001 #else
1002         load32  schedule, %r20
1003         bv      %r0(%r20)
1004 #endif
1005         ldo     R%intr_check_sig(%r2), %r2
1006
1007         /* preempt the current task on returning to kernel
1008          * mode from an interrupt, iff need_resched is set,
1009          * and preempt_count is 0. otherwise, we continue on
1010          * our merry way back to the current running task.
1011          */
1012 #ifdef CONFIG_PREEMPT
1013         .import preempt_schedule_irq,code
1014 intr_do_preempt:
1015         rsm     PSW_SM_I, %r0           /* disable interrupts */
1016
1017         /* current_thread_info()->preempt_count */
1018         mfctl   %cr30, %r1
1019         LDREG   TI_PRE_COUNT(%r1), %r19
1020         cmpib,COND(<>)  0, %r19, intr_restore   /* if preempt_count > 0 */
1021         nop                             /* prev insn branched backwards */
1022
1023         /* check if we interrupted a critical path */
1024         LDREG   PT_PSW(%r16), %r20
1025         bb,<,n  %r20, 31 - PSW_SM_I, intr_restore
1026         nop
1027
1028         BL      preempt_schedule_irq, %r2
1029         nop
1030
1031         b,n     intr_restore            /* ssm PSW_SM_I done by intr_restore */
1032 #endif /* CONFIG_PREEMPT */
1033
1034         /*
1035          * External interrupts.
1036          */
1037
1038 intr_extint:
1039         cmpib,COND(=),n 0,%r16,1f
1040
1041         get_stack_use_cr30
1042         b,n 2f
1043
1044 1:
1045         get_stack_use_r30
1046 2:
1047         save_specials   %r29
1048         virt_map
1049         save_general    %r29
1050
1051         ldo     PT_FR0(%r29), %r24
1052         save_fp %r24
1053
1054         loadgp
1055
1056         copy    %r29, %r26      /* arg0 is pt_regs */
1057         copy    %r29, %r16      /* save pt_regs */
1058
1059         ldil    L%intr_return, %r2
1060
1061 #ifdef CONFIG_64BIT
1062         ldo     -16(%r30),%r29  /* Reference param save area */
1063 #endif
1064
1065         b       do_cpu_irq_mask
1066         ldo     R%intr_return(%r2), %r2 /* return to intr_return, not here */
1067 ENDPROC(syscall_exit_rfi)
1068
1069
1070         /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1071
1072 ENTRY(intr_save)                /* for os_hpmc */
1073         mfsp    %sr7,%r16
1074         cmpib,COND(=),n 0,%r16,1f
1075         get_stack_use_cr30
1076         b       2f
1077         copy    %r8,%r26
1078
1079 1:
1080         get_stack_use_r30
1081         copy    %r8,%r26
1082
1083 2:
1084         save_specials   %r29
1085
1086         /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1087
1088         /*
1089          * FIXME: 1) Use a #define for the hardwired "6" below (and in
1090          *           traps.c.
1091          *        2) Once we start executing code above 4 Gb, we need
1092          *           to adjust iasq/iaoq here in the same way we
1093          *           adjust isr/ior below.
1094          */
1095
1096         cmpib,COND(=),n        6,%r26,skip_save_ior
1097
1098
1099         mfctl           %cr20, %r16 /* isr */
1100         nop             /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1101         mfctl           %cr21, %r17 /* ior */
1102
1103
1104 #ifdef CONFIG_64BIT
1105         /*
1106          * If the interrupted code was running with W bit off (32 bit),
1107          * clear the b bits (bits 0 & 1) in the ior.
1108          * save_specials left ipsw value in r8 for us to test.
1109          */
1110         extrd,u,*<>     %r8,PSW_W_BIT,1,%r0
1111         depdi           0,1,2,%r17
1112
1113         /*
1114          * FIXME: This code has hardwired assumptions about the split
1115          *        between space bits and offset bits. This will change
1116          *        when we allow alternate page sizes.
1117          */
1118
1119         /* adjust isr/ior. */
1120         extrd,u         %r16,63,SPACEID_SHIFT,%r1       /* get high bits from isr for ior */
1121         depd            %r1,31,SPACEID_SHIFT,%r17       /* deposit them into ior */
1122         depdi           0,63,SPACEID_SHIFT,%r16         /* clear them from isr */
1123 #endif
1124         STREG           %r16, PT_ISR(%r29)
1125         STREG           %r17, PT_IOR(%r29)
1126
1127
1128 skip_save_ior:
1129         virt_map
1130         save_general    %r29
1131
1132         ldo             PT_FR0(%r29), %r25
1133         save_fp         %r25
1134
1135         loadgp
1136
1137         copy            %r29, %r25      /* arg1 is pt_regs */
1138 #ifdef CONFIG_64BIT
1139         ldo             -16(%r30),%r29  /* Reference param save area */
1140 #endif
1141
1142         ldil            L%intr_check_sig, %r2
1143         copy            %r25, %r16      /* save pt_regs */
1144
1145         b               handle_interruption
1146         ldo             R%intr_check_sig(%r2), %r2
1147 ENDPROC(intr_save)
1148
1149
1150         /*
1151          * Note for all tlb miss handlers:
1152          *
1153          * cr24 contains a pointer to the kernel address space
1154          * page directory.
1155          *
1156          * cr25 contains a pointer to the current user address
1157          * space page directory.
1158          *
1159          * sr3 will contain the space id of the user address space
1160          * of the current running thread while that thread is
1161          * running in the kernel.
1162          */
1163
1164         /*
1165          * register number allocations.  Note that these are all
1166          * in the shadowed registers
1167          */
1168
1169         t0 = r1         /* temporary register 0 */
1170         va = r8         /* virtual address for which the trap occurred */
1171         t1 = r9         /* temporary register 1 */
1172         pte  = r16      /* pte/phys page # */
1173         prot = r17      /* prot bits */
1174         spc  = r24      /* space for which the trap occurred */
1175         ptp = r25       /* page directory/page table pointer */
1176
1177 #ifdef CONFIG_64BIT
1178
1179 dtlb_miss_20w:
1180         space_adjust    spc,va,t0
1181         get_pgd         spc,ptp
1182         space_check     spc,t0,dtlb_fault
1183
1184         L3_ptep         ptp,pte,t0,va,dtlb_check_alias_20w
1185
1186         update_ptep     ptp,pte,t0,t1
1187
1188         make_insert_tlb spc,pte,prot
1189
1190         idtlbt          pte,prot
1191
1192         rfir
1193         nop
1194
1195 dtlb_check_alias_20w:
1196         do_alias        spc,t0,t1,va,pte,prot,dtlb_fault,20
1197
1198         idtlbt          pte,prot
1199
1200         rfir
1201         nop
1202
1203 nadtlb_miss_20w:
1204         space_adjust    spc,va,t0
1205         get_pgd         spc,ptp
1206         space_check     spc,t0,nadtlb_fault
1207
1208         L3_ptep         ptp,pte,t0,va,nadtlb_check_alias_20w
1209
1210         update_ptep     ptp,pte,t0,t1
1211
1212         make_insert_tlb spc,pte,prot
1213
1214         idtlbt          pte,prot
1215
1216         rfir
1217         nop
1218
1219 nadtlb_check_alias_20w:
1220         do_alias        spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1221
1222         idtlbt          pte,prot
1223
1224         rfir
1225         nop
1226
1227 #else
1228
1229 dtlb_miss_11:
1230         get_pgd         spc,ptp
1231
1232         space_check     spc,t0,dtlb_fault
1233
1234         L2_ptep         ptp,pte,t0,va,dtlb_check_alias_11
1235
1236         update_ptep     ptp,pte,t0,t1
1237
1238         make_insert_tlb_11      spc,pte,prot
1239
1240         mfsp            %sr1,t0  /* Save sr1 so we can use it in tlb inserts */
1241         mtsp            spc,%sr1
1242
1243         idtlba          pte,(%sr1,va)
1244         idtlbp          prot,(%sr1,va)
1245
1246         mtsp            t0, %sr1        /* Restore sr1 */
1247
1248         rfir
1249         nop
1250
1251 dtlb_check_alias_11:
1252         do_alias        spc,t0,t1,va,pte,prot,dtlb_fault,11
1253
1254         idtlba          pte,(va)
1255         idtlbp          prot,(va)
1256
1257         rfir
1258         nop
1259
1260 nadtlb_miss_11:
1261         get_pgd         spc,ptp
1262
1263         space_check     spc,t0,nadtlb_fault
1264
1265         L2_ptep         ptp,pte,t0,va,nadtlb_check_alias_11
1266
1267         update_ptep     ptp,pte,t0,t1
1268
1269         make_insert_tlb_11      spc,pte,prot
1270
1271
1272         mfsp            %sr1,t0  /* Save sr1 so we can use it in tlb inserts */
1273         mtsp            spc,%sr1
1274
1275         idtlba          pte,(%sr1,va)
1276         idtlbp          prot,(%sr1,va)
1277
1278         mtsp            t0, %sr1        /* Restore sr1 */
1279
1280         rfir
1281         nop
1282
1283 nadtlb_check_alias_11:
1284         do_alias        spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1285
1286         idtlba          pte,(va)
1287         idtlbp          prot,(va)
1288
1289         rfir
1290         nop
1291
1292 dtlb_miss_20:
1293         space_adjust    spc,va,t0
1294         get_pgd         spc,ptp
1295         space_check     spc,t0,dtlb_fault
1296
1297         L2_ptep         ptp,pte,t0,va,dtlb_check_alias_20
1298
1299         update_ptep     ptp,pte,t0,t1
1300
1301         make_insert_tlb spc,pte,prot
1302
1303         f_extend        pte,t0
1304
1305         idtlbt          pte,prot
1306
1307         rfir
1308         nop
1309
1310 dtlb_check_alias_20:
1311         do_alias        spc,t0,t1,va,pte,prot,dtlb_fault,20
1312
1313         idtlbt          pte,prot
1314
1315         rfir
1316         nop
1317
1318 nadtlb_miss_20:
1319         get_pgd         spc,ptp
1320
1321         space_check     spc,t0,nadtlb_fault
1322
1323         L2_ptep         ptp,pte,t0,va,nadtlb_check_alias_20
1324
1325         update_ptep     ptp,pte,t0,t1
1326
1327         make_insert_tlb spc,pte,prot
1328
1329         f_extend        pte,t0
1330
1331         idtlbt          pte,prot
1332
1333         rfir
1334         nop
1335
1336 nadtlb_check_alias_20:
1337         do_alias        spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1338
1339         idtlbt          pte,prot
1340
1341         rfir
1342         nop
1343
1344 #endif
1345
1346 nadtlb_emulate:
1347
1348         /*
1349          * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1350          * probei instructions. We don't want to fault for these
1351          * instructions (not only does it not make sense, it can cause
1352          * deadlocks, since some flushes are done with the mmap
1353          * semaphore held). If the translation doesn't exist, we can't
1354          * insert a translation, so have to emulate the side effects
1355          * of the instruction. Since we don't insert a translation
1356          * we can get a lot of faults during a flush loop, so it makes
1357          * sense to try to do it here with minimum overhead. We only
1358          * emulate fdc,fic,pdc,probew,prober instructions whose base
1359          * and index registers are not shadowed. We defer everything
1360          * else to the "slow" path.
1361          */
1362
1363         mfctl           %cr19,%r9 /* Get iir */
1364
1365         /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1366            Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1367
1368         /* Checks for fdc,fdce,pdc,"fic,4f" only */
1369         ldi             0x280,%r16
1370         and             %r9,%r16,%r17
1371         cmpb,<>,n       %r16,%r17,nadtlb_probe_check
1372         bb,>=,n         %r9,26,nadtlb_nullify  /* m bit not set, just nullify */
1373         BL              get_register,%r25
1374         extrw,u         %r9,15,5,%r8           /* Get index register # */
1375         cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */
1376         copy            %r1,%r24
1377         BL              get_register,%r25
1378         extrw,u         %r9,10,5,%r8           /* Get base register # */
1379         cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */
1380         BL              set_register,%r25
1381         add,l           %r1,%r24,%r1           /* doesn't affect c/b bits */
1382
1383 nadtlb_nullify:
1384         mfctl           %ipsw,%r8
1385         ldil            L%PSW_N,%r9
1386         or              %r8,%r9,%r8            /* Set PSW_N */
1387         mtctl           %r8,%ipsw
1388
1389         rfir
1390         nop
1391
1392         /*
1393                 When there is no translation for the probe address then we
1394                 must nullify the insn and return zero in the target regsiter.
1395                 This will indicate to the calling code that it does not have
1396                 write/read privileges to this address.
1397
1398                 This should technically work for prober and probew in PA 1.1,
1399                 and also probe,r and probe,w in PA 2.0
1400
1401                 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1402                 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1403
1404         */
1405 nadtlb_probe_check:
1406         ldi             0x80,%r16
1407         and             %r9,%r16,%r17
1408         cmpb,<>,n       %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1409         BL              get_register,%r25      /* Find the target register */
1410         extrw,u         %r9,31,5,%r8           /* Get target register */
1411         cmpib,COND(=),n        -1,%r1,nadtlb_fault    /* have to use slow path */
1412         BL              set_register,%r25
1413         copy            %r0,%r1                /* Write zero to target register */
1414         b nadtlb_nullify                       /* Nullify return insn */
1415         nop
1416
1417
1418 #ifdef CONFIG_64BIT
1419 itlb_miss_20w:
1420
1421         /*
1422          * I miss is a little different, since we allow users to fault
1423          * on the gateway page which is in the kernel address space.
1424          */
1425
1426         space_adjust    spc,va,t0
1427         get_pgd         spc,ptp
1428         space_check     spc,t0,itlb_fault
1429
1430         L3_ptep         ptp,pte,t0,va,itlb_fault
1431
1432         update_ptep     ptp,pte,t0,t1
1433
1434         make_insert_tlb spc,pte,prot
1435
1436         iitlbt          pte,prot
1437
1438         rfir
1439         nop
1440
1441 naitlb_miss_20w:
1442
1443         /*
1444          * I miss is a little different, since we allow users to fault
1445          * on the gateway page which is in the kernel address space.
1446          */
1447
1448         space_adjust    spc,va,t0
1449         get_pgd         spc,ptp
1450         space_check     spc,t0,naitlb_fault
1451
1452         L3_ptep         ptp,pte,t0,va,naitlb_check_alias_20w
1453
1454         update_ptep     ptp,pte,t0,t1
1455
1456         make_insert_tlb spc,pte,prot
1457
1458         iitlbt          pte,prot
1459
1460         rfir
1461         nop
1462
1463 naitlb_check_alias_20w:
1464         do_alias        spc,t0,t1,va,pte,prot,naitlb_fault,20
1465
1466         iitlbt          pte,prot
1467
1468         rfir
1469         nop
1470
1471 #else
1472
1473 itlb_miss_11:
1474         get_pgd         spc,ptp
1475
1476         space_check     spc,t0,itlb_fault
1477
1478         L2_ptep         ptp,pte,t0,va,itlb_fault
1479
1480         update_ptep     ptp,pte,t0,t1
1481
1482         make_insert_tlb_11      spc,pte,prot
1483
1484         mfsp            %sr1,t0  /* Save sr1 so we can use it in tlb inserts */
1485         mtsp            spc,%sr1
1486
1487         iitlba          pte,(%sr1,va)
1488         iitlbp          prot,(%sr1,va)
1489
1490         mtsp            t0, %sr1        /* Restore sr1 */
1491
1492         rfir
1493         nop
1494
1495 naitlb_miss_11:
1496         get_pgd         spc,ptp
1497
1498         space_check     spc,t0,naitlb_fault
1499
1500         L2_ptep         ptp,pte,t0,va,naitlb_check_alias_11
1501
1502         update_ptep     ptp,pte,t0,t1
1503
1504         make_insert_tlb_11      spc,pte,prot
1505
1506         mfsp            %sr1,t0  /* Save sr1 so we can use it in tlb inserts */
1507         mtsp            spc,%sr1
1508
1509         iitlba          pte,(%sr1,va)
1510         iitlbp          prot,(%sr1,va)
1511
1512         mtsp            t0, %sr1        /* Restore sr1 */
1513
1514         rfir
1515         nop
1516
1517 naitlb_check_alias_11:
1518         do_alias        spc,t0,t1,va,pte,prot,itlb_fault,11
1519
1520         iitlba          pte,(%sr0, va)
1521         iitlbp          prot,(%sr0, va)
1522
1523         rfir
1524         nop
1525
1526
1527 itlb_miss_20:
1528         get_pgd         spc,ptp
1529
1530         space_check     spc,t0,itlb_fault
1531
1532         L2_ptep         ptp,pte,t0,va,itlb_fault
1533
1534         update_ptep     ptp,pte,t0,t1
1535
1536         make_insert_tlb spc,pte,prot
1537
1538         f_extend        pte,t0
1539
1540         iitlbt          pte,prot
1541
1542         rfir
1543         nop
1544
1545 naitlb_miss_20:
1546         get_pgd         spc,ptp
1547
1548         space_check     spc,t0,naitlb_fault
1549
1550         L2_ptep         ptp,pte,t0,va,naitlb_check_alias_20
1551
1552         update_ptep     ptp,pte,t0,t1
1553
1554         make_insert_tlb spc,pte,prot
1555
1556         f_extend        pte,t0
1557
1558         iitlbt          pte,prot
1559
1560         rfir
1561         nop
1562
1563 naitlb_check_alias_20:
1564         do_alias        spc,t0,t1,va,pte,prot,naitlb_fault,20
1565
1566         iitlbt          pte,prot
1567
1568         rfir
1569         nop
1570
1571 #endif
1572
1573 #ifdef CONFIG_64BIT
1574
1575 dbit_trap_20w:
1576         space_adjust    spc,va,t0
1577         get_pgd         spc,ptp
1578         space_check     spc,t0,dbit_fault
1579
1580         L3_ptep         ptp,pte,t0,va,dbit_fault
1581
1582 #ifdef CONFIG_SMP
1583         cmpib,COND(=),n        0,spc,dbit_nolock_20w
1584         load32          PA(pa_dbit_lock),t0
1585
1586 dbit_spin_20w:
1587         LDCW            0(t0),t1
1588         cmpib,COND(=)         0,t1,dbit_spin_20w
1589         nop
1590
1591 dbit_nolock_20w:
1592 #endif
1593         update_dirty    ptp,pte,t1
1594
1595         make_insert_tlb spc,pte,prot
1596
1597         idtlbt          pte,prot
1598 #ifdef CONFIG_SMP
1599         cmpib,COND(=),n        0,spc,dbit_nounlock_20w
1600         ldi             1,t1
1601         stw             t1,0(t0)
1602
1603 dbit_nounlock_20w:
1604 #endif
1605
1606         rfir
1607         nop
1608 #else
1609
1610 dbit_trap_11:
1611
1612         get_pgd         spc,ptp
1613
1614         space_check     spc,t0,dbit_fault
1615
1616         L2_ptep         ptp,pte,t0,va,dbit_fault
1617
1618 #ifdef CONFIG_SMP
1619         cmpib,COND(=),n        0,spc,dbit_nolock_11
1620         load32          PA(pa_dbit_lock),t0
1621
1622 dbit_spin_11:
1623         LDCW            0(t0),t1
1624         cmpib,=         0,t1,dbit_spin_11
1625         nop
1626
1627 dbit_nolock_11:
1628 #endif
1629         update_dirty    ptp,pte,t1
1630
1631         make_insert_tlb_11      spc,pte,prot
1632
1633         mfsp            %sr1,t1  /* Save sr1 so we can use it in tlb inserts */
1634         mtsp            spc,%sr1
1635
1636         idtlba          pte,(%sr1,va)
1637         idtlbp          prot,(%sr1,va)
1638
1639         mtsp            t1, %sr1     /* Restore sr1 */
1640 #ifdef CONFIG_SMP
1641         cmpib,COND(=),n        0,spc,dbit_nounlock_11
1642         ldi             1,t1
1643         stw             t1,0(t0)
1644
1645 dbit_nounlock_11:
1646 #endif
1647
1648         rfir
1649         nop
1650
1651 dbit_trap_20:
1652         get_pgd         spc,ptp
1653
1654         space_check     spc,t0,dbit_fault
1655
1656         L2_ptep         ptp,pte,t0,va,dbit_fault
1657
1658 #ifdef CONFIG_SMP
1659         cmpib,COND(=),n        0,spc,dbit_nolock_20
1660         load32          PA(pa_dbit_lock),t0
1661
1662 dbit_spin_20:
1663         LDCW            0(t0),t1
1664         cmpib,=         0,t1,dbit_spin_20
1665         nop
1666
1667 dbit_nolock_20:
1668 #endif
1669         update_dirty    ptp,pte,t1
1670
1671         make_insert_tlb spc,pte,prot
1672
1673         f_extend        pte,t1
1674
1675         idtlbt          pte,prot
1676
1677 #ifdef CONFIG_SMP
1678         cmpib,COND(=),n        0,spc,dbit_nounlock_20
1679         ldi             1,t1
1680         stw             t1,0(t0)
1681
1682 dbit_nounlock_20:
1683 #endif
1684
1685         rfir
1686         nop
1687 #endif
1688
1689         .import handle_interruption,code
1690
1691 kernel_bad_space:
1692         b               intr_save
1693         ldi             31,%r8  /* Use an unused code */
1694
1695 dbit_fault:
1696         b               intr_save
1697         ldi             20,%r8
1698
1699 itlb_fault:
1700         b               intr_save
1701         ldi             6,%r8
1702
1703 nadtlb_fault:
1704         b               intr_save
1705         ldi             17,%r8
1706
1707 naitlb_fault:
1708         b               intr_save
1709         ldi             16,%r8
1710
1711 dtlb_fault:
1712         b               intr_save
1713         ldi             15,%r8
1714
1715         /* Register saving semantics for system calls:
1716
1717            %r1             clobbered by system call macro in userspace
1718            %r2             saved in PT_REGS by gateway page
1719            %r3  - %r18     preserved by C code (saved by signal code)
1720            %r19 - %r20     saved in PT_REGS by gateway page
1721            %r21 - %r22     non-standard syscall args
1722                            stored in kernel stack by gateway page
1723            %r23 - %r26     arg3-arg0, saved in PT_REGS by gateway page
1724            %r27 - %r30     saved in PT_REGS by gateway page
1725            %r31            syscall return pointer
1726          */
1727
1728         /* Floating point registers (FIXME: what do we do with these?)
1729
1730            %fr0  - %fr3    status/exception, not preserved
1731            %fr4  - %fr7    arguments
1732            %fr8  - %fr11   not preserved by C code
1733            %fr12 - %fr21   preserved by C code
1734            %fr22 - %fr31   not preserved by C code
1735          */
1736
1737         .macro  reg_save regs
1738         STREG   %r3, PT_GR3(\regs)
1739         STREG   %r4, PT_GR4(\regs)
1740         STREG   %r5, PT_GR5(\regs)
1741         STREG   %r6, PT_GR6(\regs)
1742         STREG   %r7, PT_GR7(\regs)
1743         STREG   %r8, PT_GR8(\regs)
1744         STREG   %r9, PT_GR9(\regs)
1745         STREG   %r10,PT_GR10(\regs)
1746         STREG   %r11,PT_GR11(\regs)
1747         STREG   %r12,PT_GR12(\regs)
1748         STREG   %r13,PT_GR13(\regs)
1749         STREG   %r14,PT_GR14(\regs)
1750         STREG   %r15,PT_GR15(\regs)
1751         STREG   %r16,PT_GR16(\regs)
1752         STREG   %r17,PT_GR17(\regs)
1753         STREG   %r18,PT_GR18(\regs)
1754         .endm
1755
1756         .macro  reg_restore regs
1757         LDREG   PT_GR3(\regs), %r3
1758         LDREG   PT_GR4(\regs), %r4
1759         LDREG   PT_GR5(\regs), %r5
1760         LDREG   PT_GR6(\regs), %r6
1761         LDREG   PT_GR7(\regs), %r7
1762         LDREG   PT_GR8(\regs), %r8
1763         LDREG   PT_GR9(\regs), %r9
1764         LDREG   PT_GR10(\regs),%r10
1765         LDREG   PT_GR11(\regs),%r11
1766         LDREG   PT_GR12(\regs),%r12
1767         LDREG   PT_GR13(\regs),%r13
1768         LDREG   PT_GR14(\regs),%r14
1769         LDREG   PT_GR15(\regs),%r15
1770         LDREG   PT_GR16(\regs),%r16
1771         LDREG   PT_GR17(\regs),%r17
1772         LDREG   PT_GR18(\regs),%r18
1773         .endm
1774
1775 ENTRY(sys_fork_wrapper)
1776         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1777         ldo     TASK_REGS(%r1),%r1
1778         reg_save %r1
1779         mfctl   %cr27, %r3
1780         STREG   %r3, PT_CR27(%r1)
1781
1782         STREG   %r2,-RP_OFFSET(%r30)
1783         ldo     FRAME_SIZE(%r30),%r30
1784 #ifdef CONFIG_64BIT
1785         ldo     -16(%r30),%r29          /* Reference param save area */
1786 #endif
1787
1788         /* These are call-clobbered registers and therefore
1789            also syscall-clobbered (we hope). */
1790         STREG   %r2,PT_GR19(%r1)        /* save for child */
1791         STREG   %r30,PT_GR21(%r1)
1792
1793         LDREG   PT_GR30(%r1),%r25
1794         copy    %r1,%r24
1795         BL      sys_clone,%r2
1796         ldi     SIGCHLD,%r26
1797
1798         LDREG   -RP_OFFSET-FRAME_SIZE(%r30),%r2
1799 wrapper_exit:
1800         ldo     -FRAME_SIZE(%r30),%r30          /* get the stackframe */
1801         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1802         ldo     TASK_REGS(%r1),%r1       /* get pt regs */
1803
1804         LDREG   PT_CR27(%r1), %r3
1805         mtctl   %r3, %cr27
1806         reg_restore %r1
1807
1808         /* strace expects syscall # to be preserved in r20 */
1809         ldi     __NR_fork,%r20
1810         bv %r0(%r2)
1811         STREG   %r20,PT_GR20(%r1)
1812 ENDPROC(sys_fork_wrapper)
1813
1814         /* Set the return value for the child */
1815 ENTRY(child_return)
1816         BL      schedule_tail, %r2
1817         nop
1818
1819         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE-FRAME_SIZE(%r30), %r1
1820         LDREG   TASK_PT_GR19(%r1),%r2
1821         b       wrapper_exit
1822         copy    %r0,%r28
1823 ENDPROC(child_return)
1824
1825
1826 ENTRY(sys_clone_wrapper)
1827         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1828         ldo     TASK_REGS(%r1),%r1      /* get pt regs */
1829         reg_save %r1
1830         mfctl   %cr27, %r3
1831         STREG   %r3, PT_CR27(%r1)
1832
1833         STREG   %r2,-RP_OFFSET(%r30)
1834         ldo     FRAME_SIZE(%r30),%r30
1835 #ifdef CONFIG_64BIT
1836         ldo     -16(%r30),%r29          /* Reference param save area */
1837 #endif
1838
1839         /* WARNING - Clobbers r19 and r21, userspace must save these! */
1840         STREG   %r2,PT_GR19(%r1)        /* save for child */
1841         STREG   %r30,PT_GR21(%r1)
1842         BL      sys_clone,%r2
1843         copy    %r1,%r24
1844
1845         b       wrapper_exit
1846         LDREG   -RP_OFFSET-FRAME_SIZE(%r30),%r2
1847 ENDPROC(sys_clone_wrapper)
1848
1849
1850 ENTRY(sys_vfork_wrapper)
1851         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1852         ldo     TASK_REGS(%r1),%r1      /* get pt regs */
1853         reg_save %r1
1854         mfctl   %cr27, %r3
1855         STREG   %r3, PT_CR27(%r1)
1856
1857         STREG   %r2,-RP_OFFSET(%r30)
1858         ldo     FRAME_SIZE(%r30),%r30
1859 #ifdef CONFIG_64BIT
1860         ldo     -16(%r30),%r29          /* Reference param save area */
1861 #endif
1862
1863         STREG   %r2,PT_GR19(%r1)        /* save for child */
1864         STREG   %r30,PT_GR21(%r1)
1865
1866         BL      sys_vfork,%r2
1867         copy    %r1,%r26
1868
1869         b       wrapper_exit
1870         LDREG   -RP_OFFSET-FRAME_SIZE(%r30),%r2
1871 ENDPROC(sys_vfork_wrapper)
1872
1873
1874         .macro  execve_wrapper execve
1875         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1876         ldo     TASK_REGS(%r1),%r1      /* get pt regs */
1877
1878         /*
1879          * Do we need to save/restore r3-r18 here?
1880          * I don't think so. why would new thread need old
1881          * threads registers?
1882          */
1883
1884         /* %arg0 - %arg3 are already saved for us. */
1885
1886         STREG %r2,-RP_OFFSET(%r30)
1887         ldo FRAME_SIZE(%r30),%r30
1888 #ifdef CONFIG_64BIT
1889         ldo     -16(%r30),%r29          /* Reference param save area */
1890 #endif
1891         BL \execve,%r2
1892         copy %r1,%arg0
1893
1894         ldo -FRAME_SIZE(%r30),%r30
1895         LDREG -RP_OFFSET(%r30),%r2
1896
1897         /* If exec succeeded we need to load the args */
1898
1899         ldo -1024(%r0),%r1
1900         cmpb,>>= %r28,%r1,error_\execve
1901         copy %r2,%r19
1902
1903 error_\execve:
1904         bv %r0(%r19)
1905         nop
1906         .endm
1907
1908         .import sys_execve
1909 ENTRY(sys_execve_wrapper)
1910         execve_wrapper sys_execve
1911 ENDPROC(sys_execve_wrapper)
1912
1913 #ifdef CONFIG_64BIT
1914         .import sys32_execve
1915 ENTRY(sys32_execve_wrapper)
1916         execve_wrapper sys32_execve
1917 ENDPROC(sys32_execve_wrapper)
1918 #endif
1919
1920 ENTRY(sys_rt_sigreturn_wrapper)
1921         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1922         ldo     TASK_REGS(%r26),%r26    /* get pt regs */
1923         /* Don't save regs, we are going to restore them from sigcontext. */
1924         STREG   %r2, -RP_OFFSET(%r30)
1925 #ifdef CONFIG_64BIT
1926         ldo     FRAME_SIZE(%r30), %r30
1927         BL      sys_rt_sigreturn,%r2
1928         ldo     -16(%r30),%r29          /* Reference param save area */
1929 #else
1930         BL      sys_rt_sigreturn,%r2
1931         ldo     FRAME_SIZE(%r30), %r30
1932 #endif
1933
1934         ldo     -FRAME_SIZE(%r30), %r30
1935         LDREG   -RP_OFFSET(%r30), %r2
1936
1937         /* FIXME: I think we need to restore a few more things here. */
1938         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1939         ldo     TASK_REGS(%r1),%r1      /* get pt regs */
1940         reg_restore %r1
1941
1942         /* If the signal was received while the process was blocked on a
1943          * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1944          * take us to syscall_exit_rfi and on to intr_return.
1945          */
1946         bv      %r0(%r2)
1947         LDREG   PT_GR28(%r1),%r28  /* reload original r28 for syscall_exit */
1948 ENDPROC(sys_rt_sigreturn_wrapper)
1949
1950 ENTRY(sys_sigaltstack_wrapper)
1951         /* Get the user stack pointer */
1952         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1953         ldo     TASK_REGS(%r1),%r24     /* get pt regs */
1954         LDREG   TASK_PT_GR30(%r24),%r24
1955         STREG   %r2, -RP_OFFSET(%r30)
1956 #ifdef CONFIG_64BIT
1957         ldo     FRAME_SIZE(%r30), %r30
1958         BL      do_sigaltstack,%r2
1959         ldo     -16(%r30),%r29          /* Reference param save area */
1960 #else
1961         BL      do_sigaltstack,%r2
1962         ldo     FRAME_SIZE(%r30), %r30
1963 #endif
1964
1965         ldo     -FRAME_SIZE(%r30), %r30
1966         LDREG   -RP_OFFSET(%r30), %r2
1967         bv      %r0(%r2)
1968         nop
1969 ENDPROC(sys_sigaltstack_wrapper)
1970
1971 #ifdef CONFIG_64BIT
1972 ENTRY(sys32_sigaltstack_wrapper)
1973         /* Get the user stack pointer */
1974         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r24
1975         LDREG   TASK_PT_GR30(%r24),%r24
1976         STREG   %r2, -RP_OFFSET(%r30)
1977         ldo     FRAME_SIZE(%r30), %r30
1978         BL      do_sigaltstack32,%r2
1979         ldo     -16(%r30),%r29          /* Reference param save area */
1980
1981         ldo     -FRAME_SIZE(%r30), %r30
1982         LDREG   -RP_OFFSET(%r30), %r2
1983         bv      %r0(%r2)
1984         nop
1985 ENDPROC(sys32_sigaltstack_wrapper)
1986 #endif
1987
1988 ENTRY(syscall_exit)
1989         /* NOTE: HP-UX syscalls also come through here
1990          * after hpux_syscall_exit fixes up return
1991          * values. */
1992
1993         /* NOTE: Not all syscalls exit this way.  rt_sigreturn will exit
1994          * via syscall_exit_rfi if the signal was received while the process
1995          * was running.
1996          */
1997
1998         /* save return value now */
1999
2000         mfctl     %cr30, %r1
2001         LDREG     TI_TASK(%r1),%r1
2002         STREG     %r28,TASK_PT_GR28(%r1)
2003
2004 #ifdef CONFIG_HPUX
2005 /* <linux/personality.h> cannot be easily included */
2006 #define PER_HPUX 0x10
2007         ldw     TASK_PERSONALITY(%r1),%r19
2008
2009         /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
2010         ldo       -PER_HPUX(%r19), %r19
2011         cmpib,COND(<>),n 0,%r19,1f
2012
2013         /* Save other hpux returns if personality is PER_HPUX */
2014         STREG     %r22,TASK_PT_GR22(%r1)
2015         STREG     %r29,TASK_PT_GR29(%r1)
2016 1:
2017
2018 #endif /* CONFIG_HPUX */
2019
2020         /* Seems to me that dp could be wrong here, if the syscall involved
2021          * calling a module, and nothing got round to restoring dp on return.
2022          */
2023         loadgp
2024
2025 syscall_check_resched:
2026
2027         /* check for reschedule */
2028
2029         LDREG   TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19   /* long */
2030         bb,<,n  %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
2031
2032         .import do_signal,code
2033 syscall_check_sig:
2034         LDREG   TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
2035         ldi     (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
2036         and,COND(<>)    %r19, %r26, %r0
2037         b,n     syscall_restore /* skip past if we've nothing to do */
2038
2039 syscall_do_signal:
2040         /* Save callee-save registers (for sigcontext).
2041          * FIXME: After this point the process structure should be
2042          * consistent with all the relevant state of the process
2043          * before the syscall.  We need to verify this.
2044          */
2045         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2046         ldo     TASK_REGS(%r1), %r26            /* struct pt_regs *regs */
2047         reg_save %r26
2048
2049 #ifdef CONFIG_64BIT
2050         ldo     -16(%r30),%r29                  /* Reference param save area */
2051 #endif
2052
2053         BL      do_notify_resume,%r2
2054         ldi     1, %r25                         /* long in_syscall = 1 */
2055
2056         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2057         ldo     TASK_REGS(%r1), %r20            /* reload pt_regs */
2058         reg_restore %r20
2059
2060         b,n     syscall_check_sig
2061
2062 syscall_restore:
2063         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
2064
2065         /* Are we being ptraced? */
2066         ldw     TASK_FLAGS(%r1),%r19
2067         ldi     (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
2068         and,COND(=)     %r19,%r2,%r0
2069         b,n     syscall_restore_rfi
2070
2071         ldo     TASK_PT_FR31(%r1),%r19             /* reload fpregs */
2072         rest_fp %r19
2073
2074         LDREG   TASK_PT_SAR(%r1),%r19              /* restore SAR */
2075         mtsar   %r19
2076
2077         LDREG   TASK_PT_GR2(%r1),%r2               /* restore user rp */
2078         LDREG   TASK_PT_GR19(%r1),%r19
2079         LDREG   TASK_PT_GR20(%r1),%r20
2080         LDREG   TASK_PT_GR21(%r1),%r21
2081         LDREG   TASK_PT_GR22(%r1),%r22
2082         LDREG   TASK_PT_GR23(%r1),%r23
2083         LDREG   TASK_PT_GR24(%r1),%r24
2084         LDREG   TASK_PT_GR25(%r1),%r25
2085         LDREG   TASK_PT_GR26(%r1),%r26
2086         LDREG   TASK_PT_GR27(%r1),%r27     /* restore user dp */
2087         LDREG   TASK_PT_GR28(%r1),%r28     /* syscall return value */
2088         LDREG   TASK_PT_GR29(%r1),%r29
2089         LDREG   TASK_PT_GR31(%r1),%r31     /* restore syscall rp */
2090
2091         /* NOTE: We use rsm/ssm pair to make this operation atomic */
2092         LDREG   TASK_PT_GR30(%r1),%r1              /* Get user sp */
2093         rsm     PSW_SM_I, %r0
2094         copy    %r1,%r30                           /* Restore user sp */
2095         mfsp    %sr3,%r1                           /* Get user space id */
2096         mtsp    %r1,%sr7                           /* Restore sr7 */
2097         ssm     PSW_SM_I, %r0
2098
2099         /* Set sr2 to zero for userspace syscalls to work. */
2100         mtsp    %r0,%sr2
2101         mtsp    %r1,%sr4                           /* Restore sr4 */
2102         mtsp    %r1,%sr5                           /* Restore sr5 */
2103         mtsp    %r1,%sr6                           /* Restore sr6 */
2104
2105         depi    3,31,2,%r31                        /* ensure return to user mode. */
2106
2107 #ifdef CONFIG_64BIT
2108         /* decide whether to reset the wide mode bit
2109          *
2110          * For a syscall, the W bit is stored in the lowest bit
2111          * of sp.  Extract it and reset W if it is zero */
2112         extrd,u,*<>     %r30,63,1,%r1
2113         rsm     PSW_SM_W, %r0
2114         /* now reset the lowest bit of sp if it was set */
2115         xor     %r30,%r1,%r30
2116 #endif
2117         be,n    0(%sr3,%r31)                       /* return to user space */
2118
2119         /* We have to return via an RFI, so that PSW T and R bits can be set
2120          * appropriately.
2121          * This sets up pt_regs so we can return via intr_restore, which is not
2122          * the most efficient way of doing things, but it works.
2123          */
2124 syscall_restore_rfi:
2125         ldo     -1(%r0),%r2                        /* Set recovery cntr to -1 */
2126         mtctl   %r2,%cr0                           /*   for immediate trap */
2127         LDREG   TASK_PT_PSW(%r1),%r2               /* Get old PSW */
2128         ldi     0x0b,%r20                          /* Create new PSW */
2129         depi    -1,13,1,%r20                       /* C, Q, D, and I bits */
2130
2131         /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
2132          * set in thread_info.h and converted to PA bitmap
2133          * numbers in asm-offsets.c */
2134
2135         /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
2136         extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
2137         depi    -1,27,1,%r20                       /* R bit */
2138
2139         /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
2140         extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
2141         depi    -1,7,1,%r20                        /* T bit */
2142
2143         STREG   %r20,TASK_PT_PSW(%r1)
2144
2145         /* Always store space registers, since sr3 can be changed (e.g. fork) */
2146
2147         mfsp    %sr3,%r25
2148         STREG   %r25,TASK_PT_SR3(%r1)
2149         STREG   %r25,TASK_PT_SR4(%r1)
2150         STREG   %r25,TASK_PT_SR5(%r1)
2151         STREG   %r25,TASK_PT_SR6(%r1)
2152         STREG   %r25,TASK_PT_SR7(%r1)
2153         STREG   %r25,TASK_PT_IASQ0(%r1)
2154         STREG   %r25,TASK_PT_IASQ1(%r1)
2155
2156         /* XXX W bit??? */
2157         /* Now if old D bit is clear, it means we didn't save all registers
2158          * on syscall entry, so do that now.  This only happens on TRACEME
2159          * calls, or if someone attached to us while we were on a syscall.
2160          * We could make this more efficient by not saving r3-r18, but
2161          * then we wouldn't be able to use the common intr_restore path.
2162          * It is only for traced processes anyway, so performance is not
2163          * an issue.
2164          */
2165         bb,<    %r2,30,pt_regs_ok                  /* Branch if D set */
2166         ldo     TASK_REGS(%r1),%r25
2167         reg_save %r25                              /* Save r3 to r18 */
2168
2169         /* Save the current sr */
2170         mfsp    %sr0,%r2
2171         STREG   %r2,TASK_PT_SR0(%r1)
2172
2173         /* Save the scratch sr */
2174         mfsp    %sr1,%r2
2175         STREG   %r2,TASK_PT_SR1(%r1)
2176
2177         /* sr2 should be set to zero for userspace syscalls */
2178         STREG   %r0,TASK_PT_SR2(%r1)
2179
2180 pt_regs_ok:
2181         LDREG   TASK_PT_GR31(%r1),%r2
2182         depi    3,31,2,%r2                         /* ensure return to user mode. */
2183         STREG   %r2,TASK_PT_IAOQ0(%r1)
2184         ldo     4(%r2),%r2
2185         STREG   %r2,TASK_PT_IAOQ1(%r1)
2186         copy    %r25,%r16
2187         b       intr_restore
2188         nop
2189
2190         .import schedule,code
2191 syscall_do_resched:
2192         BL      schedule,%r2
2193 #ifdef CONFIG_64BIT
2194         ldo     -16(%r30),%r29          /* Reference param save area */
2195 #else
2196         nop
2197 #endif
2198         b       syscall_check_resched   /* if resched, we start over again */
2199         nop
2200 ENDPROC(syscall_exit)
2201
2202
2203 #ifdef CONFIG_FUNCTION_TRACER
2204         .import ftrace_function_trampoline,code
2205 ENTRY(_mcount)
2206         copy    %r3, %arg2
2207         b       ftrace_function_trampoline
2208         nop
2209 ENDPROC(_mcount)
2210
2211 ENTRY(return_to_handler)
2212         load32  return_trampoline, %rp
2213         copy    %ret0, %arg0
2214         copy    %ret1, %arg1
2215         b       ftrace_return_to_handler
2216         nop
2217 return_trampoline:
2218         copy    %ret0, %rp
2219         copy    %r23, %ret0
2220         copy    %r24, %ret1
2221
2222 .globl ftrace_stub
2223 ftrace_stub:
2224         bv      %r0(%rp)
2225         nop
2226 ENDPROC(return_to_handler)
2227 #endif  /* CONFIG_FUNCTION_TRACER */
2228
2229
2230 get_register:
2231         /*
2232          * get_register is used by the non access tlb miss handlers to
2233          * copy the value of the general register specified in r8 into
2234          * r1. This routine can't be used for shadowed registers, since
2235          * the rfir will restore the original value. So, for the shadowed
2236          * registers we put a -1 into r1 to indicate that the register
2237          * should not be used (the register being copied could also have
2238          * a -1 in it, but that is OK, it just means that we will have
2239          * to use the slow path instead).
2240          */
2241         blr     %r8,%r0
2242         nop
2243         bv      %r0(%r25)    /* r0 */
2244         copy    %r0,%r1
2245         bv      %r0(%r25)    /* r1 - shadowed */
2246         ldi     -1,%r1
2247         bv      %r0(%r25)    /* r2 */
2248         copy    %r2,%r1
2249         bv      %r0(%r25)    /* r3 */
2250         copy    %r3,%r1
2251         bv      %r0(%r25)    /* r4 */
2252         copy    %r4,%r1
2253         bv      %r0(%r25)    /* r5 */
2254         copy    %r5,%r1
2255         bv      %r0(%r25)    /* r6 */
2256         copy    %r6,%r1
2257         bv      %r0(%r25)    /* r7 */
2258         copy    %r7,%r1
2259         bv      %r0(%r25)    /* r8 - shadowed */
2260         ldi     -1,%r1
2261         bv      %r0(%r25)    /* r9 - shadowed */
2262         ldi     -1,%r1
2263         bv      %r0(%r25)    /* r10 */
2264         copy    %r10,%r1
2265         bv      %r0(%r25)    /* r11 */
2266         copy    %r11,%r1
2267         bv      %r0(%r25)    /* r12 */
2268         copy    %r12,%r1
2269         bv      %r0(%r25)    /* r13 */
2270         copy    %r13,%r1
2271         bv      %r0(%r25)    /* r14 */
2272         copy    %r14,%r1
2273         bv      %r0(%r25)    /* r15 */
2274         copy    %r15,%r1
2275         bv      %r0(%r25)    /* r16 - shadowed */
2276         ldi     -1,%r1
2277         bv      %r0(%r25)    /* r17 - shadowed */
2278         ldi     -1,%r1
2279         bv      %r0(%r25)    /* r18 */
2280         copy    %r18,%r1
2281         bv      %r0(%r25)    /* r19 */
2282         copy    %r19,%r1
2283         bv      %r0(%r25)    /* r20 */
2284         copy    %r20,%r1
2285         bv      %r0(%r25)    /* r21 */
2286         copy    %r21,%r1
2287         bv      %r0(%r25)    /* r22 */
2288         copy    %r22,%r1
2289         bv      %r0(%r25)    /* r23 */
2290         copy    %r23,%r1
2291         bv      %r0(%r25)    /* r24 - shadowed */
2292         ldi     -1,%r1
2293         bv      %r0(%r25)    /* r25 - shadowed */
2294         ldi     -1,%r1
2295         bv      %r0(%r25)    /* r26 */
2296         copy    %r26,%r1
2297         bv      %r0(%r25)    /* r27 */
2298         copy    %r27,%r1
2299         bv      %r0(%r25)    /* r28 */
2300         copy    %r28,%r1
2301         bv      %r0(%r25)    /* r29 */
2302         copy    %r29,%r1
2303         bv      %r0(%r25)    /* r30 */
2304         copy    %r30,%r1
2305         bv      %r0(%r25)    /* r31 */
2306         copy    %r31,%r1
2307
2308
2309 set_register:
2310         /*
2311          * set_register is used by the non access tlb miss handlers to
2312          * copy the value of r1 into the general register specified in
2313          * r8.
2314          */
2315         blr     %r8,%r0
2316         nop
2317         bv      %r0(%r25)    /* r0 (silly, but it is a place holder) */
2318         copy    %r1,%r0
2319         bv      %r0(%r25)    /* r1 */
2320         copy    %r1,%r1
2321         bv      %r0(%r25)    /* r2 */
2322         copy    %r1,%r2
2323         bv      %r0(%r25)    /* r3 */
2324         copy    %r1,%r3
2325         bv      %r0(%r25)    /* r4 */
2326         copy    %r1,%r4
2327         bv      %r0(%r25)    /* r5 */
2328         copy    %r1,%r5
2329         bv      %r0(%r25)    /* r6 */
2330         copy    %r1,%r6
2331         bv      %r0(%r25)    /* r7 */
2332         copy    %r1,%r7
2333         bv      %r0(%r25)    /* r8 */
2334         copy    %r1,%r8
2335         bv      %r0(%r25)    /* r9 */
2336         copy    %r1,%r9
2337         bv      %r0(%r25)    /* r10 */
2338         copy    %r1,%r10
2339         bv      %r0(%r25)    /* r11 */
2340         copy    %r1,%r11
2341         bv      %r0(%r25)    /* r12 */
2342         copy    %r1,%r12
2343         bv      %r0(%r25)    /* r13 */
2344         copy    %r1,%r13
2345         bv      %r0(%r25)    /* r14 */
2346         copy    %r1,%r14
2347         bv      %r0(%r25)    /* r15 */
2348         copy    %r1,%r15
2349         bv      %r0(%r25)    /* r16 */
2350         copy    %r1,%r16
2351         bv      %r0(%r25)    /* r17 */
2352         copy    %r1,%r17
2353         bv      %r0(%r25)    /* r18 */
2354         copy    %r1,%r18
2355         bv      %r0(%r25)    /* r19 */
2356         copy    %r1,%r19
2357         bv      %r0(%r25)    /* r20 */
2358         copy    %r1,%r20
2359         bv      %r0(%r25)    /* r21 */
2360         copy    %r1,%r21
2361         bv      %r0(%r25)    /* r22 */
2362         copy    %r1,%r22
2363         bv      %r0(%r25)    /* r23 */
2364         copy    %r1,%r23
2365         bv      %r0(%r25)    /* r24 */
2366         copy    %r1,%r24
2367         bv      %r0(%r25)    /* r25 */
2368         copy    %r1,%r25
2369         bv      %r0(%r25)    /* r26 */
2370         copy    %r1,%r26
2371         bv      %r0(%r25)    /* r27 */
2372         copy    %r1,%r27
2373         bv      %r0(%r25)    /* r28 */
2374         copy    %r1,%r28
2375         bv      %r0(%r25)    /* r29 */
2376         copy    %r1,%r29
2377         bv      %r0(%r25)    /* r30 */
2378         copy    %r1,%r30
2379         bv      %r0(%r25)    /* r31 */
2380         copy    %r1,%r31
2381