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parisc: fix partly 16/64k PAGE_SIZE boot
[deliverable/linux.git] / arch / parisc / kernel / entry.S
1 /*
2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
3 *
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <asm/asm-offsets.h>
26
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
30
31
32 #include <asm/psw.h>
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
38 #include <asm/thread_info.h>
39
40 #include <linux/linkage.h>
41
42 #ifdef CONFIG_64BIT
43 .level 2.0w
44 #else
45 .level 2.0
46 #endif
47
48 .import pa_dbit_lock,data
49
50 /* space_to_prot macro creates a prot id from a space id */
51
52 #if (SPACEID_SHIFT) == 0
53 .macro space_to_prot spc prot
54 depd,z \spc,62,31,\prot
55 .endm
56 #else
57 .macro space_to_prot spc prot
58 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
59 .endm
60 #endif
61
62 /* Switch to virtual mapping, trashing only %r1 */
63 .macro virt_map
64 /* pcxt_ssm_bug */
65 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
66 mtsp %r0, %sr4
67 mtsp %r0, %sr5
68 mfsp %sr7, %r1
69 or,= %r0,%r1,%r0 /* Only save sr7 in sr3 if sr7 != 0 */
70 mtsp %r1, %sr3
71 tovirt_r1 %r29
72 load32 KERNEL_PSW, %r1
73
74 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
75 mtsp %r0, %sr6
76 mtsp %r0, %sr7
77 mtctl %r0, %cr17 /* Clear IIASQ tail */
78 mtctl %r0, %cr17 /* Clear IIASQ head */
79 mtctl %r1, %ipsw
80 load32 4f, %r1
81 mtctl %r1, %cr18 /* Set IIAOQ tail */
82 ldo 4(%r1), %r1
83 mtctl %r1, %cr18 /* Set IIAOQ head */
84 rfir
85 nop
86 4:
87 .endm
88
89 /*
90 * The "get_stack" macros are responsible for determining the
91 * kernel stack value.
92 *
93 * If sr7 == 0
94 * Already using a kernel stack, so call the
95 * get_stack_use_r30 macro to push a pt_regs structure
96 * on the stack, and store registers there.
97 * else
98 * Need to set up a kernel stack, so call the
99 * get_stack_use_cr30 macro to set up a pointer
100 * to the pt_regs structure contained within the
101 * task pointer pointed to by cr30. Set the stack
102 * pointer to point to the end of the task structure.
103 *
104 * Note that we use shadowed registers for temps until
105 * we can save %r26 and %r29. %r26 is used to preserve
106 * %r8 (a shadowed register) which temporarily contained
107 * either the fault type ("code") or the eirr. We need
108 * to use a non-shadowed register to carry the value over
109 * the rfir in virt_map. We use %r26 since this value winds
110 * up being passed as the argument to either do_cpu_irq_mask
111 * or handle_interruption. %r29 is used to hold a pointer
112 * the register save area, and once again, it needs to
113 * be a non-shadowed register so that it survives the rfir.
114 *
115 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
116 */
117
118 .macro get_stack_use_cr30
119
120 /* we save the registers in the task struct */
121
122 mfctl %cr30, %r1
123 tophys %r1,%r9
124 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
125 tophys %r1,%r9
126 ldo TASK_REGS(%r9),%r9
127 STREG %r30, PT_GR30(%r9)
128 STREG %r29,PT_GR29(%r9)
129 STREG %r26,PT_GR26(%r9)
130 copy %r9,%r29
131 mfctl %cr30, %r1
132 ldo THREAD_SZ_ALGN(%r1), %r30
133 .endm
134
135 .macro get_stack_use_r30
136
137 /* we put a struct pt_regs on the stack and save the registers there */
138
139 tophys %r30,%r9
140 STREG %r30,PT_GR30(%r9)
141 ldo PT_SZ_ALGN(%r30),%r30
142 STREG %r29,PT_GR29(%r9)
143 STREG %r26,PT_GR26(%r9)
144 copy %r9,%r29
145 .endm
146
147 .macro rest_stack
148 LDREG PT_GR1(%r29), %r1
149 LDREG PT_GR30(%r29),%r30
150 LDREG PT_GR29(%r29),%r29
151 .endm
152
153 /* default interruption handler
154 * (calls traps.c:handle_interruption) */
155 .macro def code
156 b intr_save
157 ldi \code, %r8
158 .align 32
159 .endm
160
161 /* Interrupt interruption handler
162 * (calls irq.c:do_cpu_irq_mask) */
163 .macro extint code
164 b intr_extint
165 mfsp %sr7,%r16
166 .align 32
167 .endm
168
169 .import os_hpmc, code
170
171 /* HPMC handler */
172 .macro hpmc code
173 nop /* must be a NOP, will be patched later */
174 load32 PA(os_hpmc), %r3
175 bv,n 0(%r3)
176 nop
177 .word 0 /* checksum (will be patched) */
178 .word PA(os_hpmc) /* address of handler */
179 .word 0 /* length of handler */
180 .endm
181
182 /*
183 * Performance Note: Instructions will be moved up into
184 * this part of the code later on, once we are sure
185 * that the tlb miss handlers are close to final form.
186 */
187
188 /* Register definitions for tlb miss handler macros */
189
190 va = r8 /* virtual address for which the trap occurred */
191 spc = r24 /* space for which the trap occurred */
192
193 #ifndef CONFIG_64BIT
194
195 /*
196 * itlb miss interruption handler (parisc 1.1 - 32 bit)
197 */
198
199 .macro itlb_11 code
200
201 mfctl %pcsq, spc
202 b itlb_miss_11
203 mfctl %pcoq, va
204
205 .align 32
206 .endm
207 #endif
208
209 /*
210 * itlb miss interruption handler (parisc 2.0)
211 */
212
213 .macro itlb_20 code
214 mfctl %pcsq, spc
215 #ifdef CONFIG_64BIT
216 b itlb_miss_20w
217 #else
218 b itlb_miss_20
219 #endif
220 mfctl %pcoq, va
221
222 .align 32
223 .endm
224
225 #ifndef CONFIG_64BIT
226 /*
227 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
228 */
229
230 .macro naitlb_11 code
231
232 mfctl %isr,spc
233 b naitlb_miss_11
234 mfctl %ior,va
235
236 .align 32
237 .endm
238 #endif
239
240 /*
241 * naitlb miss interruption handler (parisc 2.0)
242 */
243
244 .macro naitlb_20 code
245
246 mfctl %isr,spc
247 #ifdef CONFIG_64BIT
248 b naitlb_miss_20w
249 #else
250 b naitlb_miss_20
251 #endif
252 mfctl %ior,va
253
254 .align 32
255 .endm
256
257 #ifndef CONFIG_64BIT
258 /*
259 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
260 */
261
262 .macro dtlb_11 code
263
264 mfctl %isr, spc
265 b dtlb_miss_11
266 mfctl %ior, va
267
268 .align 32
269 .endm
270 #endif
271
272 /*
273 * dtlb miss interruption handler (parisc 2.0)
274 */
275
276 .macro dtlb_20 code
277
278 mfctl %isr, spc
279 #ifdef CONFIG_64BIT
280 b dtlb_miss_20w
281 #else
282 b dtlb_miss_20
283 #endif
284 mfctl %ior, va
285
286 .align 32
287 .endm
288
289 #ifndef CONFIG_64BIT
290 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
291
292 .macro nadtlb_11 code
293
294 mfctl %isr,spc
295 b nadtlb_miss_11
296 mfctl %ior,va
297
298 .align 32
299 .endm
300 #endif
301
302 /* nadtlb miss interruption handler (parisc 2.0) */
303
304 .macro nadtlb_20 code
305
306 mfctl %isr,spc
307 #ifdef CONFIG_64BIT
308 b nadtlb_miss_20w
309 #else
310 b nadtlb_miss_20
311 #endif
312 mfctl %ior,va
313
314 .align 32
315 .endm
316
317 #ifndef CONFIG_64BIT
318 /*
319 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
320 */
321
322 .macro dbit_11 code
323
324 mfctl %isr,spc
325 b dbit_trap_11
326 mfctl %ior,va
327
328 .align 32
329 .endm
330 #endif
331
332 /*
333 * dirty bit trap interruption handler (parisc 2.0)
334 */
335
336 .macro dbit_20 code
337
338 mfctl %isr,spc
339 #ifdef CONFIG_64BIT
340 b dbit_trap_20w
341 #else
342 b dbit_trap_20
343 #endif
344 mfctl %ior,va
345
346 .align 32
347 .endm
348
349 /* In LP64, the space contains part of the upper 32 bits of the
350 * fault. We have to extract this and place it in the va,
351 * zeroing the corresponding bits in the space register */
352 .macro space_adjust spc,va,tmp
353 #ifdef CONFIG_64BIT
354 extrd,u \spc,63,SPACEID_SHIFT,\tmp
355 depd %r0,63,SPACEID_SHIFT,\spc
356 depd \tmp,31,SPACEID_SHIFT,\va
357 #endif
358 .endm
359
360 .import swapper_pg_dir,code
361
362 /* Get the pgd. For faults on space zero (kernel space), this
363 * is simply swapper_pg_dir. For user space faults, the
364 * pgd is stored in %cr25 */
365 .macro get_pgd spc,reg
366 ldil L%PA(swapper_pg_dir),\reg
367 ldo R%PA(swapper_pg_dir)(\reg),\reg
368 or,COND(=) %r0,\spc,%r0
369 mfctl %cr25,\reg
370 .endm
371
372 /*
373 space_check(spc,tmp,fault)
374
375 spc - The space we saw the fault with.
376 tmp - The place to store the current space.
377 fault - Function to call on failure.
378
379 Only allow faults on different spaces from the
380 currently active one if we're the kernel
381
382 */
383 .macro space_check spc,tmp,fault
384 mfsp %sr7,\tmp
385 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
386 * as kernel, so defeat the space
387 * check if it is */
388 copy \spc,\tmp
389 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
390 cmpb,COND(<>),n \tmp,\spc,\fault
391 .endm
392
393 /* Look up a PTE in a 2-Level scheme (faulting at each
394 * level if the entry isn't present
395 *
396 * NOTE: we use ldw even for LP64, since the short pointers
397 * can address up to 1TB
398 */
399 .macro L2_ptep pmd,pte,index,va,fault
400 #if PT_NLEVELS == 3
401 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
402 #else
403 # if defined(CONFIG_64BIT)
404 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
405 #else
406 # if PAGE_SIZE > 4096
407 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
408 # else
409 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
410 # endif
411 # endif
412 #endif
413 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
414 copy %r0,\pte
415 ldw,s \index(\pmd),\pmd
416 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
417 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
418 copy \pmd,%r9
419 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
420 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
421 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
422 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
423 LDREG %r0(\pmd),\pte /* pmd is now pte */
424 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
425 .endm
426
427 /* Look up PTE in a 3-Level scheme.
428 *
429 * Here we implement a Hybrid L2/L3 scheme: we allocate the
430 * first pmd adjacent to the pgd. This means that we can
431 * subtract a constant offset to get to it. The pmd and pgd
432 * sizes are arranged so that a single pmd covers 4GB (giving
433 * a full LP64 process access to 8TB) so our lookups are
434 * effectively L2 for the first 4GB of the kernel (i.e. for
435 * all ILP32 processes and all the kernel for machines with
436 * under 4GB of memory) */
437 .macro L3_ptep pgd,pte,index,va,fault
438 #if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
439 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
440 copy %r0,\pte
441 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
442 ldw,s \index(\pgd),\pgd
443 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
444 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
445 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
446 shld \pgd,PxD_VALUE_SHIFT,\index
447 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
448 copy \index,\pgd
449 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
450 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
451 #endif
452 L2_ptep \pgd,\pte,\index,\va,\fault
453 .endm
454
455 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
456 * don't needlessly dirty the cache line if it was already set */
457 .macro update_ptep ptep,pte,tmp,tmp1
458 ldi _PAGE_ACCESSED,\tmp1
459 or \tmp1,\pte,\tmp
460 and,COND(<>) \tmp1,\pte,%r0
461 STREG \tmp,0(\ptep)
462 .endm
463
464 /* Set the dirty bit (and accessed bit). No need to be
465 * clever, this is only used from the dirty fault */
466 .macro update_dirty ptep,pte,tmp
467 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
468 or \tmp,\pte,\pte
469 STREG \pte,0(\ptep)
470 .endm
471
472 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
473 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
474 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
475
476 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
477 .macro convert_for_tlb_insert20 pte
478 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
479 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
480 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
481 (63-58)+PAGE_ADD_SHIFT,\pte
482 .endm
483
484 /* Convert the pte and prot to tlb insertion values. How
485 * this happens is quite subtle, read below */
486 .macro make_insert_tlb spc,pte,prot
487 space_to_prot \spc \prot /* create prot id from space */
488 /* The following is the real subtlety. This is depositing
489 * T <-> _PAGE_REFTRAP
490 * D <-> _PAGE_DIRTY
491 * B <-> _PAGE_DMB (memory break)
492 *
493 * Then incredible subtlety: The access rights are
494 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
495 * See 3-14 of the parisc 2.0 manual
496 *
497 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
498 * trigger an access rights trap in user space if the user
499 * tries to read an unreadable page */
500 depd \pte,8,7,\prot
501
502 /* PAGE_USER indicates the page can be read with user privileges,
503 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
504 * contains _PAGE_READ) */
505 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
506 depdi 7,11,3,\prot
507 /* If we're a gateway page, drop PL2 back to zero for promotion
508 * to kernel privilege (so we can execute the page as kernel).
509 * Any privilege promotion page always denys read and write */
510 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
511 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
512
513 /* Enforce uncacheable pages.
514 * This should ONLY be use for MMIO on PA 2.0 machines.
515 * Memory/DMA is cache coherent on all PA2.0 machines we support
516 * (that means T-class is NOT supported) and the memory controllers
517 * on most of those machines only handles cache transactions.
518 */
519 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
520 depdi 1,12,1,\prot
521
522 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
523 convert_for_tlb_insert20 \pte
524 .endm
525
526 /* Identical macro to make_insert_tlb above, except it
527 * makes the tlb entry for the differently formatted pa11
528 * insertion instructions */
529 .macro make_insert_tlb_11 spc,pte,prot
530 zdep \spc,30,15,\prot
531 dep \pte,8,7,\prot
532 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
533 depi 1,12,1,\prot
534 extru,= \pte,_PAGE_USER_BIT,1,%r0
535 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
536 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
537 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
538
539 /* Get rid of prot bits and convert to page addr for iitlba */
540
541 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
542 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
543 .endm
544
545 /* This is for ILP32 PA2.0 only. The TLB insertion needs
546 * to extend into I/O space if the address is 0xfXXXXXXX
547 * so we extend the f's into the top word of the pte in
548 * this case */
549 .macro f_extend pte,tmp
550 extrd,s \pte,42,4,\tmp
551 addi,<> 1,\tmp,%r0
552 extrd,s \pte,63,25,\pte
553 .endm
554
555 /* The alias region is an 8MB aligned 16MB to do clear and
556 * copy user pages at addresses congruent with the user
557 * virtual address.
558 *
559 * To use the alias page, you set %r26 up with the to TLB
560 * entry (identifying the physical page) and %r23 up with
561 * the from tlb entry (or nothing if only a to entry---for
562 * clear_user_page_asm) */
563 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
564 cmpib,COND(<>),n 0,\spc,\fault
565 ldil L%(TMPALIAS_MAP_START),\tmp
566 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
567 /* on LP64, ldi will sign extend into the upper 32 bits,
568 * which is behaviour we don't want */
569 depdi 0,31,32,\tmp
570 #endif
571 copy \va,\tmp1
572 depi 0,31,23,\tmp1
573 cmpb,COND(<>),n \tmp,\tmp1,\fault
574 mfctl %cr19,\tmp /* iir */
575 /* get the opcode (first six bits) into \tmp */
576 extrw,u \tmp,5,6,\tmp
577 /*
578 * Only setting the T bit prevents data cache movein
579 * Setting access rights to zero prevents instruction cache movein
580 *
581 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
582 * to type field and _PAGE_READ goes to top bit of PL1
583 */
584 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
585 /*
586 * so if the opcode is one (i.e. this is a memory management
587 * instruction) nullify the next load so \prot is only T.
588 * Otherwise this is a normal data operation
589 */
590 cmpiclr,= 0x01,\tmp,%r0
591 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
592 .ifc \patype,20
593 depd,z \prot,8,7,\prot
594 .else
595 .ifc \patype,11
596 depw,z \prot,8,7,\prot
597 .else
598 .error "undefined PA type to do_alias"
599 .endif
600 .endif
601 /*
602 * OK, it is in the temp alias region, check whether "from" or "to".
603 * Check "subtle" note in pacache.S re: r23/r26.
604 */
605 #ifdef CONFIG_64BIT
606 extrd,u,*= \va,41,1,%r0
607 #else
608 extrw,u,= \va,9,1,%r0
609 #endif
610 or,COND(tr) %r23,%r0,\pte
611 or %r26,%r0,\pte
612 .endm
613
614
615 /*
616 * Align fault_vector_20 on 4K boundary so that both
617 * fault_vector_11 and fault_vector_20 are on the
618 * same page. This is only necessary as long as we
619 * write protect the kernel text, which we may stop
620 * doing once we use large page translations to cover
621 * the static part of the kernel address space.
622 */
623
624 .text
625
626 .align 4096
627
628 ENTRY(fault_vector_20)
629 /* First vector is invalid (0) */
630 .ascii "cows can fly"
631 .byte 0
632 .align 32
633
634 hpmc 1
635 def 2
636 def 3
637 extint 4
638 def 5
639 itlb_20 6
640 def 7
641 def 8
642 def 9
643 def 10
644 def 11
645 def 12
646 def 13
647 def 14
648 dtlb_20 15
649 naitlb_20 16
650 nadtlb_20 17
651 def 18
652 def 19
653 dbit_20 20
654 def 21
655 def 22
656 def 23
657 def 24
658 def 25
659 def 26
660 def 27
661 def 28
662 def 29
663 def 30
664 def 31
665 END(fault_vector_20)
666
667 #ifndef CONFIG_64BIT
668
669 .align 2048
670
671 ENTRY(fault_vector_11)
672 /* First vector is invalid (0) */
673 .ascii "cows can fly"
674 .byte 0
675 .align 32
676
677 hpmc 1
678 def 2
679 def 3
680 extint 4
681 def 5
682 itlb_11 6
683 def 7
684 def 8
685 def 9
686 def 10
687 def 11
688 def 12
689 def 13
690 def 14
691 dtlb_11 15
692 naitlb_11 16
693 nadtlb_11 17
694 def 18
695 def 19
696 dbit_11 20
697 def 21
698 def 22
699 def 23
700 def 24
701 def 25
702 def 26
703 def 27
704 def 28
705 def 29
706 def 30
707 def 31
708 END(fault_vector_11)
709
710 #endif
711 /* Fault vector is separately protected and *must* be on its own page */
712 .align PAGE_SIZE
713 ENTRY(end_fault_vector)
714
715 .import handle_interruption,code
716 .import do_cpu_irq_mask,code
717
718 /*
719 * Child Returns here
720 *
721 * copy_thread moved args into task save area.
722 */
723
724 ENTRY(ret_from_kernel_thread)
725
726 /* Call schedule_tail first though */
727 BL schedule_tail, %r2
728 nop
729
730 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
731 LDREG TASK_PT_GR25(%r1), %r26
732 #ifdef CONFIG_64BIT
733 LDREG TASK_PT_GR27(%r1), %r27
734 #endif
735 LDREG TASK_PT_GR26(%r1), %r1
736 ble 0(%sr7, %r1)
737 copy %r31, %r2
738 b finish_child_return
739 nop
740 ENDPROC(ret_from_kernel_thread)
741
742
743 /*
744 * struct task_struct *_switch_to(struct task_struct *prev,
745 * struct task_struct *next)
746 *
747 * switch kernel stacks and return prev */
748 ENTRY(_switch_to)
749 STREG %r2, -RP_OFFSET(%r30)
750
751 callee_save_float
752 callee_save
753
754 load32 _switch_to_ret, %r2
755
756 STREG %r2, TASK_PT_KPC(%r26)
757 LDREG TASK_PT_KPC(%r25), %r2
758
759 STREG %r30, TASK_PT_KSP(%r26)
760 LDREG TASK_PT_KSP(%r25), %r30
761 LDREG TASK_THREAD_INFO(%r25), %r25
762 bv %r0(%r2)
763 mtctl %r25,%cr30
764
765 _switch_to_ret:
766 mtctl %r0, %cr0 /* Needed for single stepping */
767 callee_rest
768 callee_rest_float
769
770 LDREG -RP_OFFSET(%r30), %r2
771 bv %r0(%r2)
772 copy %r26, %r28
773 ENDPROC(_switch_to)
774
775 /*
776 * Common rfi return path for interruptions, kernel execve, and
777 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
778 * return via this path if the signal was received when the process
779 * was running; if the process was blocked on a syscall then the
780 * normal syscall_exit path is used. All syscalls for traced
781 * proceses exit via intr_restore.
782 *
783 * XXX If any syscalls that change a processes space id ever exit
784 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
785 * adjust IASQ[0..1].
786 *
787 */
788
789 .align PAGE_SIZE
790
791 ENTRY(syscall_exit_rfi)
792 mfctl %cr30,%r16
793 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
794 ldo TASK_REGS(%r16),%r16
795 /* Force iaoq to userspace, as the user has had access to our current
796 * context via sigcontext. Also Filter the PSW for the same reason.
797 */
798 LDREG PT_IAOQ0(%r16),%r19
799 depi 3,31,2,%r19
800 STREG %r19,PT_IAOQ0(%r16)
801 LDREG PT_IAOQ1(%r16),%r19
802 depi 3,31,2,%r19
803 STREG %r19,PT_IAOQ1(%r16)
804 LDREG PT_PSW(%r16),%r19
805 load32 USER_PSW_MASK,%r1
806 #ifdef CONFIG_64BIT
807 load32 USER_PSW_HI_MASK,%r20
808 depd %r20,31,32,%r1
809 #endif
810 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
811 load32 USER_PSW,%r1
812 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
813 STREG %r19,PT_PSW(%r16)
814
815 /*
816 * If we aren't being traced, we never saved space registers
817 * (we don't store them in the sigcontext), so set them
818 * to "proper" values now (otherwise we'll wind up restoring
819 * whatever was last stored in the task structure, which might
820 * be inconsistent if an interrupt occurred while on the gateway
821 * page). Note that we may be "trashing" values the user put in
822 * them, but we don't support the user changing them.
823 */
824
825 STREG %r0,PT_SR2(%r16)
826 mfsp %sr3,%r19
827 STREG %r19,PT_SR0(%r16)
828 STREG %r19,PT_SR1(%r16)
829 STREG %r19,PT_SR3(%r16)
830 STREG %r19,PT_SR4(%r16)
831 STREG %r19,PT_SR5(%r16)
832 STREG %r19,PT_SR6(%r16)
833 STREG %r19,PT_SR7(%r16)
834
835 intr_return:
836 /* NOTE: Need to enable interrupts incase we schedule. */
837 ssm PSW_SM_I, %r0
838
839 intr_check_resched:
840
841 /* check for reschedule */
842 mfctl %cr30,%r1
843 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
844 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
845
846 .import do_notify_resume,code
847 intr_check_sig:
848 /* As above */
849 mfctl %cr30,%r1
850 LDREG TI_FLAGS(%r1),%r19
851 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
852 and,COND(<>) %r19, %r20, %r0
853 b,n intr_restore /* skip past if we've nothing to do */
854
855 /* This check is critical to having LWS
856 * working. The IASQ is zero on the gateway
857 * page and we cannot deliver any signals until
858 * we get off the gateway page.
859 *
860 * Only do signals if we are returning to user space
861 */
862 LDREG PT_IASQ0(%r16), %r20
863 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
864 LDREG PT_IASQ1(%r16), %r20
865 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
866
867 copy %r0, %r25 /* long in_syscall = 0 */
868 #ifdef CONFIG_64BIT
869 ldo -16(%r30),%r29 /* Reference param save area */
870 #endif
871
872 BL do_notify_resume,%r2
873 copy %r16, %r26 /* struct pt_regs *regs */
874
875 b,n intr_check_sig
876
877 intr_restore:
878 copy %r16,%r29
879 ldo PT_FR31(%r29),%r1
880 rest_fp %r1
881 rest_general %r29
882
883 /* inverse of virt_map */
884 pcxt_ssm_bug
885 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
886 tophys_r1 %r29
887
888 /* Restore space id's and special cr's from PT_REGS
889 * structure pointed to by r29
890 */
891 rest_specials %r29
892
893 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
894 * It also restores r1 and r30.
895 */
896 rest_stack
897
898 rfi
899 nop
900
901 #ifndef CONFIG_PREEMPT
902 # define intr_do_preempt intr_restore
903 #endif /* !CONFIG_PREEMPT */
904
905 .import schedule,code
906 intr_do_resched:
907 /* Only call schedule on return to userspace. If we're returning
908 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
909 * we jump back to intr_restore.
910 */
911 LDREG PT_IASQ0(%r16), %r20
912 cmpib,COND(=) 0, %r20, intr_do_preempt
913 nop
914 LDREG PT_IASQ1(%r16), %r20
915 cmpib,COND(=) 0, %r20, intr_do_preempt
916 nop
917
918 #ifdef CONFIG_64BIT
919 ldo -16(%r30),%r29 /* Reference param save area */
920 #endif
921
922 ldil L%intr_check_sig, %r2
923 #ifndef CONFIG_64BIT
924 b schedule
925 #else
926 load32 schedule, %r20
927 bv %r0(%r20)
928 #endif
929 ldo R%intr_check_sig(%r2), %r2
930
931 /* preempt the current task on returning to kernel
932 * mode from an interrupt, iff need_resched is set,
933 * and preempt_count is 0. otherwise, we continue on
934 * our merry way back to the current running task.
935 */
936 #ifdef CONFIG_PREEMPT
937 .import preempt_schedule_irq,code
938 intr_do_preempt:
939 rsm PSW_SM_I, %r0 /* disable interrupts */
940
941 /* current_thread_info()->preempt_count */
942 mfctl %cr30, %r1
943 LDREG TI_PRE_COUNT(%r1), %r19
944 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
945 nop /* prev insn branched backwards */
946
947 /* check if we interrupted a critical path */
948 LDREG PT_PSW(%r16), %r20
949 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
950 nop
951
952 BL preempt_schedule_irq, %r2
953 nop
954
955 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
956 #endif /* CONFIG_PREEMPT */
957
958 /*
959 * External interrupts.
960 */
961
962 intr_extint:
963 cmpib,COND(=),n 0,%r16,1f
964
965 get_stack_use_cr30
966 b,n 2f
967
968 1:
969 get_stack_use_r30
970 2:
971 save_specials %r29
972 virt_map
973 save_general %r29
974
975 ldo PT_FR0(%r29), %r24
976 save_fp %r24
977
978 loadgp
979
980 copy %r29, %r26 /* arg0 is pt_regs */
981 copy %r29, %r16 /* save pt_regs */
982
983 ldil L%intr_return, %r2
984
985 #ifdef CONFIG_64BIT
986 ldo -16(%r30),%r29 /* Reference param save area */
987 #endif
988
989 b do_cpu_irq_mask
990 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
991 ENDPROC(syscall_exit_rfi)
992
993
994 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
995
996 ENTRY(intr_save) /* for os_hpmc */
997 mfsp %sr7,%r16
998 cmpib,COND(=),n 0,%r16,1f
999 get_stack_use_cr30
1000 b 2f
1001 copy %r8,%r26
1002
1003 1:
1004 get_stack_use_r30
1005 copy %r8,%r26
1006
1007 2:
1008 save_specials %r29
1009
1010 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1011
1012 /*
1013 * FIXME: 1) Use a #define for the hardwired "6" below (and in
1014 * traps.c.
1015 * 2) Once we start executing code above 4 Gb, we need
1016 * to adjust iasq/iaoq here in the same way we
1017 * adjust isr/ior below.
1018 */
1019
1020 cmpib,COND(=),n 6,%r26,skip_save_ior
1021
1022
1023 mfctl %cr20, %r16 /* isr */
1024 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1025 mfctl %cr21, %r17 /* ior */
1026
1027
1028 #ifdef CONFIG_64BIT
1029 /*
1030 * If the interrupted code was running with W bit off (32 bit),
1031 * clear the b bits (bits 0 & 1) in the ior.
1032 * save_specials left ipsw value in r8 for us to test.
1033 */
1034 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1035 depdi 0,1,2,%r17
1036
1037 /*
1038 * FIXME: This code has hardwired assumptions about the split
1039 * between space bits and offset bits. This will change
1040 * when we allow alternate page sizes.
1041 */
1042
1043 /* adjust isr/ior. */
1044 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1045 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1046 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1047 #endif
1048 STREG %r16, PT_ISR(%r29)
1049 STREG %r17, PT_IOR(%r29)
1050
1051
1052 skip_save_ior:
1053 virt_map
1054 save_general %r29
1055
1056 ldo PT_FR0(%r29), %r25
1057 save_fp %r25
1058
1059 loadgp
1060
1061 copy %r29, %r25 /* arg1 is pt_regs */
1062 #ifdef CONFIG_64BIT
1063 ldo -16(%r30),%r29 /* Reference param save area */
1064 #endif
1065
1066 ldil L%intr_check_sig, %r2
1067 copy %r25, %r16 /* save pt_regs */
1068
1069 b handle_interruption
1070 ldo R%intr_check_sig(%r2), %r2
1071 ENDPROC(intr_save)
1072
1073
1074 /*
1075 * Note for all tlb miss handlers:
1076 *
1077 * cr24 contains a pointer to the kernel address space
1078 * page directory.
1079 *
1080 * cr25 contains a pointer to the current user address
1081 * space page directory.
1082 *
1083 * sr3 will contain the space id of the user address space
1084 * of the current running thread while that thread is
1085 * running in the kernel.
1086 */
1087
1088 /*
1089 * register number allocations. Note that these are all
1090 * in the shadowed registers
1091 */
1092
1093 t0 = r1 /* temporary register 0 */
1094 va = r8 /* virtual address for which the trap occurred */
1095 t1 = r9 /* temporary register 1 */
1096 pte = r16 /* pte/phys page # */
1097 prot = r17 /* prot bits */
1098 spc = r24 /* space for which the trap occurred */
1099 ptp = r25 /* page directory/page table pointer */
1100
1101 #ifdef CONFIG_64BIT
1102
1103 dtlb_miss_20w:
1104 space_adjust spc,va,t0
1105 get_pgd spc,ptp
1106 space_check spc,t0,dtlb_fault
1107
1108 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1109
1110 update_ptep ptp,pte,t0,t1
1111
1112 make_insert_tlb spc,pte,prot
1113
1114 idtlbt pte,prot
1115
1116 rfir
1117 nop
1118
1119 dtlb_check_alias_20w:
1120 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1121
1122 idtlbt pte,prot
1123
1124 rfir
1125 nop
1126
1127 nadtlb_miss_20w:
1128 space_adjust spc,va,t0
1129 get_pgd spc,ptp
1130 space_check spc,t0,nadtlb_fault
1131
1132 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1133
1134 update_ptep ptp,pte,t0,t1
1135
1136 make_insert_tlb spc,pte,prot
1137
1138 idtlbt pte,prot
1139
1140 rfir
1141 nop
1142
1143 nadtlb_check_alias_20w:
1144 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1145
1146 idtlbt pte,prot
1147
1148 rfir
1149 nop
1150
1151 #else
1152
1153 dtlb_miss_11:
1154 get_pgd spc,ptp
1155
1156 space_check spc,t0,dtlb_fault
1157
1158 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1159
1160 update_ptep ptp,pte,t0,t1
1161
1162 make_insert_tlb_11 spc,pte,prot
1163
1164 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1165 mtsp spc,%sr1
1166
1167 idtlba pte,(%sr1,va)
1168 idtlbp prot,(%sr1,va)
1169
1170 mtsp t0, %sr1 /* Restore sr1 */
1171
1172 rfir
1173 nop
1174
1175 dtlb_check_alias_11:
1176 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1177
1178 idtlba pte,(va)
1179 idtlbp prot,(va)
1180
1181 rfir
1182 nop
1183
1184 nadtlb_miss_11:
1185 get_pgd spc,ptp
1186
1187 space_check spc,t0,nadtlb_fault
1188
1189 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1190
1191 update_ptep ptp,pte,t0,t1
1192
1193 make_insert_tlb_11 spc,pte,prot
1194
1195
1196 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1197 mtsp spc,%sr1
1198
1199 idtlba pte,(%sr1,va)
1200 idtlbp prot,(%sr1,va)
1201
1202 mtsp t0, %sr1 /* Restore sr1 */
1203
1204 rfir
1205 nop
1206
1207 nadtlb_check_alias_11:
1208 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1209
1210 idtlba pte,(va)
1211 idtlbp prot,(va)
1212
1213 rfir
1214 nop
1215
1216 dtlb_miss_20:
1217 space_adjust spc,va,t0
1218 get_pgd spc,ptp
1219 space_check spc,t0,dtlb_fault
1220
1221 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1222
1223 update_ptep ptp,pte,t0,t1
1224
1225 make_insert_tlb spc,pte,prot
1226
1227 f_extend pte,t0
1228
1229 idtlbt pte,prot
1230
1231 rfir
1232 nop
1233
1234 dtlb_check_alias_20:
1235 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1236
1237 idtlbt pte,prot
1238
1239 rfir
1240 nop
1241
1242 nadtlb_miss_20:
1243 get_pgd spc,ptp
1244
1245 space_check spc,t0,nadtlb_fault
1246
1247 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1248
1249 update_ptep ptp,pte,t0,t1
1250
1251 make_insert_tlb spc,pte,prot
1252
1253 f_extend pte,t0
1254
1255 idtlbt pte,prot
1256
1257 rfir
1258 nop
1259
1260 nadtlb_check_alias_20:
1261 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1262
1263 idtlbt pte,prot
1264
1265 rfir
1266 nop
1267
1268 #endif
1269
1270 nadtlb_emulate:
1271
1272 /*
1273 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1274 * probei instructions. We don't want to fault for these
1275 * instructions (not only does it not make sense, it can cause
1276 * deadlocks, since some flushes are done with the mmap
1277 * semaphore held). If the translation doesn't exist, we can't
1278 * insert a translation, so have to emulate the side effects
1279 * of the instruction. Since we don't insert a translation
1280 * we can get a lot of faults during a flush loop, so it makes
1281 * sense to try to do it here with minimum overhead. We only
1282 * emulate fdc,fic,pdc,probew,prober instructions whose base
1283 * and index registers are not shadowed. We defer everything
1284 * else to the "slow" path.
1285 */
1286
1287 mfctl %cr19,%r9 /* Get iir */
1288
1289 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1290 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1291
1292 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1293 ldi 0x280,%r16
1294 and %r9,%r16,%r17
1295 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1296 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1297 BL get_register,%r25
1298 extrw,u %r9,15,5,%r8 /* Get index register # */
1299 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1300 copy %r1,%r24
1301 BL get_register,%r25
1302 extrw,u %r9,10,5,%r8 /* Get base register # */
1303 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1304 BL set_register,%r25
1305 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1306
1307 nadtlb_nullify:
1308 mfctl %ipsw,%r8
1309 ldil L%PSW_N,%r9
1310 or %r8,%r9,%r8 /* Set PSW_N */
1311 mtctl %r8,%ipsw
1312
1313 rfir
1314 nop
1315
1316 /*
1317 When there is no translation for the probe address then we
1318 must nullify the insn and return zero in the target regsiter.
1319 This will indicate to the calling code that it does not have
1320 write/read privileges to this address.
1321
1322 This should technically work for prober and probew in PA 1.1,
1323 and also probe,r and probe,w in PA 2.0
1324
1325 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1326 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1327
1328 */
1329 nadtlb_probe_check:
1330 ldi 0x80,%r16
1331 and %r9,%r16,%r17
1332 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1333 BL get_register,%r25 /* Find the target register */
1334 extrw,u %r9,31,5,%r8 /* Get target register */
1335 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1336 BL set_register,%r25
1337 copy %r0,%r1 /* Write zero to target register */
1338 b nadtlb_nullify /* Nullify return insn */
1339 nop
1340
1341
1342 #ifdef CONFIG_64BIT
1343 itlb_miss_20w:
1344
1345 /*
1346 * I miss is a little different, since we allow users to fault
1347 * on the gateway page which is in the kernel address space.
1348 */
1349
1350 space_adjust spc,va,t0
1351 get_pgd spc,ptp
1352 space_check spc,t0,itlb_fault
1353
1354 L3_ptep ptp,pte,t0,va,itlb_fault
1355
1356 update_ptep ptp,pte,t0,t1
1357
1358 make_insert_tlb spc,pte,prot
1359
1360 iitlbt pte,prot
1361
1362 rfir
1363 nop
1364
1365 naitlb_miss_20w:
1366
1367 /*
1368 * I miss is a little different, since we allow users to fault
1369 * on the gateway page which is in the kernel address space.
1370 */
1371
1372 space_adjust spc,va,t0
1373 get_pgd spc,ptp
1374 space_check spc,t0,naitlb_fault
1375
1376 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1377
1378 update_ptep ptp,pte,t0,t1
1379
1380 make_insert_tlb spc,pte,prot
1381
1382 iitlbt pte,prot
1383
1384 rfir
1385 nop
1386
1387 naitlb_check_alias_20w:
1388 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1389
1390 iitlbt pte,prot
1391
1392 rfir
1393 nop
1394
1395 #else
1396
1397 itlb_miss_11:
1398 get_pgd spc,ptp
1399
1400 space_check spc,t0,itlb_fault
1401
1402 L2_ptep ptp,pte,t0,va,itlb_fault
1403
1404 update_ptep ptp,pte,t0,t1
1405
1406 make_insert_tlb_11 spc,pte,prot
1407
1408 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1409 mtsp spc,%sr1
1410
1411 iitlba pte,(%sr1,va)
1412 iitlbp prot,(%sr1,va)
1413
1414 mtsp t0, %sr1 /* Restore sr1 */
1415
1416 rfir
1417 nop
1418
1419 naitlb_miss_11:
1420 get_pgd spc,ptp
1421
1422 space_check spc,t0,naitlb_fault
1423
1424 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1425
1426 update_ptep ptp,pte,t0,t1
1427
1428 make_insert_tlb_11 spc,pte,prot
1429
1430 mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
1431 mtsp spc,%sr1
1432
1433 iitlba pte,(%sr1,va)
1434 iitlbp prot,(%sr1,va)
1435
1436 mtsp t0, %sr1 /* Restore sr1 */
1437
1438 rfir
1439 nop
1440
1441 naitlb_check_alias_11:
1442 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1443
1444 iitlba pte,(%sr0, va)
1445 iitlbp prot,(%sr0, va)
1446
1447 rfir
1448 nop
1449
1450
1451 itlb_miss_20:
1452 get_pgd spc,ptp
1453
1454 space_check spc,t0,itlb_fault
1455
1456 L2_ptep ptp,pte,t0,va,itlb_fault
1457
1458 update_ptep ptp,pte,t0,t1
1459
1460 make_insert_tlb spc,pte,prot
1461
1462 f_extend pte,t0
1463
1464 iitlbt pte,prot
1465
1466 rfir
1467 nop
1468
1469 naitlb_miss_20:
1470 get_pgd spc,ptp
1471
1472 space_check spc,t0,naitlb_fault
1473
1474 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1475
1476 update_ptep ptp,pte,t0,t1
1477
1478 make_insert_tlb spc,pte,prot
1479
1480 f_extend pte,t0
1481
1482 iitlbt pte,prot
1483
1484 rfir
1485 nop
1486
1487 naitlb_check_alias_20:
1488 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1489
1490 iitlbt pte,prot
1491
1492 rfir
1493 nop
1494
1495 #endif
1496
1497 #ifdef CONFIG_64BIT
1498
1499 dbit_trap_20w:
1500 space_adjust spc,va,t0
1501 get_pgd spc,ptp
1502 space_check spc,t0,dbit_fault
1503
1504 L3_ptep ptp,pte,t0,va,dbit_fault
1505
1506 #ifdef CONFIG_SMP
1507 cmpib,COND(=),n 0,spc,dbit_nolock_20w
1508 load32 PA(pa_dbit_lock),t0
1509
1510 dbit_spin_20w:
1511 LDCW 0(t0),t1
1512 cmpib,COND(=) 0,t1,dbit_spin_20w
1513 nop
1514
1515 dbit_nolock_20w:
1516 #endif
1517 update_dirty ptp,pte,t1
1518
1519 make_insert_tlb spc,pte,prot
1520
1521 idtlbt pte,prot
1522 #ifdef CONFIG_SMP
1523 cmpib,COND(=),n 0,spc,dbit_nounlock_20w
1524 ldi 1,t1
1525 stw t1,0(t0)
1526
1527 dbit_nounlock_20w:
1528 #endif
1529
1530 rfir
1531 nop
1532 #else
1533
1534 dbit_trap_11:
1535
1536 get_pgd spc,ptp
1537
1538 space_check spc,t0,dbit_fault
1539
1540 L2_ptep ptp,pte,t0,va,dbit_fault
1541
1542 #ifdef CONFIG_SMP
1543 cmpib,COND(=),n 0,spc,dbit_nolock_11
1544 load32 PA(pa_dbit_lock),t0
1545
1546 dbit_spin_11:
1547 LDCW 0(t0),t1
1548 cmpib,= 0,t1,dbit_spin_11
1549 nop
1550
1551 dbit_nolock_11:
1552 #endif
1553 update_dirty ptp,pte,t1
1554
1555 make_insert_tlb_11 spc,pte,prot
1556
1557 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1558 mtsp spc,%sr1
1559
1560 idtlba pte,(%sr1,va)
1561 idtlbp prot,(%sr1,va)
1562
1563 mtsp t1, %sr1 /* Restore sr1 */
1564 #ifdef CONFIG_SMP
1565 cmpib,COND(=),n 0,spc,dbit_nounlock_11
1566 ldi 1,t1
1567 stw t1,0(t0)
1568
1569 dbit_nounlock_11:
1570 #endif
1571
1572 rfir
1573 nop
1574
1575 dbit_trap_20:
1576 get_pgd spc,ptp
1577
1578 space_check spc,t0,dbit_fault
1579
1580 L2_ptep ptp,pte,t0,va,dbit_fault
1581
1582 #ifdef CONFIG_SMP
1583 cmpib,COND(=),n 0,spc,dbit_nolock_20
1584 load32 PA(pa_dbit_lock),t0
1585
1586 dbit_spin_20:
1587 LDCW 0(t0),t1
1588 cmpib,= 0,t1,dbit_spin_20
1589 nop
1590
1591 dbit_nolock_20:
1592 #endif
1593 update_dirty ptp,pte,t1
1594
1595 make_insert_tlb spc,pte,prot
1596
1597 f_extend pte,t1
1598
1599 idtlbt pte,prot
1600
1601 #ifdef CONFIG_SMP
1602 cmpib,COND(=),n 0,spc,dbit_nounlock_20
1603 ldi 1,t1
1604 stw t1,0(t0)
1605
1606 dbit_nounlock_20:
1607 #endif
1608
1609 rfir
1610 nop
1611 #endif
1612
1613 .import handle_interruption,code
1614
1615 kernel_bad_space:
1616 b intr_save
1617 ldi 31,%r8 /* Use an unused code */
1618
1619 dbit_fault:
1620 b intr_save
1621 ldi 20,%r8
1622
1623 itlb_fault:
1624 b intr_save
1625 ldi 6,%r8
1626
1627 nadtlb_fault:
1628 b intr_save
1629 ldi 17,%r8
1630
1631 naitlb_fault:
1632 b intr_save
1633 ldi 16,%r8
1634
1635 dtlb_fault:
1636 b intr_save
1637 ldi 15,%r8
1638
1639 /* Register saving semantics for system calls:
1640
1641 %r1 clobbered by system call macro in userspace
1642 %r2 saved in PT_REGS by gateway page
1643 %r3 - %r18 preserved by C code (saved by signal code)
1644 %r19 - %r20 saved in PT_REGS by gateway page
1645 %r21 - %r22 non-standard syscall args
1646 stored in kernel stack by gateway page
1647 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1648 %r27 - %r30 saved in PT_REGS by gateway page
1649 %r31 syscall return pointer
1650 */
1651
1652 /* Floating point registers (FIXME: what do we do with these?)
1653
1654 %fr0 - %fr3 status/exception, not preserved
1655 %fr4 - %fr7 arguments
1656 %fr8 - %fr11 not preserved by C code
1657 %fr12 - %fr21 preserved by C code
1658 %fr22 - %fr31 not preserved by C code
1659 */
1660
1661 .macro reg_save regs
1662 STREG %r3, PT_GR3(\regs)
1663 STREG %r4, PT_GR4(\regs)
1664 STREG %r5, PT_GR5(\regs)
1665 STREG %r6, PT_GR6(\regs)
1666 STREG %r7, PT_GR7(\regs)
1667 STREG %r8, PT_GR8(\regs)
1668 STREG %r9, PT_GR9(\regs)
1669 STREG %r10,PT_GR10(\regs)
1670 STREG %r11,PT_GR11(\regs)
1671 STREG %r12,PT_GR12(\regs)
1672 STREG %r13,PT_GR13(\regs)
1673 STREG %r14,PT_GR14(\regs)
1674 STREG %r15,PT_GR15(\regs)
1675 STREG %r16,PT_GR16(\regs)
1676 STREG %r17,PT_GR17(\regs)
1677 STREG %r18,PT_GR18(\regs)
1678 .endm
1679
1680 .macro reg_restore regs
1681 LDREG PT_GR3(\regs), %r3
1682 LDREG PT_GR4(\regs), %r4
1683 LDREG PT_GR5(\regs), %r5
1684 LDREG PT_GR6(\regs), %r6
1685 LDREG PT_GR7(\regs), %r7
1686 LDREG PT_GR8(\regs), %r8
1687 LDREG PT_GR9(\regs), %r9
1688 LDREG PT_GR10(\regs),%r10
1689 LDREG PT_GR11(\regs),%r11
1690 LDREG PT_GR12(\regs),%r12
1691 LDREG PT_GR13(\regs),%r13
1692 LDREG PT_GR14(\regs),%r14
1693 LDREG PT_GR15(\regs),%r15
1694 LDREG PT_GR16(\regs),%r16
1695 LDREG PT_GR17(\regs),%r17
1696 LDREG PT_GR18(\regs),%r18
1697 .endm
1698
1699 .macro fork_like name
1700 ENTRY(sys_\name\()_wrapper)
1701 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1702 ldo TASK_REGS(%r1),%r1
1703 reg_save %r1
1704 mfctl %cr27, %r28
1705 b sys_\name
1706 STREG %r28, PT_CR27(%r1)
1707 ENDPROC(sys_\name\()_wrapper)
1708 .endm
1709
1710 fork_like clone
1711 fork_like fork
1712 fork_like vfork
1713
1714 /* Set the return value for the child */
1715 ENTRY(child_return)
1716 BL schedule_tail, %r2
1717 nop
1718 finish_child_return:
1719 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1720 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1721
1722 LDREG PT_CR27(%r1), %r3
1723 mtctl %r3, %cr27
1724 reg_restore %r1
1725 b syscall_exit
1726 copy %r0,%r28
1727 ENDPROC(child_return)
1728
1729 ENTRY(sys_rt_sigreturn_wrapper)
1730 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1731 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1732 /* Don't save regs, we are going to restore them from sigcontext. */
1733 STREG %r2, -RP_OFFSET(%r30)
1734 #ifdef CONFIG_64BIT
1735 ldo FRAME_SIZE(%r30), %r30
1736 BL sys_rt_sigreturn,%r2
1737 ldo -16(%r30),%r29 /* Reference param save area */
1738 #else
1739 BL sys_rt_sigreturn,%r2
1740 ldo FRAME_SIZE(%r30), %r30
1741 #endif
1742
1743 ldo -FRAME_SIZE(%r30), %r30
1744 LDREG -RP_OFFSET(%r30), %r2
1745
1746 /* FIXME: I think we need to restore a few more things here. */
1747 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1748 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1749 reg_restore %r1
1750
1751 /* If the signal was received while the process was blocked on a
1752 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1753 * take us to syscall_exit_rfi and on to intr_return.
1754 */
1755 bv %r0(%r2)
1756 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1757 ENDPROC(sys_rt_sigreturn_wrapper)
1758
1759 ENTRY(syscall_exit)
1760 /* NOTE: HP-UX syscalls also come through here
1761 * after hpux_syscall_exit fixes up return
1762 * values. */
1763
1764 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1765 * via syscall_exit_rfi if the signal was received while the process
1766 * was running.
1767 */
1768
1769 /* save return value now */
1770
1771 mfctl %cr30, %r1
1772 LDREG TI_TASK(%r1),%r1
1773 STREG %r28,TASK_PT_GR28(%r1)
1774
1775 #ifdef CONFIG_HPUX
1776 /* <linux/personality.h> cannot be easily included */
1777 #define PER_HPUX 0x10
1778 ldw TASK_PERSONALITY(%r1),%r19
1779
1780 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1781 ldo -PER_HPUX(%r19), %r19
1782 cmpib,COND(<>),n 0,%r19,1f
1783
1784 /* Save other hpux returns if personality is PER_HPUX */
1785 STREG %r22,TASK_PT_GR22(%r1)
1786 STREG %r29,TASK_PT_GR29(%r1)
1787 1:
1788
1789 #endif /* CONFIG_HPUX */
1790
1791 /* Seems to me that dp could be wrong here, if the syscall involved
1792 * calling a module, and nothing got round to restoring dp on return.
1793 */
1794 loadgp
1795
1796 syscall_check_resched:
1797
1798 /* check for reschedule */
1799
1800 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1801 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1802
1803 .import do_signal,code
1804 syscall_check_sig:
1805 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1806 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1807 and,COND(<>) %r19, %r26, %r0
1808 b,n syscall_restore /* skip past if we've nothing to do */
1809
1810 syscall_do_signal:
1811 /* Save callee-save registers (for sigcontext).
1812 * FIXME: After this point the process structure should be
1813 * consistent with all the relevant state of the process
1814 * before the syscall. We need to verify this.
1815 */
1816 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1817 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1818 reg_save %r26
1819
1820 #ifdef CONFIG_64BIT
1821 ldo -16(%r30),%r29 /* Reference param save area */
1822 #endif
1823
1824 BL do_notify_resume,%r2
1825 ldi 1, %r25 /* long in_syscall = 1 */
1826
1827 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1828 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1829 reg_restore %r20
1830
1831 b,n syscall_check_sig
1832
1833 syscall_restore:
1834 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1835
1836 /* Are we being ptraced? */
1837 ldw TASK_FLAGS(%r1),%r19
1838 ldi _TIF_SYSCALL_TRACE_MASK,%r2
1839 and,COND(=) %r19,%r2,%r0
1840 b,n syscall_restore_rfi
1841
1842 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1843 rest_fp %r19
1844
1845 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1846 mtsar %r19
1847
1848 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1849 LDREG TASK_PT_GR19(%r1),%r19
1850 LDREG TASK_PT_GR20(%r1),%r20
1851 LDREG TASK_PT_GR21(%r1),%r21
1852 LDREG TASK_PT_GR22(%r1),%r22
1853 LDREG TASK_PT_GR23(%r1),%r23
1854 LDREG TASK_PT_GR24(%r1),%r24
1855 LDREG TASK_PT_GR25(%r1),%r25
1856 LDREG TASK_PT_GR26(%r1),%r26
1857 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1858 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1859 LDREG TASK_PT_GR29(%r1),%r29
1860 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1861
1862 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1863 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1864 rsm PSW_SM_I, %r0
1865 copy %r1,%r30 /* Restore user sp */
1866 mfsp %sr3,%r1 /* Get user space id */
1867 mtsp %r1,%sr7 /* Restore sr7 */
1868 ssm PSW_SM_I, %r0
1869
1870 /* Set sr2 to zero for userspace syscalls to work. */
1871 mtsp %r0,%sr2
1872 mtsp %r1,%sr4 /* Restore sr4 */
1873 mtsp %r1,%sr5 /* Restore sr5 */
1874 mtsp %r1,%sr6 /* Restore sr6 */
1875
1876 depi 3,31,2,%r31 /* ensure return to user mode. */
1877
1878 #ifdef CONFIG_64BIT
1879 /* decide whether to reset the wide mode bit
1880 *
1881 * For a syscall, the W bit is stored in the lowest bit
1882 * of sp. Extract it and reset W if it is zero */
1883 extrd,u,*<> %r30,63,1,%r1
1884 rsm PSW_SM_W, %r0
1885 /* now reset the lowest bit of sp if it was set */
1886 xor %r30,%r1,%r30
1887 #endif
1888 be,n 0(%sr3,%r31) /* return to user space */
1889
1890 /* We have to return via an RFI, so that PSW T and R bits can be set
1891 * appropriately.
1892 * This sets up pt_regs so we can return via intr_restore, which is not
1893 * the most efficient way of doing things, but it works.
1894 */
1895 syscall_restore_rfi:
1896 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1897 mtctl %r2,%cr0 /* for immediate trap */
1898 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1899 ldi 0x0b,%r20 /* Create new PSW */
1900 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1901
1902 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1903 * set in thread_info.h and converted to PA bitmap
1904 * numbers in asm-offsets.c */
1905
1906 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1907 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1908 depi -1,27,1,%r20 /* R bit */
1909
1910 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1911 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1912 depi -1,7,1,%r20 /* T bit */
1913
1914 STREG %r20,TASK_PT_PSW(%r1)
1915
1916 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1917
1918 mfsp %sr3,%r25
1919 STREG %r25,TASK_PT_SR3(%r1)
1920 STREG %r25,TASK_PT_SR4(%r1)
1921 STREG %r25,TASK_PT_SR5(%r1)
1922 STREG %r25,TASK_PT_SR6(%r1)
1923 STREG %r25,TASK_PT_SR7(%r1)
1924 STREG %r25,TASK_PT_IASQ0(%r1)
1925 STREG %r25,TASK_PT_IASQ1(%r1)
1926
1927 /* XXX W bit??? */
1928 /* Now if old D bit is clear, it means we didn't save all registers
1929 * on syscall entry, so do that now. This only happens on TRACEME
1930 * calls, or if someone attached to us while we were on a syscall.
1931 * We could make this more efficient by not saving r3-r18, but
1932 * then we wouldn't be able to use the common intr_restore path.
1933 * It is only for traced processes anyway, so performance is not
1934 * an issue.
1935 */
1936 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1937 ldo TASK_REGS(%r1),%r25
1938 reg_save %r25 /* Save r3 to r18 */
1939
1940 /* Save the current sr */
1941 mfsp %sr0,%r2
1942 STREG %r2,TASK_PT_SR0(%r1)
1943
1944 /* Save the scratch sr */
1945 mfsp %sr1,%r2
1946 STREG %r2,TASK_PT_SR1(%r1)
1947
1948 /* sr2 should be set to zero for userspace syscalls */
1949 STREG %r0,TASK_PT_SR2(%r1)
1950
1951 LDREG TASK_PT_GR31(%r1),%r2
1952 depi 3,31,2,%r2 /* ensure return to user mode. */
1953 STREG %r2,TASK_PT_IAOQ0(%r1)
1954 ldo 4(%r2),%r2
1955 STREG %r2,TASK_PT_IAOQ1(%r1)
1956 b intr_restore
1957 copy %r25,%r16
1958
1959 pt_regs_ok:
1960 LDREG TASK_PT_IAOQ0(%r1),%r2
1961 depi 3,31,2,%r2 /* ensure return to user mode. */
1962 STREG %r2,TASK_PT_IAOQ0(%r1)
1963 LDREG TASK_PT_IAOQ1(%r1),%r2
1964 depi 3,31,2,%r2
1965 STREG %r2,TASK_PT_IAOQ1(%r1)
1966 b intr_restore
1967 copy %r25,%r16
1968
1969 .import schedule,code
1970 syscall_do_resched:
1971 BL schedule,%r2
1972 #ifdef CONFIG_64BIT
1973 ldo -16(%r30),%r29 /* Reference param save area */
1974 #else
1975 nop
1976 #endif
1977 b syscall_check_resched /* if resched, we start over again */
1978 nop
1979 ENDPROC(syscall_exit)
1980
1981
1982 #ifdef CONFIG_FUNCTION_TRACER
1983 .import ftrace_function_trampoline,code
1984 ENTRY(_mcount)
1985 copy %r3, %arg2
1986 b ftrace_function_trampoline
1987 nop
1988 ENDPROC(_mcount)
1989
1990 ENTRY(return_to_handler)
1991 load32 return_trampoline, %rp
1992 copy %ret0, %arg0
1993 copy %ret1, %arg1
1994 b ftrace_return_to_handler
1995 nop
1996 return_trampoline:
1997 copy %ret0, %rp
1998 copy %r23, %ret0
1999 copy %r24, %ret1
2000
2001 .globl ftrace_stub
2002 ftrace_stub:
2003 bv %r0(%rp)
2004 nop
2005 ENDPROC(return_to_handler)
2006 #endif /* CONFIG_FUNCTION_TRACER */
2007
2008
2009 get_register:
2010 /*
2011 * get_register is used by the non access tlb miss handlers to
2012 * copy the value of the general register specified in r8 into
2013 * r1. This routine can't be used for shadowed registers, since
2014 * the rfir will restore the original value. So, for the shadowed
2015 * registers we put a -1 into r1 to indicate that the register
2016 * should not be used (the register being copied could also have
2017 * a -1 in it, but that is OK, it just means that we will have
2018 * to use the slow path instead).
2019 */
2020 blr %r8,%r0
2021 nop
2022 bv %r0(%r25) /* r0 */
2023 copy %r0,%r1
2024 bv %r0(%r25) /* r1 - shadowed */
2025 ldi -1,%r1
2026 bv %r0(%r25) /* r2 */
2027 copy %r2,%r1
2028 bv %r0(%r25) /* r3 */
2029 copy %r3,%r1
2030 bv %r0(%r25) /* r4 */
2031 copy %r4,%r1
2032 bv %r0(%r25) /* r5 */
2033 copy %r5,%r1
2034 bv %r0(%r25) /* r6 */
2035 copy %r6,%r1
2036 bv %r0(%r25) /* r7 */
2037 copy %r7,%r1
2038 bv %r0(%r25) /* r8 - shadowed */
2039 ldi -1,%r1
2040 bv %r0(%r25) /* r9 - shadowed */
2041 ldi -1,%r1
2042 bv %r0(%r25) /* r10 */
2043 copy %r10,%r1
2044 bv %r0(%r25) /* r11 */
2045 copy %r11,%r1
2046 bv %r0(%r25) /* r12 */
2047 copy %r12,%r1
2048 bv %r0(%r25) /* r13 */
2049 copy %r13,%r1
2050 bv %r0(%r25) /* r14 */
2051 copy %r14,%r1
2052 bv %r0(%r25) /* r15 */
2053 copy %r15,%r1
2054 bv %r0(%r25) /* r16 - shadowed */
2055 ldi -1,%r1
2056 bv %r0(%r25) /* r17 - shadowed */
2057 ldi -1,%r1
2058 bv %r0(%r25) /* r18 */
2059 copy %r18,%r1
2060 bv %r0(%r25) /* r19 */
2061 copy %r19,%r1
2062 bv %r0(%r25) /* r20 */
2063 copy %r20,%r1
2064 bv %r0(%r25) /* r21 */
2065 copy %r21,%r1
2066 bv %r0(%r25) /* r22 */
2067 copy %r22,%r1
2068 bv %r0(%r25) /* r23 */
2069 copy %r23,%r1
2070 bv %r0(%r25) /* r24 - shadowed */
2071 ldi -1,%r1
2072 bv %r0(%r25) /* r25 - shadowed */
2073 ldi -1,%r1
2074 bv %r0(%r25) /* r26 */
2075 copy %r26,%r1
2076 bv %r0(%r25) /* r27 */
2077 copy %r27,%r1
2078 bv %r0(%r25) /* r28 */
2079 copy %r28,%r1
2080 bv %r0(%r25) /* r29 */
2081 copy %r29,%r1
2082 bv %r0(%r25) /* r30 */
2083 copy %r30,%r1
2084 bv %r0(%r25) /* r31 */
2085 copy %r31,%r1
2086
2087
2088 set_register:
2089 /*
2090 * set_register is used by the non access tlb miss handlers to
2091 * copy the value of r1 into the general register specified in
2092 * r8.
2093 */
2094 blr %r8,%r0
2095 nop
2096 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2097 copy %r1,%r0
2098 bv %r0(%r25) /* r1 */
2099 copy %r1,%r1
2100 bv %r0(%r25) /* r2 */
2101 copy %r1,%r2
2102 bv %r0(%r25) /* r3 */
2103 copy %r1,%r3
2104 bv %r0(%r25) /* r4 */
2105 copy %r1,%r4
2106 bv %r0(%r25) /* r5 */
2107 copy %r1,%r5
2108 bv %r0(%r25) /* r6 */
2109 copy %r1,%r6
2110 bv %r0(%r25) /* r7 */
2111 copy %r1,%r7
2112 bv %r0(%r25) /* r8 */
2113 copy %r1,%r8
2114 bv %r0(%r25) /* r9 */
2115 copy %r1,%r9
2116 bv %r0(%r25) /* r10 */
2117 copy %r1,%r10
2118 bv %r0(%r25) /* r11 */
2119 copy %r1,%r11
2120 bv %r0(%r25) /* r12 */
2121 copy %r1,%r12
2122 bv %r0(%r25) /* r13 */
2123 copy %r1,%r13
2124 bv %r0(%r25) /* r14 */
2125 copy %r1,%r14
2126 bv %r0(%r25) /* r15 */
2127 copy %r1,%r15
2128 bv %r0(%r25) /* r16 */
2129 copy %r1,%r16
2130 bv %r0(%r25) /* r17 */
2131 copy %r1,%r17
2132 bv %r0(%r25) /* r18 */
2133 copy %r1,%r18
2134 bv %r0(%r25) /* r19 */
2135 copy %r1,%r19
2136 bv %r0(%r25) /* r20 */
2137 copy %r1,%r20
2138 bv %r0(%r25) /* r21 */
2139 copy %r1,%r21
2140 bv %r0(%r25) /* r22 */
2141 copy %r1,%r22
2142 bv %r0(%r25) /* r23 */
2143 copy %r1,%r23
2144 bv %r0(%r25) /* r24 */
2145 copy %r1,%r24
2146 bv %r0(%r25) /* r25 */
2147 copy %r1,%r25
2148 bv %r0(%r25) /* r26 */
2149 copy %r1,%r26
2150 bv %r0(%r25) /* r27 */
2151 copy %r1,%r27
2152 bv %r0(%r25) /* r28 */
2153 copy %r1,%r28
2154 bv %r0(%r25) /* r29 */
2155 copy %r1,%r29
2156 bv %r0(%r25) /* r30 */
2157 copy %r1,%r30
2158 bv %r0(%r25) /* r31 */
2159 copy %r1,%r31
2160
Linux kernel - Deliverables
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