2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/types.h>
36 #undef PARISC_IRQ_CR16_COUNTS
38 extern irqreturn_t
timer_interrupt(int, void *);
39 extern irqreturn_t
ipi_interrupt(int, void *);
41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
43 /* Bits in EIEM correlate with cpu_irq_action[].
44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
46 static volatile unsigned long cpu_eiem
= 0;
49 ** local ACK bitmap ... habitually set to 1, but reset to zero
50 ** between ->ack() and ->end() of the interrupt to prevent
51 ** re-interruption of a processing interrupt.
53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem
) = ~0UL;
55 static void cpu_mask_irq(struct irq_data
*d
)
57 unsigned long eirr_bit
= EIEM_MASK(d
->irq
);
59 cpu_eiem
&= ~eirr_bit
;
60 /* Do nothing on the other CPUs. If they get this interrupt,
61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
62 * handle it, and the set_eiem() at the bottom will ensure it
63 * then gets disabled */
66 static void __cpu_unmask_irq(unsigned int irq
)
68 unsigned long eirr_bit
= EIEM_MASK(irq
);
72 /* This is just a simple NOP IPI. But what it does is cause
73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
74 * of the interrupt handler */
78 static void cpu_unmask_irq(struct irq_data
*d
)
80 __cpu_unmask_irq(d
->irq
);
83 void cpu_ack_irq(struct irq_data
*d
)
85 unsigned long mask
= EIEM_MASK(d
->irq
);
86 int cpu
= smp_processor_id();
88 /* Clear in EIEM so we can no longer process */
89 per_cpu(local_ack_eiem
, cpu
) &= ~mask
;
91 /* disable the interrupt */
92 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
98 void cpu_eoi_irq(struct irq_data
*d
)
100 unsigned long mask
= EIEM_MASK(d
->irq
);
101 int cpu
= smp_processor_id();
103 /* set it in the eiems---it's no longer in process */
104 per_cpu(local_ack_eiem
, cpu
) |= mask
;
106 /* enable the interrupt */
107 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
111 int cpu_check_affinity(struct irq_data
*d
, const struct cpumask
*dest
)
115 /* timer and ipi have to always be received on all CPUs */
116 if (irqd_is_per_cpu(d
))
119 /* whatever mask they set, we just allow one CPU */
120 cpu_dest
= first_cpu(*dest
);
125 static int cpu_set_affinity_irq(struct irq_data
*d
, const struct cpumask
*dest
,
130 cpu_dest
= cpu_check_affinity(d
, dest
);
134 cpumask_copy(d
->affinity
, dest
);
140 static struct irq_chip cpu_interrupt_type
= {
142 .irq_mask
= cpu_mask_irq
,
143 .irq_unmask
= cpu_unmask_irq
,
144 .irq_ack
= cpu_ack_irq
,
145 .irq_eoi
= cpu_eoi_irq
,
147 .irq_set_affinity
= cpu_set_affinity_irq
,
149 /* XXX: Needs to be written. We managed without it so far, but
150 * we really ought to write it.
152 .irq_retrigger
= NULL
,
155 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t
, irq_stat
);
156 #define irq_stats(x) (&per_cpu(irq_stat, x))
159 * /proc/interrupts printing for arch specific interrupts
161 int arch_show_interrupts(struct seq_file
*p
, int prec
)
165 #ifdef CONFIG_DEBUG_STACKOVERFLOW
166 seq_printf(p
, "%*s: ", prec
, "STK");
167 for_each_online_cpu(j
)
168 seq_printf(p
, "%10u ", irq_stats(j
)->kernel_stack_usage
);
169 seq_printf(p
, " Kernel stack usage\n");
172 seq_printf(p
, "%*s: ", prec
, "RES");
173 for_each_online_cpu(j
)
174 seq_printf(p
, "%10u ", irq_stats(j
)->irq_resched_count
);
175 seq_printf(p
, " Rescheduling interrupts\n");
176 seq_printf(p
, "%*s: ", prec
, "CAL");
177 for_each_online_cpu(j
)
178 seq_printf(p
, "%10u ", irq_stats(j
)->irq_call_count
-
179 irq_stats(j
)->irq_tlb_count
);
180 seq_printf(p
, " Function call interrupts\n");
181 seq_printf(p
, "%*s: ", prec
, "TLB");
182 for_each_online_cpu(j
)
183 seq_printf(p
, "%10u ", irq_stats(j
)->irq_tlb_count
);
184 seq_printf(p
, " TLB shootdowns\n");
189 int show_interrupts(struct seq_file
*p
, void *v
)
191 int i
= *(loff_t
*) v
, j
;
196 for_each_online_cpu(j
)
197 seq_printf(p
, " CPU%d", j
);
199 #ifdef PARISC_IRQ_CR16_COUNTS
200 seq_printf(p
, " [min/avg/max] (CPU cycle counts)");
206 struct irq_desc
*desc
= irq_to_desc(i
);
207 struct irqaction
*action
;
209 raw_spin_lock_irqsave(&desc
->lock
, flags
);
210 action
= desc
->action
;
213 seq_printf(p
, "%3d: ", i
);
215 for_each_online_cpu(j
)
216 seq_printf(p
, "%10u ", kstat_irqs_cpu(i
, j
));
218 seq_printf(p
, "%10u ", kstat_irqs(i
));
221 seq_printf(p
, " %14s", irq_desc_get_chip(desc
)->name
);
222 #ifndef PARISC_IRQ_CR16_COUNTS
223 seq_printf(p
, " %s", action
->name
);
225 while ((action
= action
->next
))
226 seq_printf(p
, ", %s", action
->name
);
228 for ( ;action
; action
= action
->next
) {
229 unsigned int k
, avg
, min
, max
;
231 min
= max
= action
->cr16_hist
[0];
233 for (avg
= k
= 0; k
< PARISC_CR16_HIST_SIZE
; k
++) {
234 int hist
= action
->cr16_hist
[k
];
241 if (hist
> max
) max
= hist
;
242 if (hist
< min
) min
= hist
;
246 seq_printf(p
, " %s[%d/%d/%d]", action
->name
,
253 raw_spin_unlock_irqrestore(&desc
->lock
, flags
);
257 arch_show_interrupts(p
, 3);
265 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
266 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
268 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
269 ** Then use that to get the Transaction address and data.
272 int cpu_claim_irq(unsigned int irq
, struct irq_chip
*type
, void *data
)
274 if (irq_has_action(irq
))
276 if (irq_get_chip(irq
) != &cpu_interrupt_type
)
279 /* for iosapic interrupts */
281 irq_set_chip_and_handler(irq
, type
, handle_percpu_irq
);
282 irq_set_chip_data(irq
, data
);
283 __cpu_unmask_irq(irq
);
288 int txn_claim_irq(int irq
)
290 return cpu_claim_irq(irq
, NULL
, NULL
) ? -1 : irq
;
294 * The bits_wide parameter accommodates the limitations of the HW/SW which
296 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
297 * V-class (EPIC): 6 bits
298 * N/L/A-class (iosapic): 8 bits
299 * PCI 2.2 MSI: 16 bits
300 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
302 * On the service provider side:
303 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
304 * o PA 2.0 wide mode 6-bits (per processor)
305 * o IA64 8-bits (0-256 total)
307 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
308 * by the processor...and the N/L-class I/O subsystem supports more bits than
309 * PA2.0 has. The first case is the problem.
311 int txn_alloc_irq(unsigned int bits_wide
)
315 /* never return irq 0 cause that's the interval timer */
316 for (irq
= CPU_IRQ_BASE
+ 1; irq
<= CPU_IRQ_MAX
; irq
++) {
317 if (cpu_claim_irq(irq
, NULL
, NULL
) < 0)
319 if ((irq
- CPU_IRQ_BASE
) >= (1 << bits_wide
))
324 /* unlikely, but be prepared */
329 unsigned long txn_affinity_addr(unsigned int irq
, int cpu
)
332 struct irq_data
*d
= irq_get_irq_data(irq
);
333 cpumask_copy(d
->affinity
, cpumask_of(cpu
));
336 return per_cpu(cpu_data
, cpu
).txn_addr
;
340 unsigned long txn_alloc_addr(unsigned int virt_irq
)
342 static int next_cpu
= -1;
344 next_cpu
++; /* assign to "next" CPU we want this bugger on */
347 while ((next_cpu
< nr_cpu_ids
) &&
348 (!per_cpu(cpu_data
, next_cpu
).txn_addr
||
349 !cpu_online(next_cpu
)))
352 if (next_cpu
>= nr_cpu_ids
)
353 next_cpu
= 0; /* nothing else, assign monarch */
355 return txn_affinity_addr(virt_irq
, next_cpu
);
359 unsigned int txn_alloc_data(unsigned int virt_irq
)
361 return virt_irq
- CPU_IRQ_BASE
;
364 static inline int eirr_to_irq(unsigned long eirr
)
366 int bit
= fls_long(eirr
);
367 return (BITS_PER_LONG
- bit
) + TIMER_IRQ
;
370 int sysctl_panic_on_stackoverflow
= 1;
372 static inline void stack_overflow_check(struct pt_regs
*regs
)
374 #ifdef CONFIG_DEBUG_STACKOVERFLOW
375 #define STACK_MARGIN (256*6)
377 /* Our stack starts directly behind the thread_info struct. */
378 unsigned long stack_start
= (unsigned long) current_thread_info();
379 unsigned long sp
= regs
->gr
[30];
380 unsigned long stack_usage
;
381 unsigned int *last_usage
;
383 /* if sr7 != 0, we interrupted a userspace process which we do not want
384 * to check for stack overflow. We will only check the kernel stack. */
388 /* calculate kernel stack usage */
389 stack_usage
= sp
- stack_start
;
390 last_usage
= &per_cpu(irq_stat
.kernel_stack_usage
, smp_processor_id());
392 if (unlikely(stack_usage
> *last_usage
))
393 *last_usage
= stack_usage
;
395 if (likely(stack_usage
< (THREAD_SIZE
- STACK_MARGIN
)))
398 pr_emerg("stackcheck: %s will most likely overflow kernel stack "
399 "(sp:%lx, stk bottom-top:%lx-%lx)\n",
400 current
->comm
, sp
, stack_start
, stack_start
+ THREAD_SIZE
);
402 if (sysctl_panic_on_stackoverflow
)
403 panic("low stack detected by irq handler - check messages\n");
407 #ifdef CONFIG_IRQSTACKS
408 DEFINE_PER_CPU(union irq_stack_union
, irq_stack_union
);
410 static void execute_on_irq_stack(void *func
, unsigned long param1
)
412 unsigned long *irq_stack_start
;
413 unsigned long irq_stack
;
414 int cpu
= smp_processor_id();
416 irq_stack_start
= &per_cpu(irq_stack_union
, cpu
).stack
[0];
417 irq_stack
= (unsigned long) irq_stack_start
;
418 irq_stack
= ALIGN(irq_stack
, 16); /* align for stack frame usage */
420 BUG_ON(*irq_stack_start
); /* report bug if we were called recursive. */
421 *irq_stack_start
= 1;
423 /* This is where we switch to the IRQ stack. */
424 call_on_stack(param1
, func
, irq_stack
);
426 *irq_stack_start
= 0;
428 #endif /* CONFIG_IRQSTACKS */
430 /* ONLY called from entry.S:intr_extint() */
431 void do_cpu_irq_mask(struct pt_regs
*regs
)
433 struct pt_regs
*old_regs
;
434 unsigned long eirr_val
;
435 int irq
, cpu
= smp_processor_id();
437 struct irq_desc
*desc
;
441 old_regs
= set_irq_regs(regs
);
445 eirr_val
= mfctl(23) & cpu_eiem
& per_cpu(local_ack_eiem
, cpu
);
448 irq
= eirr_to_irq(eirr_val
);
451 desc
= irq_to_desc(irq
);
452 cpumask_copy(&dest
, desc
->irq_data
.affinity
);
453 if (irqd_is_per_cpu(&desc
->irq_data
) &&
454 !cpu_isset(smp_processor_id(), dest
)) {
455 int cpu
= first_cpu(dest
);
457 printk(KERN_DEBUG
"redirecting irq %d from CPU %d to %d\n",
458 irq
, smp_processor_id(), cpu
);
459 gsc_writel(irq
+ CPU_IRQ_BASE
,
460 per_cpu(cpu_data
, cpu
).hpa
);
464 stack_overflow_check(regs
);
466 #ifdef CONFIG_IRQSTACKS
467 execute_on_irq_stack(&generic_handle_irq
, irq
);
469 generic_handle_irq(irq
);
470 #endif /* CONFIG_IRQSTACKS */
474 set_irq_regs(old_regs
);
478 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
482 static struct irqaction timer_action
= {
483 .handler
= timer_interrupt
,
485 .flags
= IRQF_TIMER
| IRQF_PERCPU
| IRQF_IRQPOLL
,
489 static struct irqaction ipi_action
= {
490 .handler
= ipi_interrupt
,
492 .flags
= IRQF_PERCPU
,
496 static void claim_cpu_irqs(void)
499 for (i
= CPU_IRQ_BASE
; i
<= CPU_IRQ_MAX
; i
++) {
500 irq_set_chip_and_handler(i
, &cpu_interrupt_type
,
504 irq_set_handler(TIMER_IRQ
, handle_percpu_irq
);
505 setup_irq(TIMER_IRQ
, &timer_action
);
507 irq_set_handler(IPI_IRQ
, handle_percpu_irq
);
508 setup_irq(IPI_IRQ
, &ipi_action
);
512 void __init
init_IRQ(void)
514 local_irq_disable(); /* PARANOID - should already be disabled */
515 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
519 cpu_eiem
= EIEM_MASK(IPI_IRQ
) | EIEM_MASK(TIMER_IRQ
);
523 cpu_eiem
= EIEM_MASK(TIMER_IRQ
);
525 set_eiem(cpu_eiem
); /* EIEM : enable all external intr */