2 * PARISC TLB and cache flushing support
3 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
4 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
5 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * NOTE: fdc,fic, and pdc instructions that use base register modification
24 * should only use index and base registers that are not shadowed,
25 * so that the fast path emulation in the non access miss handler
44 #include <asm/assembly.h>
45 #include <asm/pgtable.h>
46 #include <asm/cache.h>
51 .export flush_tlb_all_local,code
59 * The pitlbe and pdtlbe instructions should only be used to
60 * flush the entire tlb. Also, there needs to be no intervening
61 * tlb operations, e.g. tlb misses, so the operation needs
62 * to happen in real mode with all interruptions disabled.
65 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
66 rsm PSW_SM_I, %r19 /* save I-bit state */
74 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
75 mtctl %r0, %cr17 /* Clear IIASQ tail */
76 mtctl %r0, %cr17 /* Clear IIASQ head */
77 mtctl %r1, %cr18 /* IIAOQ head */
79 mtctl %r1, %cr18 /* IIAOQ tail */
80 load32 REAL_MODE_PSW, %r1
85 1: ldil L%PA(cache_info), %r1
86 ldo R%PA(cache_info)(%r1), %r1
88 /* Flush Instruction Tlb */
90 LDREG ITLB_SID_BASE(%r1), %r20
91 LDREG ITLB_SID_STRIDE(%r1), %r21
92 LDREG ITLB_SID_COUNT(%r1), %r22
93 LDREG ITLB_OFF_BASE(%r1), %arg0
94 LDREG ITLB_OFF_STRIDE(%r1), %arg1
95 LDREG ITLB_OFF_COUNT(%r1), %arg2
96 LDREG ITLB_LOOP(%r1), %arg3
98 ADDIB= -1, %arg3, fitoneloop /* Preadjust and test */
99 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
100 copy %arg0, %r28 /* Init base addr */
102 fitmanyloop: /* Loop if LOOP >= 2 */
104 add %r21, %r20, %r20 /* increment space */
105 copy %arg2, %r29 /* Init middle loop count */
107 fitmanymiddle: /* Loop if LOOP >= 2 */
108 ADDIB> -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
110 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
111 ADDIB> -1, %r29, fitmanymiddle /* Middle loop decr */
112 copy %arg3, %r31 /* Re-init inner loop count */
114 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
115 ADDIB<=,n -1, %r22, fitdone /* Outer loop count decr */
117 fitoneloop: /* Loop if LOOP = 1 */
119 copy %arg0, %r28 /* init base addr */
120 copy %arg2, %r29 /* init middle loop count */
122 fitonemiddle: /* Loop if LOOP = 1 */
123 ADDIB> -1, %r29, fitonemiddle /* Middle loop count decr */
124 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
126 ADDIB> -1, %r22, fitoneloop /* Outer loop count decr */
127 add %r21, %r20, %r20 /* increment space */
133 LDREG DTLB_SID_BASE(%r1), %r20
134 LDREG DTLB_SID_STRIDE(%r1), %r21
135 LDREG DTLB_SID_COUNT(%r1), %r22
136 LDREG DTLB_OFF_BASE(%r1), %arg0
137 LDREG DTLB_OFF_STRIDE(%r1), %arg1
138 LDREG DTLB_OFF_COUNT(%r1), %arg2
139 LDREG DTLB_LOOP(%r1), %arg3
141 ADDIB= -1, %arg3, fdtoneloop /* Preadjust and test */
142 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
143 copy %arg0, %r28 /* Init base addr */
145 fdtmanyloop: /* Loop if LOOP >= 2 */
147 add %r21, %r20, %r20 /* increment space */
148 copy %arg2, %r29 /* Init middle loop count */
150 fdtmanymiddle: /* Loop if LOOP >= 2 */
151 ADDIB> -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
153 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
154 ADDIB> -1, %r29, fdtmanymiddle /* Middle loop decr */
155 copy %arg3, %r31 /* Re-init inner loop count */
157 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
158 ADDIB<=,n -1, %r22,fdtdone /* Outer loop count decr */
160 fdtoneloop: /* Loop if LOOP = 1 */
162 copy %arg0, %r28 /* init base addr */
163 copy %arg2, %r29 /* init middle loop count */
165 fdtonemiddle: /* Loop if LOOP = 1 */
166 ADDIB> -1, %r29, fdtonemiddle /* Middle loop count decr */
167 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
169 ADDIB> -1, %r22, fdtoneloop /* Outer loop count decr */
170 add %r21, %r20, %r20 /* increment space */
175 * Switch back to virtual mode
186 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
187 mtctl %r0, %cr17 /* Clear IIASQ tail */
188 mtctl %r0, %cr17 /* Clear IIASQ head */
189 mtctl %r1, %cr18 /* IIAOQ head */
191 mtctl %r1, %cr18 /* IIAOQ tail */
192 load32 KERNEL_PSW, %r1
193 or %r1, %r19, %r1 /* I-bit to state on entry */
194 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
204 .export flush_instruction_cache_local,code
205 .import cache_info,data
207 flush_instruction_cache_local:
213 ldil L%cache_info, %r1
214 ldo R%cache_info(%r1), %r1
216 /* Flush Instruction Cache */
218 LDREG ICACHE_BASE(%r1), %arg0
219 LDREG ICACHE_STRIDE(%r1), %arg1
220 LDREG ICACHE_COUNT(%r1), %arg2
221 LDREG ICACHE_LOOP(%r1), %arg3
222 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
223 ADDIB= -1, %arg3, fioneloop /* Preadjust and test */
224 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
226 fimanyloop: /* Loop if LOOP >= 2 */
227 ADDIB> -1, %r31, fimanyloop /* Adjusted inner loop decr */
229 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
230 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
231 ADDIB<=,n -1, %arg2, fisync /* Outer loop decr */
233 fioneloop: /* Loop if LOOP = 1 */
234 ADDIB> -1, %arg2, fioneloop /* Outer loop count decr */
235 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
239 mtsm %r22 /* restore I-bit */
246 .export flush_data_cache_local, code
247 .import cache_info, data
249 flush_data_cache_local:
255 ldil L%cache_info, %r1
256 ldo R%cache_info(%r1), %r1
258 /* Flush Data Cache */
260 LDREG DCACHE_BASE(%r1), %arg0
261 LDREG DCACHE_STRIDE(%r1), %arg1
262 LDREG DCACHE_COUNT(%r1), %arg2
263 LDREG DCACHE_LOOP(%r1), %arg3
265 ADDIB= -1, %arg3, fdoneloop /* Preadjust and test */
266 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
268 fdmanyloop: /* Loop if LOOP >= 2 */
269 ADDIB> -1, %r31, fdmanyloop /* Adjusted inner loop decr */
271 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
272 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
273 ADDIB<=,n -1, %arg2, fdsync /* Outer loop decr */
275 fdoneloop: /* Loop if LOOP = 1 */
276 ADDIB> -1, %arg2, fdoneloop /* Outer loop count decr */
277 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
282 mtsm %r22 /* restore I-bit */
289 .export copy_user_page_asm,code
298 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
299 * Unroll the loop by hand and arrange insn appropriately.
300 * GCC probably can do this just as well.
304 ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
305 ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
306 ldw 128(%r25), %r0 /* prefetch 2 */
309 ldw 192(%r25), %r0 /* prefetch 3 */
310 ldw 256(%r25), %r0 /* prefetch 4 */
352 ADDIB> -1, %r1, 1b /* bundle 10 */
353 ldd 0(%r25), %r19 /* start next loads */
358 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
359 * bundles (very restricted rules for bundling).
360 * Note that until (if) we start saving
361 * the full 64 bit register values on interrupt, we can't
362 * use ldd/std on a 32 bit kernel.
364 ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
410 * NOTE: Code in clear_user_page has a hard coded dependency on the
411 * maximum alias boundary being 4 Mb. We've been assured by the
412 * parisc chip designers that there will not ever be a parisc
413 * chip with a larger alias boundary (Never say never :-) ).
415 * Subtle: the dtlb miss handlers support the temp alias region by
416 * "knowing" that if a dtlb miss happens within the temp alias
417 * region it must have occurred while in clear_user_page. Since
418 * this routine makes use of processor local translations, we
419 * don't want to insert them into the kernel page table. Instead,
420 * we load up some general registers (they need to be registers
421 * which aren't shadowed) with the physical page numbers (preshifted
422 * for tlb insertion) needed to insert the translations. When we
423 * miss on the translation, the dtlb miss handler inserts the
424 * translation into the tlb using these values:
426 * %r26 physical page (shifted for tlb insert) of "to" translation
427 * %r23 physical page (shifted for tlb insert) of "from" translation
433 * We can't do this since copy_user_page is used to bring in
434 * file data that might have instructions. Since the data would
435 * then need to be flushed out so the i-fetch can see it, it
436 * makes more sense to just copy through the kernel translation
439 * I'm still keeping this around because it may be possible to
440 * use it if more information is passed into copy_user_page().
441 * Have to do some measurements to see if it is worthwhile to
442 * lobby for such a change.
445 .export copy_user_page_asm,code
452 ldil L%(__PAGE_OFFSET), %r1
454 sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
456 ldil L%(TMPALIAS_MAP_START), %r28
458 extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
459 extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
460 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
461 depdi 0, 63,12, %r28 /* Clear any offset bits */
463 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
465 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
466 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
467 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
468 depwi 0, 31,12, %r28 /* Clear any offset bits */
470 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
473 /* Purge any old translations */
481 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
482 * bundles (very restricted rules for bundling). It probably
483 * does OK on PCXU and better, but we could do better with
484 * ldd/std instructions. Note that until (if) we start saving
485 * the full 64 bit register values on interrupt, we can't
486 * use ldd/std on a 32 bit kernel.
534 .export __clear_user_page_asm,code
536 __clear_user_page_asm:
543 ldil L%(TMPALIAS_MAP_START), %r28
545 #if (TMPALIAS_MAP_START >= 0x80000000)
546 depdi 0, 31,32, %r28 /* clear any sign extension */
548 extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
549 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
550 depdi 0, 63,12, %r28 /* Clear any offset bits */
552 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
553 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
554 depwi 0, 31,12, %r28 /* Clear any offset bits */
557 /* Purge any old translation */
562 ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
564 /* PREFETCH (Write) has not (yet) been proven to help here */
565 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
588 ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
617 .export flush_kernel_dcache_page
619 flush_kernel_dcache_page:
624 ldil L%dcache_stride, %r1
625 ldw R%dcache_stride(%r1), %r23
628 depdi,z 1, 63-PAGE_SHIFT,1, %r25
630 depwi,z 1, 31-PAGE_SHIFT,1, %r25
661 .export flush_user_dcache_page
663 flush_user_dcache_page:
668 ldil L%dcache_stride, %r1
669 ldw R%dcache_stride(%r1), %r23
672 depdi,z 1,63-PAGE_SHIFT,1, %r25
674 depwi,z 1,31-PAGE_SHIFT,1, %r25
680 1: fdc,m %r23(%sr3, %r26)
681 fdc,m %r23(%sr3, %r26)
682 fdc,m %r23(%sr3, %r26)
683 fdc,m %r23(%sr3, %r26)
684 fdc,m %r23(%sr3, %r26)
685 fdc,m %r23(%sr3, %r26)
686 fdc,m %r23(%sr3, %r26)
687 fdc,m %r23(%sr3, %r26)
688 fdc,m %r23(%sr3, %r26)
689 fdc,m %r23(%sr3, %r26)
690 fdc,m %r23(%sr3, %r26)
691 fdc,m %r23(%sr3, %r26)
692 fdc,m %r23(%sr3, %r26)
693 fdc,m %r23(%sr3, %r26)
694 fdc,m %r23(%sr3, %r26)
696 fdc,m %r23(%sr3, %r26)
705 .export flush_user_icache_page
707 flush_user_icache_page:
712 ldil L%dcache_stride, %r1
713 ldw R%dcache_stride(%r1), %r23
716 depdi,z 1, 63-PAGE_SHIFT,1, %r25
718 depwi,z 1, 31-PAGE_SHIFT,1, %r25
724 1: fic,m %r23(%sr3, %r26)
725 fic,m %r23(%sr3, %r26)
726 fic,m %r23(%sr3, %r26)
727 fic,m %r23(%sr3, %r26)
728 fic,m %r23(%sr3, %r26)
729 fic,m %r23(%sr3, %r26)
730 fic,m %r23(%sr3, %r26)
731 fic,m %r23(%sr3, %r26)
732 fic,m %r23(%sr3, %r26)
733 fic,m %r23(%sr3, %r26)
734 fic,m %r23(%sr3, %r26)
735 fic,m %r23(%sr3, %r26)
736 fic,m %r23(%sr3, %r26)
737 fic,m %r23(%sr3, %r26)
738 fic,m %r23(%sr3, %r26)
740 fic,m %r23(%sr3, %r26)
750 .export purge_kernel_dcache_page
752 purge_kernel_dcache_page:
757 ldil L%dcache_stride, %r1
758 ldw R%dcache_stride(%r1), %r23
761 depdi,z 1, 63-PAGE_SHIFT,1, %r25
763 depwi,z 1, 31-PAGE_SHIFT,1, %r25
783 CMPB<< %r26, %r25, 1b
794 /* Currently not used, but it still is a possible alternate
798 .export flush_alias_page
807 ldil L%(TMPALIAS_MAP_START), %r28
809 extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
810 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
811 depdi 0, 63,12, %r28 /* Clear any offset bits */
813 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
814 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
815 depwi 0, 31,12, %r28 /* Clear any offset bits */
818 /* Purge any old translation */
822 ldil L%dcache_stride, %r1
823 ldw R%dcache_stride(%r1), %r23
826 depdi,z 1, 63-PAGE_SHIFT,1, %r29
828 depwi,z 1, 31-PAGE_SHIFT,1, %r29
848 CMPB<< %r28, %r29, 1b
859 .export flush_user_dcache_range_asm
861 flush_user_dcache_range_asm:
866 ldil L%dcache_stride, %r1
867 ldw R%dcache_stride(%r1), %r23
869 ANDCM %r26, %r21, %r26
871 1: CMPB<<,n %r26, %r25, 1b
872 fdc,m %r23(%sr3, %r26)
881 .export flush_kernel_dcache_range_asm
883 flush_kernel_dcache_range_asm:
888 ldil L%dcache_stride, %r1
889 ldw R%dcache_stride(%r1), %r23
891 ANDCM %r26, %r21, %r26
893 1: CMPB<<,n %r26, %r25,1b
904 .export flush_user_icache_range_asm
906 flush_user_icache_range_asm:
911 ldil L%icache_stride, %r1
912 ldw R%icache_stride(%r1), %r23
914 ANDCM %r26, %r21, %r26
916 1: CMPB<<,n %r26, %r25,1b
917 fic,m %r23(%sr3, %r26)
926 .export flush_kernel_icache_page
928 flush_kernel_icache_page:
933 ldil L%icache_stride, %r1
934 ldw R%icache_stride(%r1), %r23
937 depdi,z 1, 63-PAGE_SHIFT,1, %r25
939 depwi,z 1, 31-PAGE_SHIFT,1, %r25
960 CMPB<< %r26, %r25, 1b
970 .export flush_kernel_icache_range_asm
972 flush_kernel_icache_range_asm:
977 ldil L%icache_stride, %r1
978 ldw R%icache_stride(%r1), %r23
980 ANDCM %r26, %r21, %r26
982 1: CMPB<<,n %r26, %r25, 1b
991 /* align should cover use of rfi in disable_sr_hashing_asm and
995 .export disable_sr_hashing_asm,code
997 disable_sr_hashing_asm:
1003 * Switch to real mode
1014 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1015 mtctl %r0, %cr17 /* Clear IIASQ tail */
1016 mtctl %r0, %cr17 /* Clear IIASQ head */
1017 mtctl %r1, %cr18 /* IIAOQ head */
1019 mtctl %r1, %cr18 /* IIAOQ tail */
1020 load32 REAL_MODE_PSW, %r1
1025 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1026 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1027 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1032 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1034 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1035 .word 0x141c1a00 /* must issue twice */
1036 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1037 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1038 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1039 .word 0x141c1600 /* must issue twice */
1044 /* Disable Space Register Hashing for PCXL */
1046 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1047 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1048 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1053 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1055 .word 0x144008bc /* mfdiag %dr2, %r28 */
1056 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1057 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1061 /* Switch back to virtual mode */
1062 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1070 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1071 mtctl %r0, %cr17 /* Clear IIASQ tail */
1072 mtctl %r0, %cr17 /* Clear IIASQ head */
1073 mtctl %r1, %cr18 /* IIAOQ head */
1075 mtctl %r1, %cr18 /* IIAOQ tail */
1076 load32 KERNEL_PSW, %r1