arch/powerpc/boot/dts/fsl/b4si-post.dtsi

   1 /*
   2  * B4420 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * This software is provided by Freescale Semiconductor "as is" and any
  24  * express or implied warranties, including, but not limited to, the implied
  25  * warranties of merchantability and fitness for a particular purpose are
  26  * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27  * direct, indirect, incidental, special, exemplary, or consequential damages
  28  * (including, but not limited to, procurement of substitute goods or services;
  29  * loss of use, data, or profits; or business interruption) however caused and
  30  * on any theory of liability, whether in contract, strict liability, or tort
  31  * (including negligence or otherwise) arising in any way out of the use of
  32  * this software, even if advised of the possibility of such damage.
  33  */
  34
  35 &ifc {
  36         #address-cells = <2>;
  37         #size-cells = <1>;
  38         compatible = "fsl,ifc", "simple-bus";
  39         interrupts = <25 2 0 0>;
  40 };
  41
  42 /* controller at 0x200000 */
  43 &pci0 {
  44         compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0x0 0xff>;
  49         interrupts = <20 2 0 0>;
  50         fsl,iommu-parent = <&pamu0>;
  51         pcie@0 {
  52                 #interrupt-cells = <1>;
  53                 #size-cells = <2>;
  54                 #address-cells = <3>;
  55                 device_type = "pci";
  56                 interrupts = <20 2 0 0>;
  57                 interrupt-map-mask = <0xf800 0 0 7>;
  58                 interrupt-map = <
  59                         /* IDSEL 0x0 */
  60                         0000 0 0 1 &mpic 40 1 0 0
  61                         0000 0 0 2 &mpic 1 1 0 0
  62                         0000 0 0 3 &mpic 2 1 0 0
  63                         0000 0 0 4 &mpic 3 1 0 0
  64                         >;
  65         };
  66 };
  67
  68 &dcsr {
  69         #address-cells = <1>;
  70         #size-cells = <1>;
  71         compatible = "fsl,dcsr", "simple-bus";
  72
  73         dcsr-epu@0 {
  74                 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
  75                 interrupts = <52 2 0 0
  76                               84 2 0 0
  77                               85 2 0 0
  78                               94 2 0 0
  79                               95 2 0 0>;
  80                 reg = <0x0 0x1000>;
  81         };
  82         dcsr-npc {
  83                 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
  84                 reg = <0x1000 0x1000 0x1002000 0x10000>;
  85         };
  86         dcsr-nxc@2000 {
  87                 compatible = "fsl,dcsr-nxc";
  88                 reg = <0x2000 0x1000>;
  89         };
  90         dcsr-corenet {
  91                 compatible = "fsl,dcsr-corenet";
  92                 reg = <0x8000 0x1000 0x1A000 0x1000>;
  93         };
  94         dcsr-dpaa@9000 {
  95                 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
  96                 reg = <0x9000 0x1000>;
  97         };
  98         dcsr-ocn@11000 {
  99                 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
 100                 reg = <0x11000 0x1000>;
 101         };
 102         dcsr-ddr@12000 {
 103                 compatible = "fsl,dcsr-ddr";
 104                 dev-handle = <&ddr1>;
 105                 reg = <0x12000 0x1000>;
 106         };
 107         dcsr-nal@18000 {
 108                 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
 109                 reg = <0x18000 0x1000>;
 110         };
 111         dcsr-rcpm@22000 {
 112                 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
 113                 reg = <0x22000 0x1000>;
 114         };
 115         dcsr-snpc@30000 {
 116                 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
 117                 reg = <0x30000 0x1000 0x1022000 0x10000>;
 118         };
 119         dcsr-snpc@31000 {
 120                 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
 121                 reg = <0x31000 0x1000 0x1042000 0x10000>;
 122         };
 123         dcsr-cpu-sb-proxy@100000 {
 124                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 125                 cpu-handle = <&cpu0>;
 126                 reg = <0x100000 0x1000 0x101000 0x1000>;
 127         };
 128 };
 129
 130 &soc {
 131         #address-cells = <1>;
 132         #size-cells = <1>;
 133         device_type = "soc";
 134         compatible = "simple-bus";
 135
 136         soc-sram-error {
 137                 compatible = "fsl,soc-sram-error";
 138                 interrupts = <16 2 1 2>;
 139         };
 140
 141         corenet-law@0 {
 142                 compatible = "fsl,corenet-law";
 143                 reg = <0x0 0x1000>;
 144                 fsl,num-laws = <32>;
 145         };
 146
 147         ddr1: memory-controller@8000 {
 148                 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 149                 reg = <0x8000 0x1000>;
 150                 interrupts = <16 2 1 8>;
 151         };
 152
 153         cpc: l3-cache-controller@10000 {
 154                 compatible = "fsl,b4-l3-cache-controller", "cache";
 155                 reg = <0x10000 0x1000>;
 156                 interrupts = <16 2 1 4>;
 157         };
 158
 159         corenet-cf@18000 {
 160                 compatible = "fsl,b4-corenet-cf";
 161                 reg = <0x18000 0x1000>;
 162                 interrupts = <16 2 1 0>;
 163                 fsl,ccf-num-csdids = <32>;
 164                 fsl,ccf-num-snoopids = <32>;
 165         };
 166
 167         iommu@20000 {
 168                 compatible =  "fsl,pamu-v1.0", "fsl,pamu";
 169                 reg = <0x20000 0x4000>;
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 interrupts = <
 173                         24 2 0 0
 174                         16 2 1 1>;
 175
 176
 177                 /* PCIe, DMA, SRIO */
 178                 pamu0: pamu@0 {
 179                         reg = <0 0x1000>;
 180                         fsl,primary-cache-geometry = <8 1>;
 181                         fsl,secondary-cache-geometry = <32 2>;
 182                 };
 183
 184                 /* AXI2, Maple */
 185                 pamu1: pamu@1000 {
 186                         reg = <0x1000 0x1000>;
 187                         fsl,primary-cache-geometry = <32 1>;
 188                         fsl,secondary-cache-geometry = <32 2>;
 189                 };
 190
 191                 /* Q/BMan */
 192                 pamu2: pamu@2000 {
 193                         reg = <0x2000 0x1000>;
 194                         fsl,primary-cache-geometry = <32 1>;
 195                         fsl,secondary-cache-geometry = <32 2>;
 196                 };
 197
 198                 /* AXI1, FMAN */
 199                 pamu3: pamu@3000 {
 200                         reg = <0x3000 0x1000>;
 201                         fsl,primary-cache-geometry = <32 1>;
 202                         fsl,secondary-cache-geometry = <32 2>;
 203                 };
 204         };
 205
 206 /include/ "qoriq-mpic.dtsi"
 207
 208         guts: global-utilities@e0000 {
 209                 compatible = "fsl,b4-device-config";
 210                 reg = <0xe0000 0xe00>;
 211                 fsl,has-rstcr;
 212                 fsl,liodn-bits = <12>;
 213         };
 214
 215         clockgen: global-utilities@e1000 {
 216                 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
 217                 reg = <0xe1000 0x1000>;
 218         };
 219
 220         rcpm: global-utilities@e2000 {
 221                 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
 222                 reg = <0xe2000 0x1000>;
 223         };
 224
 225 /include/ "qoriq-dma-0.dtsi"
 226         dma@100300 {
 227                 fsl,iommu-parent = <&pamu0>;
 228                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 229         };
 230
 231 /include/ "qoriq-dma-1.dtsi"
 232         dma@101300 {
 233                 fsl,iommu-parent = <&pamu0>;
 234                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 235         };
 236
 237 /include/ "qonverge-usb2-dr-0.dtsi"
 238         usb0: usb@210000 {
 239                 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
 240                 fsl,iommu-parent = <&pamu1>;
 241                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 242         };
 243
 244 /include/ "qoriq-espi-0.dtsi"
 245         spi@110000 {
 246                 fsl,espi-num-chipselects = <4>;
 247         };
 248
 249 /include/ "qoriq-esdhc-0.dtsi"
 250         sdhc@114000 {
 251                 sdhci,auto-cmd12;
 252                 fsl,iommu-parent = <&pamu1>;
 253                 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 254         };
 255
 256 /include/ "qoriq-i2c-0.dtsi"
 257 /include/ "qoriq-i2c-1.dtsi"
 258 /include/ "qoriq-duart-0.dtsi"
 259 /include/ "qoriq-duart-1.dtsi"
 260 /include/ "qoriq-sec5.3-0.dtsi"
 261
 262         L2: l2-cache-controller@c20000 {
 263                 compatible = "fsl,b4-l2-cache-controller";
 264                 reg = <0xc20000 0x1000>;
 265                 next-level-cache = <&cpc>;
 266         };
 267 };