arch/powerpc/boot/dts/fsl/p4080si-post.dtsi

   1 /*
   2  * P4080/P4040 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &lbc {
  36         compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
  37         interrupts = <25 2 0 0>;
  38         #address-cells = <2>;
  39         #size-cells = <1>;
  40 };
  41
  42 /* controller at 0x200000 */
  43 &pci0 {
  44         compatible = "fsl,p4080-pcie";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0x0 0xff>;
  49         clock-frequency = <33333333>;
  50         interrupts = <16 2 1 15>;
  51         pcie@0 {
  52                 reg = <0 0 0 0 0>;
  53                 #interrupt-cells = <1>;
  54                 #size-cells = <2>;
  55                 #address-cells = <3>;
  56                 device_type = "pci";
  57                 interrupts = <16 2 1 15>;
  58                 interrupt-map-mask = <0xf800 0 0 7>;
  59                 interrupt-map = <
  60                         /* IDSEL 0x0 */
  61                         0000 0 0 1 &mpic 40 1 0 0
  62                         0000 0 0 2 &mpic 1 1 0 0
  63                         0000 0 0 3 &mpic 2 1 0 0
  64                         0000 0 0 4 &mpic 3 1 0 0
  65                         >;
  66         };
  67 };
  68
  69 /* controller at 0x201000 */
  70 &pci1 {
  71         compatible = "fsl,p4080-pcie";
  72         device_type = "pci";
  73         #size-cells = <2>;
  74         #address-cells = <3>;
  75         bus-range = <0 0xff>;
  76         clock-frequency = <33333333>;
  77         interrupts = <16 2 1 14>;
  78         pcie@0 {
  79                 reg = <0 0 0 0 0>;
  80                 #interrupt-cells = <1>;
  81                 #size-cells = <2>;
  82                 #address-cells = <3>;
  83                 device_type = "pci";
  84                 interrupts = <16 2 1 14>;
  85                 interrupt-map-mask = <0xf800 0 0 7>;
  86                 interrupt-map = <
  87                         /* IDSEL 0x0 */
  88                         0000 0 0 1 &mpic 41 1 0 0
  89                         0000 0 0 2 &mpic 5 1 0 0
  90                         0000 0 0 3 &mpic 6 1 0 0
  91                         0000 0 0 4 &mpic 7 1 0 0
  92                         >;
  93         };
  94 };
  95
  96 /* controller at 0x202000 */
  97 &pci2 {
  98         compatible = "fsl,p4080-pcie";
  99         device_type = "pci";
 100         #size-cells = <2>;
 101         #address-cells = <3>;
 102         bus-range = <0x0 0xff>;
 103         clock-frequency = <33333333>;
 104         interrupts = <16 2 1 13>;
 105         pcie@0 {
 106                 reg = <0 0 0 0 0>;
 107                 #interrupt-cells = <1>;
 108                 #size-cells = <2>;
 109                 #address-cells = <3>;
 110                 device_type = "pci";
 111                 interrupts = <16 2 1 13>;
 112                 interrupt-map-mask = <0xf800 0 0 7>;
 113                 interrupt-map = <
 114                         /* IDSEL 0x0 */
 115                         0000 0 0 1 &mpic 42 1 0 0
 116                         0000 0 0 2 &mpic 9 1 0 0
 117                         0000 0 0 3 &mpic 10 1 0 0
 118                         0000 0 0 4 &mpic 11 1 0 0
 119                         >;
 120         };
 121 };
 122
 123 &rio {
 124         compatible = "fsl,srio";
 125         interrupts = <16 2 1 11>;
 126         #address-cells = <2>;
 127         #size-cells = <2>;
 128         fsl,srio-rmu-handle = <&rmu>;
 129         ranges;
 130
 131         port1 {
 132                 #address-cells = <2>;
 133                 #size-cells = <2>;
 134                 cell-index = <1>;
 135         };
 136
 137         port2 {
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 cell-index = <2>;
 141         };
 142 };
 143
 144 &dcsr {
 145         #address-cells = <1>;
 146         #size-cells = <1>;
 147         compatible = "fsl,dcsr", "simple-bus";
 148
 149         dcsr-epu@0 {
 150                 compatible = "fsl,dcsr-epu";
 151                 interrupts = <52 2 0 0
 152                               84 2 0 0
 153                               85 2 0 0>;
 154                 reg = <0x0 0x1000>;
 155         };
 156         dcsr-npc {
 157                 compatible = "fsl,dcsr-npc";
 158                 reg = <0x1000 0x1000 0x1000000 0x8000>;
 159         };
 160         dcsr-nxc@2000 {
 161                 compatible = "fsl,dcsr-nxc";
 162                 reg = <0x2000 0x1000>;
 163         };
 164         dcsr-corenet {
 165                 compatible = "fsl,dcsr-corenet";
 166                 reg = <0x8000 0x1000 0xB0000 0x1000>;
 167         };
 168         dcsr-dpaa@9000 {
 169                 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
 170                 reg = <0x9000 0x1000>;
 171         };
 172         dcsr-ocn@11000 {
 173                 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
 174                 reg = <0x11000 0x1000>;
 175         };
 176         dcsr-ddr@12000 {
 177                 compatible = "fsl,dcsr-ddr";
 178                 dev-handle = <&ddr1>;
 179                 reg = <0x12000 0x1000>;
 180         };
 181         dcsr-ddr@13000 {
 182                 compatible = "fsl,dcsr-ddr";
 183                 dev-handle = <&ddr2>;
 184                 reg = <0x13000 0x1000>;
 185         };
 186         dcsr-nal@18000 {
 187                 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
 188                 reg = <0x18000 0x1000>;
 189         };
 190         dcsr-rcpm@22000 {
 191                 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
 192                 reg = <0x22000 0x1000>;
 193         };
 194         dcsr-cpu-sb-proxy@40000 {
 195                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 196                 cpu-handle = <&cpu0>;
 197                 reg = <0x40000 0x1000>;
 198         };
 199         dcsr-cpu-sb-proxy@41000 {
 200                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 201                 cpu-handle = <&cpu1>;
 202                 reg = <0x41000 0x1000>;
 203         };
 204         dcsr-cpu-sb-proxy@42000 {
 205                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 206                 cpu-handle = <&cpu2>;
 207                 reg = <0x42000 0x1000>;
 208         };
 209         dcsr-cpu-sb-proxy@43000 {
 210                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 211                 cpu-handle = <&cpu3>;
 212                 reg = <0x43000 0x1000>;
 213         };
 214         dcsr-cpu-sb-proxy@44000 {
 215                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 216                 cpu-handle = <&cpu4>;
 217                 reg = <0x44000 0x1000>;
 218         };
 219         dcsr-cpu-sb-proxy@45000 {
 220                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 221                 cpu-handle = <&cpu5>;
 222                 reg = <0x45000 0x1000>;
 223         };
 224         dcsr-cpu-sb-proxy@46000 {
 225                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 226                 cpu-handle = <&cpu6>;
 227                 reg = <0x46000 0x1000>;
 228         };
 229         dcsr-cpu-sb-proxy@47000 {
 230                 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 231                 cpu-handle = <&cpu7>;
 232                 reg = <0x47000 0x1000>;
 233         };
 234
 235 };
 236
 237 &soc {
 238         #address-cells = <1>;
 239         #size-cells = <1>;
 240         device_type = "soc";
 241         compatible = "simple-bus";
 242
 243         soc-sram-error {
 244                 compatible = "fsl,soc-sram-error";
 245                 interrupts = <16 2 1 29>;
 246         };
 247
 248         corenet-law@0 {
 249                 compatible = "fsl,corenet-law";
 250                 reg = <0x0 0x1000>;
 251                 fsl,num-laws = <32>;
 252         };
 253
 254         ddr1: memory-controller@8000 {
 255                 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
 256                 reg = <0x8000 0x1000>;
 257                 interrupts = <16 2 1 23>;
 258         };
 259
 260         ddr2: memory-controller@9000 {
 261                 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
 262                 reg = <0x9000 0x1000>;
 263                 interrupts = <16 2 1 22>;
 264         };
 265
 266         cpc: l3-cache-controller@10000 {
 267                 compatible = "fsl,p4080-l3-cache-controller", "cache";
 268                 reg = <0x10000 0x1000
 269                        0x11000 0x1000>;
 270                 interrupts = <16 2 1 27
 271                               16 2 1 26>;
 272         };
 273
 274         corenet-cf@18000 {
 275                 compatible = "fsl,corenet-cf";
 276                 reg = <0x18000 0x1000>;
 277                 interrupts = <16 2 1 31>;
 278                 fsl,ccf-num-csdids = <32>;
 279                 fsl,ccf-num-snoopids = <32>;
 280         };
 281
 282         iommu@20000 {
 283                 compatible = "fsl,pamu-v1.0", "fsl,pamu";
 284                 reg = <0x20000 0x5000>;
 285                 interrupts = <
 286                         24 2 0 0
 287                         16 2 1 30>;
 288         };
 289
 290 /include/ "qoriq-rmu-0.dtsi"
 291 /include/ "qoriq-mpic.dtsi"
 292
 293         guts: global-utilities@e0000 {
 294                 compatible = "fsl,qoriq-device-config-1.0";
 295                 reg = <0xe0000 0xe00>;
 296                 fsl,has-rstcr;
 297                 #sleep-cells = <1>;
 298                 fsl,liodn-bits = <12>;
 299         };
 300
 301         pins: global-utilities@e0e00 {
 302                 compatible = "fsl,qoriq-pin-control-1.0";
 303                 reg = <0xe0e00 0x200>;
 304                 #sleep-cells = <2>;
 305         };
 306
 307         clockgen: global-utilities@e1000 {
 308                 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
 309                 reg = <0xe1000 0x1000>;
 310                 clock-frequency = <0>;
 311         };
 312
 313         rcpm: global-utilities@e2000 {
 314                 compatible = "fsl,qoriq-rcpm-1.0";
 315                 reg = <0xe2000 0x1000>;
 316                 #sleep-cells = <1>;
 317         };
 318
 319         sfp: sfp@e8000 {
 320                 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
 321                 reg        = <0xe8000 0x1000>;
 322         };
 323
 324         serdes: serdes@ea000 {
 325                 compatible = "fsl,p4080-serdes";
 326                 reg        = <0xea000 0x1000>;
 327         };
 328
 329 /include/ "qoriq-dma-0.dtsi"
 330 /include/ "qoriq-dma-1.dtsi"
 331 /include/ "qoriq-espi-0.dtsi"
 332         spi@110000 {
 333                 fsl,espi-num-chipselects = <4>;
 334         };
 335
 336 /include/ "qoriq-esdhc-0.dtsi"
 337         sdhc@114000 {
 338                 voltage-ranges = <3300 3300>;
 339                 sdhci,auto-cmd12;
 340         };
 341
 342 /include/ "qoriq-i2c-0.dtsi"
 343 /include/ "qoriq-i2c-1.dtsi"
 344 /include/ "qoriq-duart-0.dtsi"
 345 /include/ "qoriq-duart-1.dtsi"
 346 /include/ "qoriq-gpio-0.dtsi"
 347 /include/ "qoriq-usb2-mph-0.dtsi"
 348         usb@210000 {
 349                 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 350                 port0;
 351         };
 352 /include/ "qoriq-usb2-dr-0.dtsi"
 353         usb@211000 {
 354                 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 355         };
 356 /include/ "qoriq-sec4.0-0.dtsi"
 357 };