2 * GE Fanuc SBC310 Device Tree Source
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
25 compatible = "gef,sbc310";
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
76 interrupt-parent = <&mpic>;
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
86 compatible = "cfi-flash";
87 reg = <0 0 0x01000000>;
94 reg = <0x00000000 0x01000000>;
101 compatible = "cfi-flash";
102 reg = <1 0 0x8000000>;
105 #address-cells = <1>;
109 reg = <0x00000000 0x07800000>;
113 reg = <0x07800000 0x00800000>;
119 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>;
124 #interrupt-cells = <2>;
125 device_type = "watchdog";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>;
133 #interrupt-cells = <2>;
134 device_type = "watchdog";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>;
141 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 compatible = "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>;
148 interrupt-parent = <&mpic>;
151 gef_gpio: gpio@4,8000 {
153 compatible = "gef,sbc310-gpio";
154 reg = <0x4 0x8000 0x24>;
160 #address-cells = <1>;
162 #interrupt-cells = <2>;
164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>;
170 compatible = "fsl,mcm-law";
176 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
177 reg = <0x1000 0x1000>;
179 interrupt-parent = <&mpic>;
183 #address-cells = <1>;
185 compatible = "fsl-i2c";
186 reg = <0x3000 0x100>;
187 interrupts = <0x2b 0x2>;
188 interrupt-parent = <&mpic>;
192 compatible = "epson,rx8581";
198 #address-cells = <1>;
200 compatible = "fsl-i2c";
201 reg = <0x3100 0x100>;
202 interrupts = <0x2b 0x2>;
203 interrupt-parent = <&mpic>;
207 compatible = "national,lm92";
212 compatible = "adi,adt7461";
217 compatible = "dallas,ds1682";
223 #address-cells = <1>;
225 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
227 ranges = <0x0 0x21100 0x200>;
230 compatible = "fsl,mpc8641-dma-channel",
231 "fsl,eloplus-dma-channel";
234 interrupt-parent = <&mpic>;
238 compatible = "fsl,mpc8641-dma-channel",
239 "fsl,eloplus-dma-channel";
242 interrupt-parent = <&mpic>;
246 compatible = "fsl,mpc8641-dma-channel",
247 "fsl,eloplus-dma-channel";
250 interrupt-parent = <&mpic>;
254 compatible = "fsl,mpc8641-dma-channel",
255 "fsl,eloplus-dma-channel";
258 interrupt-parent = <&mpic>;
263 enet0: ethernet@24000 {
264 #address-cells = <1>;
266 device_type = "network";
268 compatible = "gianfar";
269 reg = <0x24000 0x1000>;
270 ranges = <0x0 0x24000 0x1000>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
273 interrupt-parent = <&mpic>;
274 phy-handle = <&phy0>;
275 phy-connection-type = "gmii";
278 #address-cells = <1>;
280 compatible = "fsl,gianfar-mdio";
283 phy0: ethernet-phy@0 {
284 interrupt-parent = <&gef_pic>;
285 interrupts = <0x9 0x4>;
288 phy2: ethernet-phy@2 {
289 interrupt-parent = <&gef_pic>;
290 interrupts = <0x8 0x4>;
296 enet1: ethernet@26000 {
297 device_type = "network";
299 compatible = "gianfar";
300 reg = <0x26000 0x1000>;
301 local-mac-address = [ 00 00 00 00 00 00 ];
302 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
303 interrupt-parent = <&mpic>;
304 phy-handle = <&phy2>;
305 phy-connection-type = "gmii";
308 serial0: serial@4500 {
310 device_type = "serial";
311 compatible = "ns16550";
312 reg = <0x4500 0x100>;
313 clock-frequency = <0>;
314 interrupts = <0x2a 0x2>;
315 interrupt-parent = <&mpic>;
318 serial1: serial@4600 {
320 device_type = "serial";
321 compatible = "ns16550";
322 reg = <0x4600 0x100>;
323 clock-frequency = <0>;
324 interrupts = <0x1c 0x2>;
325 interrupt-parent = <&mpic>;
329 clock-frequency = <0>;
330 interrupt-controller;
331 #address-cells = <0>;
332 #interrupt-cells = <2>;
333 reg = <0x40000 0x40000>;
334 compatible = "chrp,open-pic";
335 device_type = "open-pic";
338 global-utilities@e0000 {
339 compatible = "fsl,mpc8641-guts";
340 reg = <0xe0000 0x1000>;
345 pci0: pcie@fef08000 {
346 compatible = "fsl,mpc8641-pcie";
348 #interrupt-cells = <1>;
350 #address-cells = <3>;
351 reg = <0xfef08000 0x1000>;
352 bus-range = <0x0 0xff>;
353 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
354 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
355 clock-frequency = <33333333>;
356 interrupt-parent = <&mpic>;
357 interrupts = <0x18 0x2>;
358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
361 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
362 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
363 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
369 #address-cells = <3>;
371 ranges = <0x02000000 0x0 0x80000000
372 0x02000000 0x0 0x80000000
375 0x01000000 0x0 0x00000000
376 0x01000000 0x0 0x00000000