2 * MPC8315E RDB Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,mpc8315erdb";
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <16384>;
37 i-cache-size = <16384>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
45 device_type = "memory";
46 reg = <0x00000000 0x08000000>; // 128MB at 0
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>;
57 // CS0 and CS1 are swapped when
58 // booting from nand, but the
59 // addresses are the same.
60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 0x1 0x0 0xe0600000 0x00002000
62 0x2 0x0 0xf0000000 0x00020000
63 0x3 0x0 0xfa000000 0x00008000>;
68 compatible = "cfi-flash";
69 reg = <0x0 0x0 0x800000>;
77 compatible = "fsl,mpc8315-fcm-nand",
79 reg = <0x1 0x0 0x2000>;
87 reg = <0x100000 0x300000>;
90 reg = <0x400000 0x1c00000>;
99 compatible = "fsl,mpc8315-immr", "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>;
105 device_type = "watchdog";
106 compatible = "mpc83xx_wdt";
111 #address-cells = <1>;
114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>;
116 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>;
121 compatible = "dallas,ds1339";
127 compatible = "fsl,mc9s08qg8-mpc8315erdb",
128 "fsl,mcu-mpc8349emitx";
136 compatible = "fsl,spi";
137 reg = <0x7000 0x1000>;
138 interrupts = <16 0x8>;
139 interrupt-parent = <&ipic>;
144 #address-cells = <1>;
146 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
148 ranges = <0 0x8100 0x1a8>;
149 interrupt-parent = <&ipic>;
153 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
156 interrupt-parent = <&ipic>;
160 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
163 interrupt-parent = <&ipic>;
167 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
170 interrupt-parent = <&ipic>;
174 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
177 interrupt-parent = <&ipic>;
183 compatible = "fsl-usb2-dr";
184 reg = <0x23000 0x1000>;
185 #address-cells = <1>;
187 interrupt-parent = <&ipic>;
188 interrupts = <38 0x8>;
193 #address-cells = <1>;
195 compatible = "fsl,gianfar-mdio";
196 reg = <0x24520 0x20>;
197 phy0: ethernet-phy@0 {
198 interrupt-parent = <&ipic>;
199 interrupts = <20 0x8>;
201 device_type = "ethernet-phy";
203 phy1: ethernet-phy@1 {
204 interrupt-parent = <&ipic>;
205 interrupts = <19 0x8>;
207 device_type = "ethernet-phy";
211 device_type = "tbi-phy";
216 #address-cells = <1>;
218 compatible = "fsl,gianfar-tbi";
219 reg = <0x25520 0x20>;
223 device_type = "tbi-phy";
228 enet0: ethernet@24000 {
230 device_type = "network";
232 compatible = "gianfar";
233 reg = <0x24000 0x1000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <32 0x8 33 0x8 34 0x8>;
236 interrupt-parent = <&ipic>;
237 tbi-handle = <&tbi0>;
238 phy-handle = < &phy0 >;
241 enet1: ethernet@25000 {
243 device_type = "network";
245 compatible = "gianfar";
246 reg = <0x25000 0x1000>;
247 local-mac-address = [ 00 00 00 00 00 00 ];
248 interrupts = <35 0x8 36 0x8 37 0x8>;
249 interrupt-parent = <&ipic>;
250 tbi-handle = <&tbi1>;
251 phy-handle = < &phy1 >;
254 serial0: serial@4500 {
256 device_type = "serial";
257 compatible = "ns16550";
258 reg = <0x4500 0x100>;
259 clock-frequency = <0>;
260 interrupts = <9 0x8>;
261 interrupt-parent = <&ipic>;
264 serial1: serial@4600 {
266 device_type = "serial";
267 compatible = "ns16550";
268 reg = <0x4600 0x100>;
269 clock-frequency = <0>;
270 interrupts = <10 0x8>;
271 interrupt-parent = <&ipic>;
275 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
276 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
278 reg = <0x30000 0x10000>;
279 interrupts = <11 0x8>;
280 interrupt-parent = <&ipic>;
281 fsl,num-channels = <4>;
282 fsl,channel-fifo-len = <24>;
283 fsl,exec-units-mask = <0x97c>;
284 fsl,descriptor-types-mask = <0x3ab0abf>;
288 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
289 reg = <0x18000 0x1000>;
291 interrupts = <44 0x8>;
292 interrupt-parent = <&ipic>;
296 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
297 reg = <0x19000 0x1000>;
299 interrupts = <45 0x8>;
300 interrupt-parent = <&ipic>;
304 * interrupts cell = <intr #, sense>
305 * sense values match linux IORESOURCE_IRQ_* defines:
306 * sense == 8: Level, low assertion
307 * sense == 2: Edge, high-to-low change
309 ipic: interrupt-controller@700 {
310 interrupt-controller;
311 #address-cells = <0>;
312 #interrupt-cells = <2>;
314 device_type = "ipic";
319 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
321 /* IDSEL 0x0E -mini PCI */
322 0x7000 0x0 0x0 0x1 &ipic 18 0x8
323 0x7000 0x0 0x0 0x2 &ipic 18 0x8
324 0x7000 0x0 0x0 0x3 &ipic 18 0x8
325 0x7000 0x0 0x0 0x4 &ipic 18 0x8
327 /* IDSEL 0x0F -mini PCI */
328 0x7800 0x0 0x0 0x1 &ipic 17 0x8
329 0x7800 0x0 0x0 0x2 &ipic 17 0x8
330 0x7800 0x0 0x0 0x3 &ipic 17 0x8
331 0x7800 0x0 0x0 0x4 &ipic 17 0x8
333 /* IDSEL 0x10 - PCI slot */
334 0x8000 0x0 0x0 0x1 &ipic 48 0x8
335 0x8000 0x0 0x0 0x2 &ipic 17 0x8
336 0x8000 0x0 0x0 0x3 &ipic 48 0x8
337 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
338 interrupt-parent = <&ipic>;
339 interrupts = <66 0x8>;
340 bus-range = <0x0 0x0>;
341 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
342 0x42000000 0 0x80000000 0x80000000 0 0x10000000
343 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
344 clock-frequency = <66666666>;
345 #interrupt-cells = <1>;
347 #address-cells = <3>;
348 reg = <0xe0008500 0x100 /* internal registers */
349 0xe0008300 0x8>; /* config space access registers */
350 compatible = "fsl,mpc8349-pci";