arch/powerpc/boot/dts/mpc8315erdb.dts

   1 /*
   2  * MPC8315E RDB Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         compatible = "fsl,mpc8315erdb";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 PowerPC,8315@0 {
  32                         device_type = "cpu";
  33                         reg = <0x0>;
  34                         d-cache-line-size = <32>;
  35                         i-cache-line-size = <32>;
  36                         d-cache-size = <16384>;
  37                         i-cache-size = <16384>;
  38                         timebase-frequency = <0>;       // from bootloader
  39                         bus-frequency = <0>;            // from bootloader
  40                         clock-frequency = <0>;          // from bootloader
  41                 };
  42         };
  43
  44         memory {
  45                 device_type = "memory";
  46                 reg = <0x00000000 0x08000000>;  // 128MB at 0
  47         };
  48
  49         localbus@e0005000 {
  50                 #address-cells = <2>;
  51                 #size-cells = <1>;
  52                 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
  53                 reg = <0xe0005000 0x1000>;
  54                 interrupts = <77 0x8>;
  55                 interrupt-parent = <&ipic>;
  56
  57                 // CS0 and CS1 are swapped when
  58                 // booting from nand, but the
  59                 // addresses are the same.
  60                 ranges = <0x0 0x0 0xfe000000 0x00800000
  61                           0x1 0x0 0xe0600000 0x00002000
  62                           0x2 0x0 0xf0000000 0x00020000
  63                           0x3 0x0 0xfa000000 0x00008000>;
  64
  65                 flash@0,0 {
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         compatible = "cfi-flash";
  69                         reg = <0x0 0x0 0x800000>;
  70                         bank-width = <2>;
  71                         device-width = <1>;
  72                 };
  73
  74                 nand@1,0 {
  75                         #address-cells = <1>;
  76                         #size-cells = <1>;
  77                         compatible = "fsl,mpc8315-fcm-nand",
  78                                      "fsl,elbc-fcm-nand";
  79                         reg = <0x1 0x0 0x2000>;
  80
  81                         u-boot@0 {
  82                                 reg = <0x0 0x100000>;
  83                                 read-only;
  84                         };
  85
  86                         kernel@100000 {
  87                                 reg = <0x100000 0x300000>;
  88                         };
  89                         fs@400000 {
  90                                 reg = <0x400000 0x1c00000>;
  91                         };
  92                 };
  93         };
  94
  95         immr@e0000000 {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 device_type = "soc";
  99                 compatible = "fsl,mpc8315-immr", "simple-bus";
 100                 ranges = <0 0xe0000000 0x00100000>;
 101                 reg = <0xe0000000 0x00000200>;
 102                 bus-frequency = <0>;
 103
 104                 wdt@200 {
 105                         device_type = "watchdog";
 106                         compatible = "mpc83xx_wdt";
 107                         reg = <0x200 0x100>;
 108                 };
 109
 110                 i2c@3000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         cell-index = <0>;
 114                         compatible = "fsl-i2c";
 115                         reg = <0x3000 0x100>;
 116                         interrupts = <14 0x8>;
 117                         interrupt-parent = <&ipic>;
 118                         dfsrr;
 119                         rtc@68 {
 120                                 compatible = "dallas,ds1339";
 121                                 reg = <0x68>;
 122                         };
 123
 124                         mcu_pio: mcu@a {
 125                                 #gpio-cells = <2>;
 126                                 compatible = "fsl,mc9s08qg8-mpc8315erdb",
 127                                              "fsl,mcu-mpc8349emitx";
 128                                 reg = <0x0a>;
 129                                 gpio-controller;
 130                         };
 131                 };
 132
 133                 spi@7000 {
 134                         cell-index = <0>;
 135                         compatible = "fsl,spi";
 136                         reg = <0x7000 0x1000>;
 137                         interrupts = <16 0x8>;
 138                         interrupt-parent = <&ipic>;
 139                         mode = "cpu";
 140                 };
 141
 142                 dma@82a8 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
 146                         reg = <0x82a8 4>;
 147                         ranges = <0 0x8100 0x1a8>;
 148                         interrupt-parent = <&ipic>;
 149                         interrupts = <71 8>;
 150                         cell-index = <0>;
 151                         dma-channel@0 {
 152                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
 153                                 reg = <0 0x80>;
 154                                 cell-index = <0>;
 155                                 interrupt-parent = <&ipic>;
 156                                 interrupts = <71 8>;
 157                         };
 158                         dma-channel@80 {
 159                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
 160                                 reg = <0x80 0x80>;
 161                                 cell-index = <1>;
 162                                 interrupt-parent = <&ipic>;
 163                                 interrupts = <71 8>;
 164                         };
 165                         dma-channel@100 {
 166                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
 167                                 reg = <0x100 0x80>;
 168                                 cell-index = <2>;
 169                                 interrupt-parent = <&ipic>;
 170                                 interrupts = <71 8>;
 171                         };
 172                         dma-channel@180 {
 173                                 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
 174                                 reg = <0x180 0x28>;
 175                                 cell-index = <3>;
 176                                 interrupt-parent = <&ipic>;
 177                                 interrupts = <71 8>;
 178                         };
 179                 };
 180
 181                 usb@23000 {
 182                         compatible = "fsl-usb2-dr";
 183                         reg = <0x23000 0x1000>;
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         interrupt-parent = <&ipic>;
 187                         interrupts = <38 0x8>;
 188                         phy_type = "utmi";
 189                 };
 190
 191                 mdio@24520 {
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         compatible = "fsl,gianfar-mdio";
 195                         reg = <0x24520 0x20>;
 196                         phy0: ethernet-phy@0 {
 197                                 interrupt-parent = <&ipic>;
 198                                 interrupts = <20 0x8>;
 199                                 reg = <0x0>;
 200                                 device_type = "ethernet-phy";
 201                         };
 202                         phy1: ethernet-phy@1 {
 203                                 interrupt-parent = <&ipic>;
 204                                 interrupts = <19 0x8>;
 205                                 reg = <0x1>;
 206                                 device_type = "ethernet-phy";
 207                         };
 208                 };
 209
 210                 enet0: ethernet@24000 {
 211                         cell-index = <0>;
 212                         device_type = "network";
 213                         model = "eTSEC";
 214                         compatible = "gianfar";
 215                         reg = <0x24000 0x1000>;
 216                         local-mac-address = [ 00 00 00 00 00 00 ];
 217                         interrupts = <32 0x8 33 0x8 34 0x8>;
 218                         interrupt-parent = <&ipic>;
 219                         phy-handle = < &phy0 >;
 220                 };
 221
 222                 enet1: ethernet@25000 {
 223                         cell-index = <1>;
 224                         device_type = "network";
 225                         model = "eTSEC";
 226                         compatible = "gianfar";
 227                         reg = <0x25000 0x1000>;
 228                         local-mac-address = [ 00 00 00 00 00 00 ];
 229                         interrupts = <35 0x8 36 0x8 37 0x8>;
 230                         interrupt-parent = <&ipic>;
 231                         phy-handle = < &phy1 >;
 232                 };
 233
 234                 serial0: serial@4500 {
 235                         cell-index = <0>;
 236                         device_type = "serial";
 237                         compatible = "ns16550";
 238                         reg = <0x4500 0x100>;
 239                         clock-frequency = <0>;
 240                         interrupts = <9 0x8>;
 241                         interrupt-parent = <&ipic>;
 242                 };
 243
 244                 serial1: serial@4600 {
 245                         cell-index = <1>;
 246                         device_type = "serial";
 247                         compatible = "ns16550";
 248                         reg = <0x4600 0x100>;
 249                         clock-frequency = <0>;
 250                         interrupts = <10 0x8>;
 251                         interrupt-parent = <&ipic>;
 252                 };
 253
 254                 crypto@30000 {
 255                         compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
 256                                      "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
 257                                      "fsl,sec2.0";
 258                         reg = <0x30000 0x10000>;
 259                         interrupts = <11 0x8>;
 260                         interrupt-parent = <&ipic>;
 261                         fsl,num-channels = <4>;
 262                         fsl,channel-fifo-len = <24>;
 263                         fsl,exec-units-mask = <0x97c>;
 264                         fsl,descriptor-types-mask = <0x3ab0abf>;
 265                 };
 266
 267                 sata@18000 {
 268                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
 269                         reg = <0x18000 0x1000>;
 270                         cell-index = <1>;
 271                         interrupts = <44 0x8>;
 272                         interrupt-parent = <&ipic>;
 273                 };
 274
 275                 sata@19000 {
 276                         compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
 277                         reg = <0x19000 0x1000>;
 278                         cell-index = <2>;
 279                         interrupts = <45 0x8>;
 280                         interrupt-parent = <&ipic>;
 281                 };
 282
 283                 /* IPIC
 284                  * interrupts cell = <intr #, sense>
 285                  * sense values match linux IORESOURCE_IRQ_* defines:
 286                  * sense == 8: Level, low assertion
 287                  * sense == 2: Edge, high-to-low change
 288                  */
 289                 ipic: interrupt-controller@700 {
 290                         interrupt-controller;
 291                         #address-cells = <0>;
 292                         #interrupt-cells = <2>;
 293                         reg = <0x700 0x100>;
 294                         device_type = "ipic";
 295                 };
 296         };
 297
 298         pci0: pci@e0008500 {
 299                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 300                 interrupt-map = <
 301                                 /* IDSEL 0x0E -mini PCI */
 302                                  0x7000 0x0 0x0 0x1 &ipic 18 0x8
 303                                  0x7000 0x0 0x0 0x2 &ipic 18 0x8
 304                                  0x7000 0x0 0x0 0x3 &ipic 18 0x8
 305                                  0x7000 0x0 0x0 0x4 &ipic 18 0x8
 306
 307                                 /* IDSEL 0x0F -mini PCI */
 308                                  0x7800 0x0 0x0 0x1 &ipic 17 0x8
 309                                  0x7800 0x0 0x0 0x2 &ipic 17 0x8
 310                                  0x7800 0x0 0x0 0x3 &ipic 17 0x8
 311                                  0x7800 0x0 0x0 0x4 &ipic 17 0x8
 312
 313                                 /* IDSEL 0x10 - PCI slot */
 314                                  0x8000 0x0 0x0 0x1 &ipic 48 0x8
 315                                  0x8000 0x0 0x0 0x2 &ipic 17 0x8
 316                                  0x8000 0x0 0x0 0x3 &ipic 48 0x8
 317                                  0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
 318                 interrupt-parent = <&ipic>;
 319                 interrupts = <66 0x8>;
 320                 bus-range = <0x0 0x0>;
 321                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
 322                           0x42000000 0 0x80000000 0x80000000 0 0x10000000
 323                           0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
 324                 clock-frequency = <66666666>;
 325                 #interrupt-cells = <1>;
 326                 #size-cells = <2>;
 327                 #address-cells = <3>;
 328                 reg = <0xe0008500 0x100         /* internal registers */
 329                        0xe0008300 0x8>;         /* config space access registers */
 330                 compatible = "fsl,mpc8349-pci";
 331                 device_type = "pci";
 332         };
 333 };