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Merge branch 'fix/hda' into topic/hda
[deliverable/linux.git] / arch / powerpc / boot / dts / mpc8568mds.dts
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 /dts-v1/;
13
14 / {
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8568@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x0 0x10000000>;
52 };
53
54 bcsr@f8000000 {
55 compatible = "fsl,mpc8568mds-bcsr";
56 reg = <0xf8000000 0x8000>;
57 };
58
59 soc8568@e0000000 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 device_type = "soc";
63 compatible = "simple-bus";
64 ranges = <0x0 0xe0000000 0x100000>;
65 reg = <0xe0000000 0x1000>;
66 bus-frequency = <0>;
67
68 memory-controller@2000 {
69 compatible = "fsl,8568-memory-controller";
70 reg = <0x2000 0x1000>;
71 interrupt-parent = <&mpic>;
72 interrupts = <18 2>;
73 };
74
75 L2: l2-cache-controller@20000 {
76 compatible = "fsl,8568-l2-cache-controller";
77 reg = <0x20000 0x1000>;
78 cache-line-size = <32>; // 32 bytes
79 cache-size = <0x80000>; // L2, 512K
80 interrupt-parent = <&mpic>;
81 interrupts = <16 2>;
82 };
83
84 i2c@3000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 cell-index = <0>;
88 compatible = "fsl-i2c";
89 reg = <0x3000 0x100>;
90 interrupts = <43 2>;
91 interrupt-parent = <&mpic>;
92 dfsrr;
93
94 rtc@68 {
95 compatible = "dallas,ds1374";
96 reg = <0x68>;
97 };
98 };
99
100 i2c@3100 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 cell-index = <1>;
104 compatible = "fsl-i2c";
105 reg = <0x3100 0x100>;
106 interrupts = <43 2>;
107 interrupt-parent = <&mpic>;
108 dfsrr;
109 };
110
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
115 reg = <0x21300 0x4>;
116 ranges = <0x0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8568-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8568-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8568-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8568-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
151
152 mdio@24520 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,gianfar-mdio";
156 reg = <0x24520 0x20>;
157
158 phy0: ethernet-phy@7 {
159 interrupt-parent = <&mpic>;
160 interrupts = <1 1>;
161 reg = <0x7>;
162 device_type = "ethernet-phy";
163 };
164 phy1: ethernet-phy@1 {
165 interrupt-parent = <&mpic>;
166 interrupts = <2 1>;
167 reg = <0x1>;
168 device_type = "ethernet-phy";
169 };
170 phy2: ethernet-phy@2 {
171 interrupt-parent = <&mpic>;
172 interrupts = <1 1>;
173 reg = <0x2>;
174 device_type = "ethernet-phy";
175 };
176 phy3: ethernet-phy@3 {
177 interrupt-parent = <&mpic>;
178 interrupts = <2 1>;
179 reg = <0x3>;
180 device_type = "ethernet-phy";
181 };
182 };
183
184 enet0: ethernet@24000 {
185 cell-index = <0>;
186 device_type = "network";
187 model = "eTSEC";
188 compatible = "gianfar";
189 reg = <0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 30 2 34 2>;
192 interrupt-parent = <&mpic>;
193 phy-handle = <&phy2>;
194 };
195
196 enet1: ethernet@25000 {
197 cell-index = <1>;
198 device_type = "network";
199 model = "eTSEC";
200 compatible = "gianfar";
201 reg = <0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 phy-handle = <&phy3>;
206 };
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <0>;
214 interrupts = <42 2>;
215 interrupt-parent = <&mpic>;
216 };
217
218 global-utilities@e0000 { //global utilities block
219 compatible = "fsl,mpc8548-guts";
220 reg = <0xe0000 0x1000>;
221 fsl,has-rstcr;
222 };
223
224 serial1: serial@4600 {
225 cell-index = <1>;
226 device_type = "serial";
227 compatible = "ns16550";
228 reg = <0x4600 0x100>;
229 clock-frequency = <0>;
230 interrupts = <42 2>;
231 interrupt-parent = <&mpic>;
232 };
233
234 crypto@30000 {
235 compatible = "fsl,sec2.1", "fsl,sec2.0";
236 reg = <0x30000 0x10000>;
237 interrupts = <45 2>;
238 interrupt-parent = <&mpic>;
239 fsl,num-channels = <4>;
240 fsl,channel-fifo-len = <24>;
241 fsl,exec-units-mask = <0xfe>;
242 fsl,descriptor-types-mask = <0x12b0ebf>;
243 };
244
245 mpic: pic@40000 {
246 interrupt-controller;
247 #address-cells = <0>;
248 #interrupt-cells = <2>;
249 reg = <0x40000 0x40000>;
250 compatible = "chrp,open-pic";
251 device_type = "open-pic";
252 };
253
254 par_io@e0100 {
255 reg = <0xe0100 0x100>;
256 device_type = "par_io";
257 num-ports = <7>;
258
259 pio1: ucc_pin@01 {
260 pio-map = <
261 /* port pin dir open_drain assignment has_irq */
262 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
263 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
264 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
265 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
266 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
267 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
268 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
269 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
270 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
271 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
272 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
273 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
274 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
275 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
276 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
277 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
278 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
279 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
280 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
281 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
282 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
283 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
284 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
285 };
286
287 pio2: ucc_pin@02 {
288 pio-map = <
289 /* port pin dir open_drain assignment has_irq */
290 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
291 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
292 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
293 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
294 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
295 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
296 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
297 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
298 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
299 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
300 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
301 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
302 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
303 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
304 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
305 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
306 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
307 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
308 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
309 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
310 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
311 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
312 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
313 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
314 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
315 };
316 };
317 };
318
319 qe@e0080000 {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 device_type = "qe";
323 compatible = "fsl,qe";
324 ranges = <0x0 0xe0080000 0x40000>;
325 reg = <0xe0080000 0x480>;
326 brg-frequency = <0>;
327 bus-frequency = <396000000>;
328
329 muram@10000 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,qe-muram", "fsl,cpm-muram";
333 ranges = <0x0 0x10000 0x10000>;
334
335 data-only@0 {
336 compatible = "fsl,qe-muram-data",
337 "fsl,cpm-muram-data";
338 reg = <0x0 0x10000>;
339 };
340 };
341
342 spi@4c0 {
343 cell-index = <0>;
344 compatible = "fsl,spi";
345 reg = <0x4c0 0x40>;
346 interrupts = <2>;
347 interrupt-parent = <&qeic>;
348 mode = "cpu";
349 };
350
351 spi@500 {
352 cell-index = <1>;
353 compatible = "fsl,spi";
354 reg = <0x500 0x40>;
355 interrupts = <1>;
356 interrupt-parent = <&qeic>;
357 mode = "cpu";
358 };
359
360 enet2: ucc@2000 {
361 device_type = "network";
362 compatible = "ucc_geth";
363 cell-index = <1>;
364 reg = <0x2000 0x200>;
365 interrupts = <32>;
366 interrupt-parent = <&qeic>;
367 local-mac-address = [ 00 00 00 00 00 00 ];
368 rx-clock-name = "none";
369 tx-clock-name = "clk16";
370 pio-handle = <&pio1>;
371 phy-handle = <&phy0>;
372 phy-connection-type = "rgmii-id";
373 };
374
375 enet3: ucc@3000 {
376 device_type = "network";
377 compatible = "ucc_geth";
378 cell-index = <2>;
379 reg = <0x3000 0x200>;
380 interrupts = <33>;
381 interrupt-parent = <&qeic>;
382 local-mac-address = [ 00 00 00 00 00 00 ];
383 rx-clock-name = "none";
384 tx-clock-name = "clk16";
385 pio-handle = <&pio2>;
386 phy-handle = <&phy1>;
387 phy-connection-type = "rgmii-id";
388 };
389
390 mdio@2120 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 reg = <0x2120 0x18>;
394 compatible = "fsl,ucc-mdio";
395
396 /* These are the same PHYs as on
397 * gianfar's MDIO bus */
398 qe_phy0: ethernet-phy@07 {
399 interrupt-parent = <&mpic>;
400 interrupts = <1 1>;
401 reg = <0x7>;
402 device_type = "ethernet-phy";
403 };
404 qe_phy1: ethernet-phy@01 {
405 interrupt-parent = <&mpic>;
406 interrupts = <2 1>;
407 reg = <0x1>;
408 device_type = "ethernet-phy";
409 };
410 qe_phy2: ethernet-phy@02 {
411 interrupt-parent = <&mpic>;
412 interrupts = <1 1>;
413 reg = <0x2>;
414 device_type = "ethernet-phy";
415 };
416 qe_phy3: ethernet-phy@03 {
417 interrupt-parent = <&mpic>;
418 interrupts = <2 1>;
419 reg = <0x3>;
420 device_type = "ethernet-phy";
421 };
422 };
423
424 qeic: interrupt-controller@80 {
425 interrupt-controller;
426 compatible = "fsl,qe-ic";
427 #address-cells = <0>;
428 #interrupt-cells = <1>;
429 reg = <0x80 0x80>;
430 big-endian;
431 interrupts = <46 2 46 2>; //high:30 low:30
432 interrupt-parent = <&mpic>;
433 };
434
435 };
436
437 pci0: pci@e0008000 {
438 cell-index = <0>;
439 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
440 interrupt-map = <
441 /* IDSEL 0x12 AD18 */
442 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
443 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
444 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
445 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
446
447 /* IDSEL 0x13 AD19 */
448 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
449 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
450 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
451 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
452
453 interrupt-parent = <&mpic>;
454 interrupts = <24 2>;
455 bus-range = <0 255>;
456 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
457 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
458 clock-frequency = <66666666>;
459 #interrupt-cells = <1>;
460 #size-cells = <2>;
461 #address-cells = <3>;
462 reg = <0xe0008000 0x1000>;
463 compatible = "fsl,mpc8540-pci";
464 device_type = "pci";
465 };
466
467 /* PCI Express */
468 pci1: pcie@e000a000 {
469 cell-index = <2>;
470 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
471 interrupt-map = <
472
473 /* IDSEL 0x0 (PEX) */
474 00000 0x0 0x0 0x1 &mpic 0x0 0x1
475 00000 0x0 0x0 0x2 &mpic 0x1 0x1
476 00000 0x0 0x0 0x3 &mpic 0x2 0x1
477 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
478
479 interrupt-parent = <&mpic>;
480 interrupts = <26 2>;
481 bus-range = <0 255>;
482 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
483 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
484 clock-frequency = <33333333>;
485 #interrupt-cells = <1>;
486 #size-cells = <2>;
487 #address-cells = <3>;
488 reg = <0xe000a000 0x1000>;
489 compatible = "fsl,mpc8548-pcie";
490 device_type = "pci";
491 pcie@0 {
492 reg = <0x0 0x0 0x0 0x0 0x0>;
493 #size-cells = <2>;
494 #address-cells = <3>;
495 device_type = "pci";
496 ranges = <0x2000000 0x0 0xa0000000
497 0x2000000 0x0 0xa0000000
498 0x0 0x10000000
499
500 0x1000000 0x0 0x0
501 0x1000000 0x0 0x0
502 0x0 0x800000>;
503 };
504 };
505 };
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