arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "MPC8610HPCD";
  15         compatible = "fsl,MPC8610HPCD";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24                 pci2 = &pci2;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 PowerPC,8610@0 {
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         d-cache-line-size = <32>;
  35                         i-cache-line-size = <32>;
  36                         d-cache-size = <32768>;         // L1
  37                         i-cache-size = <32768>;         // L1
  38                         timebase-frequency = <0>;       // From uboot
  39                         bus-frequency = <0>;            // From uboot
  40                         clock-frequency = <0>;          // From uboot
  41                 };
  42         };
  43
  44         memory {
  45                 device_type = "memory";
  46                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  47         };
  48
  49         localbus@e0005000 {
  50                 #address-cells = <2>;
  51                 #size-cells = <1>;
  52                 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
  53                 reg = <0xe0005000 0x1000>;
  54                 interrupts = <19 2>;
  55                 interrupt-parent = <&mpic>;
  56                 ranges = <0 0 0xf8000000 0x08000000
  57                           1 0 0xf0000000 0x08000000
  58                           2 0 0xe8400000 0x00008000
  59                           4 0 0xe8440000 0x00008000
  60                           5 0 0xe8480000 0x00008000
  61                           6 0 0xe84c0000 0x00008000
  62                           3 0 0xe8000000 0x00000020>;
  63
  64                 flash@0,0 {
  65                         compatible = "cfi-flash";
  66                         reg = <0 0 0x8000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69                 };
  70
  71                 flash@1,0 {
  72                         compatible = "cfi-flash";
  73                         reg = <1 0 0x8000000>;
  74                         bank-width = <2>;
  75                         device-width = <1>;
  76                 };
  77
  78                 flash@2,0 {
  79                         compatible = "fsl,mpc8610-fcm-nand",
  80                                      "fsl,elbc-fcm-nand";
  81                         reg = <2 0 0x8000>;
  82                 };
  83
  84                 flash@4,0 {
  85                         compatible = "fsl,mpc8610-fcm-nand",
  86                                      "fsl,elbc-fcm-nand";
  87                         reg = <4 0 0x8000>;
  88                 };
  89
  90                 flash@5,0 {
  91                         compatible = "fsl,mpc8610-fcm-nand",
  92                                      "fsl,elbc-fcm-nand";
  93                         reg = <5 0 0x8000>;
  94                 };
  95
  96                 flash@6,0 {
  97                         compatible = "fsl,mpc8610-fcm-nand",
  98                                      "fsl,elbc-fcm-nand";
  99                         reg = <6 0 0x8000>;
 100                 };
 101
 102                 board-control@3,0 {
 103                         compatible = "fsl,fpga-pixis";
 104                         reg = <3 0 0x20>;
 105                 };
 106         };
 107
 108         soc@e0000000 {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 #interrupt-cells = <2>;
 112                 device_type = "soc";
 113                 compatible = "fsl,mpc8610-immr", "simple-bus";
 114                 ranges = <0x0 0xe0000000 0x00100000>;
 115                 reg = <0xe0000000 0x1000>;
 116                 bus-frequency = <0>;
 117
 118                 i2c@3000 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         cell-index = <0>;
 122                         compatible = "fsl-i2c";
 123                         reg = <0x3000 0x100>;
 124                         interrupts = <43 2>;
 125                         interrupt-parent = <&mpic>;
 126                         dfsrr;
 127
 128                         cs4270:codec@4f {
 129                                 compatible = "cirrus,cs4270";
 130                                 reg = <0x4f>;
 131                                 /* MCLK source is a stand-alone oscillator */
 132                                 clock-frequency = <12288000>;
 133                         };
 134                 };
 135
 136                 i2c@3100 {
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         cell-index = <1>;
 140                         compatible = "fsl-i2c";
 141                         reg = <0x3100 0x100>;
 142                         interrupts = <43 2>;
 143                         interrupt-parent = <&mpic>;
 144                         dfsrr;
 145                 };
 146
 147                 serial0: serial@4500 {
 148                         cell-index = <0>;
 149                         device_type = "serial";
 150                         compatible = "ns16550";
 151                         reg = <0x4500 0x100>;
 152                         clock-frequency = <0>;
 153                         interrupts = <42 2>;
 154                         interrupt-parent = <&mpic>;
 155                 };
 156
 157                 serial1: serial@4600 {
 158                         cell-index = <1>;
 159                         device_type = "serial";
 160                         compatible = "ns16550";
 161                         reg = <0x4600 0x100>;
 162                         clock-frequency = <0>;
 163                         interrupts = <42 2>;
 164                         interrupt-parent = <&mpic>;
 165                 };
 166
 167                 display@2c000 {
 168                         compatible = "fsl,diu";
 169                         reg = <0x2c000 100>;
 170                         interrupts = <72 2>;
 171                         interrupt-parent = <&mpic>;
 172                 };
 173
 174                 mpic: interrupt-controller@40000 {
 175                         interrupt-controller;
 176                         #address-cells = <0>;
 177                         #interrupt-cells = <2>;
 178                         reg = <0x40000 0x40000>;
 179                         compatible = "chrp,open-pic";
 180                         device_type = "open-pic";
 181                 };
 182
 183                 msi@41600 {
 184                         compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
 185                         reg = <0x41600 0x80>;
 186                         msi-available-ranges = <0 0x100>;
 187                         interrupts = <
 188                                 0xe0 0
 189                                 0xe1 0
 190                                 0xe2 0
 191                                 0xe3 0
 192                                 0xe4 0
 193                                 0xe5 0
 194                                 0xe6 0
 195                                 0xe7 0>;
 196                         interrupt-parent = <&mpic>;
 197                 };
 198
 199                 global-utilities@e0000 {
 200                         compatible = "fsl,mpc8610-guts";
 201                         reg = <0xe0000 0x1000>;
 202                         fsl,has-rstcr;
 203                 };
 204
 205                 wdt@e4000 {
 206                         compatible = "fsl,mpc8610-wdt";
 207                         reg = <0xe4000 0x100>;
 208                 };
 209
 210                 ssi@16000 {
 211                         compatible = "fsl,mpc8610-ssi";
 212                         cell-index = <0>;
 213                         reg = <0x16000 0x100>;
 214                         interrupt-parent = <&mpic>;
 215                         interrupts = <62 2>;
 216                         fsl,mode = "i2s-slave";
 217                         codec-handle = <&cs4270>;
 218                         fsl,playback-dma = <&dma00>;
 219                         fsl,capture-dma = <&dma01>;
 220                         fsl,fifo-depth = <8>;
 221                 };
 222
 223                 ssi@16100 {
 224                         compatible = "fsl,mpc8610-ssi";
 225                         cell-index = <1>;
 226                         reg = <0x16100 0x100>;
 227                         interrupt-parent = <&mpic>;
 228                         interrupts = <63 2>;
 229                         fsl,fifo-depth = <8>;
 230                 };
 231
 232                 dma@21300 {
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 236                         cell-index = <0>;
 237                         reg = <0x21300 0x4>; /* DMA general status register */
 238                         ranges = <0x0 0x21100 0x200>;
 239
 240                         dma00: dma-channel@0 {
 241                                 compatible = "fsl,mpc8610-dma-channel",
 242                                         "fsl,ssi-dma-channel";
 243                                 cell-index = <0>;
 244                                 reg = <0x0 0x80>;
 245                                 interrupt-parent = <&mpic>;
 246                                 interrupts = <20 2>;
 247                         };
 248                         dma01: dma-channel@1 {
 249                                 compatible = "fsl,mpc8610-dma-channel",
 250                                         "fsl,ssi-dma-channel";
 251                                 cell-index = <1>;
 252                                 reg = <0x80 0x80>;
 253                                 interrupt-parent = <&mpic>;
 254                                 interrupts = <21 2>;
 255                         };
 256                         dma-channel@2 {
 257                                 compatible = "fsl,mpc8610-dma-channel",
 258                                         "fsl,eloplus-dma-channel";
 259                                 cell-index = <2>;
 260                                 reg = <0x100 0x80>;
 261                                 interrupt-parent = <&mpic>;
 262                                 interrupts = <22 2>;
 263                         };
 264                         dma-channel@3 {
 265                                 compatible = "fsl,mpc8610-dma-channel",
 266                                         "fsl,eloplus-dma-channel";
 267                                 cell-index = <3>;
 268                                 reg = <0x180 0x80>;
 269                                 interrupt-parent = <&mpic>;
 270                                 interrupts = <23 2>;
 271                         };
 272                 };
 273
 274                 dma@c300 {
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 278                         cell-index = <1>;
 279                         reg = <0xc300 0x4>; /* DMA general status register */
 280                         ranges = <0x0 0xc100 0x200>;
 281
 282                         dma-channel@0 {
 283                                 compatible = "fsl,mpc8610-dma-channel",
 284                                         "fsl,eloplus-dma-channel";
 285                                 cell-index = <0>;
 286                                 reg = <0x0 0x80>;
 287                                 interrupt-parent = <&mpic>;
 288                                 interrupts = <76 2>;
 289                         };
 290                         dma-channel@1 {
 291                                 compatible = "fsl,mpc8610-dma-channel",
 292                                         "fsl,eloplus-dma-channel";
 293                                 cell-index = <1>;
 294                                 reg = <0x80 0x80>;
 295                                 interrupt-parent = <&mpic>;
 296                                 interrupts = <77 2>;
 297                         };
 298                         dma-channel@2 {
 299                                 compatible = "fsl,mpc8610-dma-channel",
 300                                         "fsl,eloplus-dma-channel";
 301                                 cell-index = <2>;
 302                                 reg = <0x100 0x80>;
 303                                 interrupt-parent = <&mpic>;
 304                                 interrupts = <78 2>;
 305                         };
 306                         dma-channel@3 {
 307                                 compatible = "fsl,mpc8610-dma-channel",
 308                                         "fsl,eloplus-dma-channel";
 309                                 cell-index = <3>;
 310                                 reg = <0x180 0x80>;
 311                                 interrupt-parent = <&mpic>;
 312                                 interrupts = <79 2>;
 313                         };
 314                 };
 315
 316         };
 317
 318         pci0: pci@e0008000 {
 319                 cell-index = <0>;
 320                 compatible = "fsl,mpc8610-pci";
 321                 device_type = "pci";
 322                 #interrupt-cells = <1>;
 323                 #size-cells = <2>;
 324                 #address-cells = <3>;
 325                 reg = <0xe0008000 0x1000>;
 326                 bus-range = <0 0>;
 327                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 328                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 329                 clock-frequency = <33333333>;
 330                 interrupt-parent = <&mpic>;
 331                 interrupts = <24 2>;
 332                 interrupt-map-mask = <0xf800 0 0 7>;
 333                 interrupt-map = <
 334                         /* IDSEL 0x11 */
 335                         0x8800 0 0 1 &mpic 4 1
 336                         0x8800 0 0 2 &mpic 5 1
 337                         0x8800 0 0 3 &mpic 6 1
 338                         0x8800 0 0 4 &mpic 7 1
 339
 340                         /* IDSEL 0x12 */
 341                         0x9000 0 0 1 &mpic 5 1
 342                         0x9000 0 0 2 &mpic 6 1
 343                         0x9000 0 0 3 &mpic 7 1
 344                         0x9000 0 0 4 &mpic 4 1
 345                         >;
 346         };
 347
 348         pci1: pcie@e000a000 {
 349                 cell-index = <1>;
 350                 compatible = "fsl,mpc8641-pcie";
 351                 device_type = "pci";
 352                 #interrupt-cells = <1>;
 353                 #size-cells = <2>;
 354                 #address-cells = <3>;
 355                 reg = <0xe000a000 0x1000>;
 356                 bus-range = <1 3>;
 357                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 358                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 359                 clock-frequency = <33333333>;
 360                 interrupt-parent = <&mpic>;
 361                 interrupts = <26 2>;
 362                 interrupt-map-mask = <0xf800 0 0 7>;
 363
 364                 interrupt-map = <
 365                         /* IDSEL 0x1b */
 366                         0xd800 0 0 1 &mpic 2 1
 367
 368                         /* IDSEL 0x1c*/
 369                         0xe000 0 0 1 &mpic 1 1
 370                         0xe000 0 0 2 &mpic 1 1
 371                         0xe000 0 0 3 &mpic 1 1
 372                         0xe000 0 0 4 &mpic 1 1
 373
 374                         /* IDSEL 0x1f */
 375                         0xf800 0 0 1 &mpic 3 2
 376                         0xf800 0 0 2 &mpic 0 1
 377                 >;
 378
 379                 pcie@0 {
 380                         reg = <0 0 0 0 0>;
 381                         #size-cells = <2>;
 382                         #address-cells = <3>;
 383                         device_type = "pci";
 384                         ranges = <0x02000000 0x0 0xa0000000
 385                                   0x02000000 0x0 0xa0000000
 386                                   0x0 0x10000000
 387                                   0x01000000 0x0 0x00000000
 388                                   0x01000000 0x0 0x00000000
 389                                   0x0 0x00100000>;
 390                         uli1575@0 {
 391                                 reg = <0 0 0 0 0>;
 392                                 #size-cells = <2>;
 393                                 #address-cells = <3>;
 394                                 ranges = <0x02000000 0x0 0xa0000000
 395                                           0x02000000 0x0 0xa0000000
 396                                           0x0 0x10000000
 397                                           0x01000000 0x0 0x00000000
 398                                           0x01000000 0x0 0x00000000
 399                                           0x0 0x00100000>;
 400
 401                                 isa@1e {
 402                                         device_type = "isa";
 403                                         #size-cells = <1>;
 404                                         #address-cells = <2>;
 405                                         reg = <0xf000 0 0 0 0>;
 406                                         ranges = <1 0 0x01000000 0 0
 407                                                   0x00001000>;
 408
 409                                         rtc@70 {
 410                                                 compatible = "pnpPNP,b00";
 411                                                 reg = <1 0x70 2>;
 412                                         };
 413                                 };
 414                         };
 415                 };
 416         };
 417
 418         pci2: pcie@e0009000 {
 419                 #address-cells = <3>;
 420                 #size-cells = <2>;
 421                 #interrupt-cells = <1>;
 422                 device_type = "pci";
 423                 compatible = "fsl,mpc8641-pcie";
 424                 reg = <0xe0009000 0x00001000>;
 425                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
 426                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
 427                 bus-range = <0 255>;
 428                 interrupt-map-mask = <0xf800 0 0 7>;
 429                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
 430                                  0x0000 0 0 2 &mpic 5 1
 431                                  0x0000 0 0 3 &mpic 6 1
 432                                  0x0000 0 0 4 &mpic 7 1>;
 433                 interrupt-parent = <&mpic>;
 434                 interrupts = <25 2>;
 435                 clock-frequency = <33333333>;
 436         };
 437 };