arch/powerpc/include/asm/book3s/64/mmu-hash.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
   3 /*
   4  * PowerPC64 memory management structures
   5  *
   6  * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   7  *   PPC64 rework.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <asm/asm-compat.h>
  16 #include <asm/page.h>
  17 #include <asm/bug.h>
  18
  19 /*
  20  * This is necessary to get the definition of PGTABLE_RANGE which we
  21  * need for various slices related matters. Note that this isn't the
  22  * complete pgtable.h but only a portion of it.
  23  */
  24 #include <asm/book3s/64/pgtable.h>
  25 #include <asm/bug.h>
  26 #include <asm/processor.h>
  27
  28 /*
  29  * SLB
  30  */
  31
  32 #define SLB_NUM_BOLTED          3
  33 #define SLB_CACHE_ENTRIES       8
  34 #define SLB_MIN_SIZE            32
  35
  36 /* Bits in the SLB ESID word */
  37 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  38
  39 /* Bits in the SLB VSID word */
  40 #define SLB_VSID_SHIFT          12
  41 #define SLB_VSID_SHIFT_1T       24
  42 #define SLB_VSID_SSIZE_SHIFT    62
  43 #define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  44 #define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  45 #define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  46 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  47 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  48 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  49 #define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  50 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  51 #define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  52 #define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  53 #define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  54 #define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  55 #define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  56 #define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  57
  58 #define SLB_VSID_KERNEL         (SLB_VSID_KP)
  59 #define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  60
  61 #define SLBIE_C                 (0x08000000)
  62 #define SLBIE_SSIZE_SHIFT       25
  63
  64 /*
  65  * Hash table
  66  */
  67
  68 #define HPTES_PER_GROUP 8
  69
  70 #define HPTE_V_SSIZE_SHIFT      62
  71 #define HPTE_V_AVPN_SHIFT       7
  72 #define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  73 #define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  74 #define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  75 #define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  76 #define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  77 #define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  78 #define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  79 #define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  80
  81 #define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
  82 #define HPTE_R_TS               ASM_CONST(0x4000000000000000)
  83 #define HPTE_R_KEY_HI           ASM_CONST(0x3000000000000000)
  84 #define HPTE_R_RPN_SHIFT        12
  85 #define HPTE_R_RPN              ASM_CONST(0x0ffffffffffff000)
  86 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
  87 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
  88 #define HPTE_R_G                ASM_CONST(0x0000000000000008)
  89 #define HPTE_R_M                ASM_CONST(0x0000000000000010)
  90 #define HPTE_R_I                ASM_CONST(0x0000000000000020)
  91 #define HPTE_R_W                ASM_CONST(0x0000000000000040)
  92 #define HPTE_R_WIMG             ASM_CONST(0x0000000000000078)
  93 #define HPTE_R_C                ASM_CONST(0x0000000000000080)
  94 #define HPTE_R_R                ASM_CONST(0x0000000000000100)
  95 #define HPTE_R_KEY_LO           ASM_CONST(0x0000000000000e00)
  96
  97 #define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
  98 #define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
  99
 100 /* Values for PP (assumes Ks=0, Kp=1) */
 101 #define PP_RWXX 0       /* Supervisor read/write, User none */
 102 #define PP_RWRX 1       /* Supervisor read/write, User read */
 103 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
 104 #define PP_RXRX 3       /* Supervisor read,       User read */
 105 #define PP_RXXX (HPTE_R_PP0 | 2)        /* Supervisor read, user none */
 106
 107 /* Fields for tlbiel instruction in architecture 2.06 */
 108 #define TLBIEL_INVAL_SEL_MASK   0xc00   /* invalidation selector */
 109 #define  TLBIEL_INVAL_PAGE      0x000   /* invalidate a single page */
 110 #define  TLBIEL_INVAL_SET_LPID  0x800   /* invalidate a set for current LPID */
 111 #define  TLBIEL_INVAL_SET       0xc00   /* invalidate a set for all LPIDs */
 112 #define TLBIEL_INVAL_SET_MASK   0xfff000        /* set number to inval. */
 113 #define TLBIEL_INVAL_SET_SHIFT  12
 114
 115 #define POWER7_TLB_SETS         128     /* # sets in POWER7 TLB */
 116 #define POWER8_TLB_SETS         512     /* # sets in POWER8 TLB */
 117 #define POWER9_TLB_SETS_HASH    256     /* # sets in POWER9 TLB Hash mode */
 118
 119 #ifndef __ASSEMBLY__
 120
 121 struct hash_pte {
 122         __be64 v;
 123         __be64 r;
 124 };
 125
 126 extern struct hash_pte *htab_address;
 127 extern unsigned long htab_size_bytes;
 128 extern unsigned long htab_hash_mask;
 129
 130
 131 static inline int shift_to_mmu_psize(unsigned int shift)
 132 {
 133         int psize;
 134
 135         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
 136                 if (mmu_psize_defs[psize].shift == shift)
 137                         return psize;
 138         return -1;
 139 }
 140
 141 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 142 {
 143         if (mmu_psize_defs[mmu_psize].shift)
 144                 return mmu_psize_defs[mmu_psize].shift;
 145         BUG();
 146 }
 147
 148 #endif /* __ASSEMBLY__ */
 149
 150 /*
 151  * Segment sizes.
 152  * These are the values used by hardware in the B field of
 153  * SLB entries and the first dword of MMU hashtable entries.
 154  * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 155  */
 156 #define MMU_SEGSIZE_256M        0
 157 #define MMU_SEGSIZE_1T          1
 158
 159 /*
 160  * encode page number shift.
 161  * in order to fit the 78 bit va in a 64 bit variable we shift the va by
 162  * 12 bits. This enable us to address upto 76 bit va.
 163  * For hpt hash from a va we can ignore the page size bits of va and for
 164  * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
 165  * we work in all cases including 4k page size.
 166  */
 167 #define VPN_SHIFT       12
 168
 169 /*
 170  * HPTE Large Page (LP) details
 171  */
 172 #define LP_SHIFT        12
 173 #define LP_BITS         8
 174 #define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
 175
 176 #ifndef __ASSEMBLY__
 177
 178 static inline int slb_vsid_shift(int ssize)
 179 {
 180         if (ssize == MMU_SEGSIZE_256M)
 181                 return SLB_VSID_SHIFT;
 182         return SLB_VSID_SHIFT_1T;
 183 }
 184
 185 static inline int segment_shift(int ssize)
 186 {
 187         if (ssize == MMU_SEGSIZE_256M)
 188                 return SID_SHIFT;
 189         return SID_SHIFT_1T;
 190 }
 191
 192 /*
 193  * The current system page and segment sizes
 194  */
 195 extern int mmu_kernel_ssize;
 196 extern int mmu_highuser_ssize;
 197 extern u16 mmu_slb_size;
 198 extern unsigned long tce_alloc_start, tce_alloc_end;
 199
 200 /*
 201  * If the processor supports 64k normal pages but not 64k cache
 202  * inhibited pages, we have to be prepared to switch processes
 203  * to use 4k pages when they create cache-inhibited mappings.
 204  * If this is the case, mmu_ci_restrictions will be set to 1.
 205  */
 206 extern int mmu_ci_restrictions;
 207
 208 /*
 209  * This computes the AVPN and B fields of the first dword of a HPTE,
 210  * for use when we want to match an existing PTE.  The bottom 7 bits
 211  * of the returned value are zero.
 212  */
 213 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
 214                                              int ssize)
 215 {
 216         unsigned long v;
 217         /*
 218          * The AVA field omits the low-order 23 bits of the 78 bits VA.
 219          * These bits are not needed in the PTE, because the
 220          * low-order b of these bits are part of the byte offset
 221          * into the virtual page and, if b < 23, the high-order
 222          * 23-b of these bits are always used in selecting the
 223          * PTEGs to be searched
 224          */
 225         v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
 226         v <<= HPTE_V_AVPN_SHIFT;
 227         v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
 228         return v;
 229 }
 230
 231 /*
 232  * This function sets the AVPN and L fields of the HPTE  appropriately
 233  * using the base page size and actual page size.
 234  */
 235 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
 236                                           int actual_psize, int ssize)
 237 {
 238         unsigned long v;
 239         v = hpte_encode_avpn(vpn, base_psize, ssize);
 240         if (actual_psize != MMU_PAGE_4K)
 241                 v |= HPTE_V_LARGE;
 242         return v;
 243 }
 244
 245 /*
 246  * This function sets the ARPN, and LP fields of the HPTE appropriately
 247  * for the page size. We assume the pa is already "clean" that is properly
 248  * aligned for the requested page size
 249  */
 250 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
 251                                           int actual_psize)
 252 {
 253         /* A 4K page needs no special encoding */
 254         if (actual_psize == MMU_PAGE_4K)
 255                 return pa & HPTE_R_RPN;
 256         else {
 257                 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
 258                 unsigned int shift = mmu_psize_defs[actual_psize].shift;
 259                 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
 260         }
 261 }
 262
 263 /*
 264  * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
 265  */
 266 static inline unsigned long hpt_vpn(unsigned long ea,
 267                                     unsigned long vsid, int ssize)
 268 {
 269         unsigned long mask;
 270         int s_shift = segment_shift(ssize);
 271
 272         mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
 273         return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
 274 }
 275
 276 /*
 277  * This hashes a virtual address
 278  */
 279 static inline unsigned long hpt_hash(unsigned long vpn,
 280                                      unsigned int shift, int ssize)
 281 {
 282         int mask;
 283         unsigned long hash, vsid;
 284
 285         /* VPN_SHIFT can be atmost 12 */
 286         if (ssize == MMU_SEGSIZE_256M) {
 287                 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
 288                 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
 289                         ((vpn & mask) >> (shift - VPN_SHIFT));
 290         } else {
 291                 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
 292                 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
 293                 hash = vsid ^ (vsid << 25) ^
 294                         ((vpn & mask) >> (shift - VPN_SHIFT)) ;
 295         }
 296         return hash & 0x7fffffffffUL;
 297 }
 298
 299 #define HPTE_LOCAL_UPDATE       0x1
 300 #define HPTE_NOHPTE_UPDATE      0x2
 301
 302 extern int __hash_page_4K(unsigned long ea, unsigned long access,
 303                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 304                           unsigned long flags, int ssize, int subpage_prot);
 305 extern int __hash_page_64K(unsigned long ea, unsigned long access,
 306                            unsigned long vsid, pte_t *ptep, unsigned long trap,
 307                            unsigned long flags, int ssize);
 308 struct mm_struct;
 309 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
 310 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
 311                         unsigned long access, unsigned long trap,
 312                         unsigned long flags);
 313 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
 314                      unsigned long dsisr);
 315 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 316                      pte_t *ptep, unsigned long trap, unsigned long flags,
 317                      int ssize, unsigned int shift, unsigned int mmu_psize);
 318 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 319 extern int __hash_page_thp(unsigned long ea, unsigned long access,
 320                            unsigned long vsid, pmd_t *pmdp, unsigned long trap,
 321                            unsigned long flags, int ssize, unsigned int psize);
 322 #else
 323 static inline int __hash_page_thp(unsigned long ea, unsigned long access,
 324                                   unsigned long vsid, pmd_t *pmdp,
 325                                   unsigned long trap, unsigned long flags,
 326                                   int ssize, unsigned int psize)
 327 {
 328         BUG();
 329         return -1;
 330 }
 331 #endif
 332 extern void hash_failure_debug(unsigned long ea, unsigned long access,
 333                                unsigned long vsid, unsigned long trap,
 334                                int ssize, int psize, int lpsize,
 335                                unsigned long pte);
 336 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 337                              unsigned long pstart, unsigned long prot,
 338                              int psize, int ssize);
 339 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 340                         int psize, int ssize);
 341 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
 342 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 343
 344 extern void hpte_init_native(void);
 345 extern void hpte_init_lpar(void);
 346 extern void hpte_init_beat(void);
 347 extern void hpte_init_beat_v3(void);
 348
 349 extern void slb_initialize(void);
 350 extern void slb_flush_and_rebolt(void);
 351
 352 extern void slb_vmalloc_update(void);
 353 extern void slb_set_size(u16 size);
 354 #endif /* __ASSEMBLY__ */
 355
 356 /*
 357  * VSID allocation (256MB segment)
 358  *
 359  * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
 360  * from mmu context id and effective segment id of the address.
 361  *
 362  * For user processes max context id is limited to ((1ul << 19) - 5)
 363  * for kernel space, we use the top 4 context ids to map address as below
 364  * NOTE: each context only support 64TB now.
 365  * 0x7fffc -  [ 0xc000000000000000 - 0xc0003fffffffffff ]
 366  * 0x7fffd -  [ 0xd000000000000000 - 0xd0003fffffffffff ]
 367  * 0x7fffe -  [ 0xe000000000000000 - 0xe0003fffffffffff ]
 368  * 0x7ffff -  [ 0xf000000000000000 - 0xf0003fffffffffff ]
 369  *
 370  * The proto-VSIDs are then scrambled into real VSIDs with the
 371  * multiplicative hash:
 372  *
 373  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 374  *
 375  * VSID_MULTIPLIER is prime, so in particular it is
 376  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 377  * Because the modulus is 2^n-1 we can compute it efficiently without
 378  * a divide or extra multiply (see below). The scramble function gives
 379  * robust scattering in the hash table (at least based on some initial
 380  * results).
 381  *
 382  * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
 383  * bad address. This enables us to consolidate bad address handling in
 384  * hash_page.
 385  *
 386  * We also need to avoid the last segment of the last context, because that
 387  * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
 388  * because of the modulo operation in vsid scramble. But the vmemmap
 389  * (which is what uses region 0xf) will never be close to 64TB in size
 390  * (it's 56 bytes per page of system memory).
 391  */
 392
 393 #define CONTEXT_BITS            19
 394 #define ESID_BITS               18
 395 #define ESID_BITS_1T            6
 396
 397 /*
 398  * 256MB segment
 399  * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
 400  * available for user + kernel mapping. The top 4 contexts are used for
 401  * kernel mapping. Each segment contains 2^28 bytes. Each
 402  * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
 403  * (19 == 37 + 28 - 46).
 404  */
 405 #define MAX_USER_CONTEXT        ((ASM_CONST(1) << CONTEXT_BITS) - 5)
 406
 407 /*
 408  * This should be computed such that protovosid * vsid_mulitplier
 409  * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
 410  */
 411 #define VSID_MULTIPLIER_256M    ASM_CONST(12538073)     /* 24-bit prime */
 412 #define VSID_BITS_256M          (CONTEXT_BITS + ESID_BITS)
 413 #define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
 414
 415 #define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
 416 #define VSID_BITS_1T            (CONTEXT_BITS + ESID_BITS_1T)
 417 #define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
 418
 419
 420 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
 421
 422 /*
 423  * This macro generates asm code to compute the VSID scramble
 424  * function.  Used in slb_allocate() and do_stab_bolted.  The function
 425  * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 426  *
 427  *      rt = register continaing the proto-VSID and into which the
 428  *              VSID will be stored
 429  *      rx = scratch register (clobbered)
 430  *
 431  *      - rt and rx must be different registers
 432  *      - The answer will end up in the low VSID_BITS bits of rt.  The higher
 433  *        bits may contain other garbage, so you may need to mask the
 434  *        result.
 435  */
 436 #define ASM_VSID_SCRAMBLE(rt, rx, size)                                 \
 437         lis     rx,VSID_MULTIPLIER_##size@h;                            \
 438         ori     rx,rx,VSID_MULTIPLIER_##size@l;                         \
 439         mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 440                                                                         \
 441         srdi    rx,rt,VSID_BITS_##size;                                 \
 442         clrldi  rt,rt,(64-VSID_BITS_##size);                            \
 443         add     rt,rt,rx;               /* add high and low bits */     \
 444         /* NOTE: explanation based on VSID_BITS_##size = 36             \
 445          * Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 446          * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 447          * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 448          * the bit clear, r3 already has the answer we want, if it      \
 449          * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 450          * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 451         addi    rx,rt,1;                                                \
 452         srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
 453         add     rt,rt,rx
 454
 455 /* 4 bits per slice and we have one slice per 1TB */
 456 #define SLICE_ARRAY_SIZE  (PGTABLE_RANGE >> 41)
 457
 458 #ifndef __ASSEMBLY__
 459
 460 #ifdef CONFIG_PPC_SUBPAGE_PROT
 461 /*
 462  * For the sub-page protection option, we extend the PGD with one of
 463  * these.  Basically we have a 3-level tree, with the top level being
 464  * the protptrs array.  To optimize speed and memory consumption when
 465  * only addresses < 4GB are being protected, pointers to the first
 466  * four pages of sub-page protection words are stored in the low_prot
 467  * array.
 468  * Each page of sub-page protection words protects 1GB (4 bytes
 469  * protects 64k).  For the 3-level tree, each page of pointers then
 470  * protects 8TB.
 471  */
 472 struct subpage_prot_table {
 473         unsigned long maxaddr;  /* only addresses < this are protected */
 474         unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
 475         unsigned int *low_prot[4];
 476 };
 477
 478 #define SBP_L1_BITS             (PAGE_SHIFT - 2)
 479 #define SBP_L2_BITS             (PAGE_SHIFT - 3)
 480 #define SBP_L1_COUNT            (1 << SBP_L1_BITS)
 481 #define SBP_L2_COUNT            (1 << SBP_L2_BITS)
 482 #define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
 483 #define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
 484
 485 extern void subpage_prot_free(struct mm_struct *mm);
 486 extern void subpage_prot_init_new_context(struct mm_struct *mm);
 487 #else
 488 static inline void subpage_prot_free(struct mm_struct *mm) {}
 489 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
 490 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 491
 492 #if 0
 493 /*
 494  * The code below is equivalent to this function for arguments
 495  * < 2^VSID_BITS, which is all this should ever be called
 496  * with.  However gcc is not clever enough to compute the
 497  * modulus (2^n-1) without a second multiply.
 498  */
 499 #define vsid_scramble(protovsid, size) \
 500         ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
 501
 502 #else /* 1 */
 503 #define vsid_scramble(protovsid, size) \
 504         ({                                                               \
 505                 unsigned long x;                                         \
 506                 x = (protovsid) * VSID_MULTIPLIER_##size;                \
 507                 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
 508                 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
 509         })
 510 #endif /* 1 */
 511
 512 /* Returns the segment size indicator for a user address */
 513 static inline int user_segment_size(unsigned long addr)
 514 {
 515         /* Use 1T segments if possible for addresses >= 1T */
 516         if (addr >= (1UL << SID_SHIFT_1T))
 517                 return mmu_highuser_ssize;
 518         return MMU_SEGSIZE_256M;
 519 }
 520
 521 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
 522                                      int ssize)
 523 {
 524         /*
 525          * Bad address. We return VSID 0 for that
 526          */
 527         if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
 528                 return 0;
 529
 530         if (ssize == MMU_SEGSIZE_256M)
 531                 return vsid_scramble((context << ESID_BITS)
 532                                      | (ea >> SID_SHIFT), 256M);
 533         return vsid_scramble((context << ESID_BITS_1T)
 534                              | (ea >> SID_SHIFT_1T), 1T);
 535 }
 536
 537 /*
 538  * This is only valid for addresses >= PAGE_OFFSET
 539  *
 540  * For kernel space, we use the top 4 context ids to map address as below
 541  * 0x7fffc -  [ 0xc000000000000000 - 0xc0003fffffffffff ]
 542  * 0x7fffd -  [ 0xd000000000000000 - 0xd0003fffffffffff ]
 543  * 0x7fffe -  [ 0xe000000000000000 - 0xe0003fffffffffff ]
 544  * 0x7ffff -  [ 0xf000000000000000 - 0xf0003fffffffffff ]
 545  */
 546 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 547 {
 548         unsigned long context;
 549
 550         /*
 551          * kernel take the top 4 context from the available range
 552          */
 553         context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
 554         return get_vsid(context, ea, ssize);
 555 }
 556
 557 unsigned htab_shift_for_mem_size(unsigned long mem_size);
 558
 559 #endif /* __ASSEMBLY__ */
 560
 561 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */