arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         union {
  20                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  21                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  22         };
  23 };
  24 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  25
  26 #define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)
  27
  28 #endif /* __ASSEMBLY__ */
  29
  30 /* 64-bit classic hash table MMU */
  31 #include <asm/book3s/64/mmu-hash.h>
  32
  33 #ifndef __ASSEMBLY__
  34 /*
  35  * ISA 3.0 partiton and process table entry format
  36  */
  37 struct prtb_entry {
  38         __be64 prtb0;
  39         __be64 prtb1;
  40 };
  41 extern struct prtb_entry *process_tb;
  42
  43 struct patb_entry {
  44         __be64 patb0;
  45         __be64 patb1;
  46 };
  47 extern struct patb_entry *partition_tb;
  48
  49 #define PATB_HR         (1UL << 63)
  50 #define PATB_GR         (1UL << 63)
  51 #define RPDB_MASK       0x0ffffffffffff00fUL
  52 #define RPDB_SHIFT      (1UL << 8)
  53 /*
  54  * Limit process table to PAGE_SIZE table. This
  55  * also limit the max pid we can support.
  56  * MAX_USER_CONTEXT * 16 bytes of space.
  57  */
  58 #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
  59 /*
  60  * Power9 currently only support 64K partition table size.
  61  */
  62 #define PATB_SIZE_SHIFT 16
  63
  64 typedef unsigned long mm_context_id_t;
  65 struct spinlock;
  66
  67 typedef struct {
  68         mm_context_id_t id;
  69         u16 user_psize;         /* page size index */
  70
  71 #ifdef CONFIG_PPC_MM_SLICES
  72         u64 low_slices_psize;   /* SLB page size encodings */
  73         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  74 #else
  75         u16 sllp;               /* SLB page size encoding */
  76 #endif
  77         unsigned long vdso_base;
  78 #ifdef CONFIG_PPC_SUBPAGE_PROT
  79         struct subpage_prot_table spt;
  80 #endif /* CONFIG_PPC_SUBPAGE_PROT */
  81 #ifdef CONFIG_PPC_ICSWX
  82         struct spinlock *cop_lockp; /* guard acop and cop_pid */
  83         unsigned long acop;     /* mask of enabled coprocessor types */
  84         unsigned int cop_pid;   /* pid value used with coprocessors */
  85 #endif /* CONFIG_PPC_ICSWX */
  86 #ifdef CONFIG_PPC_64K_PAGES
  87         /* for 4K PTE fragment support */
  88         void *pte_frag;
  89 #endif
  90 #ifdef CONFIG_SPAPR_TCE_IOMMU
  91         struct list_head iommu_group_mem_list;
  92 #endif
  93 } mm_context_t;
  94
  95 /*
  96  * The current system page and segment sizes
  97  */
  98 extern int mmu_linear_psize;
  99 extern int mmu_virtual_psize;
 100 extern int mmu_vmalloc_psize;
 101 extern int mmu_vmemmap_psize;
 102 extern int mmu_io_psize;
 103
 104 /* MMU initialization */
 105 extern void radix_init_native(void);
 106 extern void hash__early_init_mmu(void);
 107 extern void radix__early_init_mmu(void);
 108 static inline void early_init_mmu(void)
 109 {
 110         if (radix_enabled())
 111                 return radix__early_init_mmu();
 112         return hash__early_init_mmu();
 113 }
 114 extern void hash__early_init_mmu_secondary(void);
 115 extern void radix__early_init_mmu_secondary(void);
 116 static inline void early_init_mmu_secondary(void)
 117 {
 118         if (radix_enabled())
 119                 return radix__early_init_mmu_secondary();
 120         return hash__early_init_mmu_secondary();
 121 }
 122
 123 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 124                                          phys_addr_t first_memblock_size);
 125 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 126                                          phys_addr_t first_memblock_size);
 127 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 128                                               phys_addr_t first_memblock_size)
 129 {
 130         if (radix_enabled())
 131                 return radix__setup_initial_memory_limit(first_memblock_base,
 132                                                    first_memblock_size);
 133         return hash__setup_initial_memory_limit(first_memblock_base,
 134                                            first_memblock_size);
 135 }
 136 #endif /* __ASSEMBLY__ */
 137 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */