arch/powerpc/include/asm/book3s/64/mmu.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
   2 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Page size definition
   7  *
   8  *    shift : is the "PAGE_SHIFT" value for that page size
   9  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
  10  *            directly to a slbmte "vsid" value
  11  *    penc  : is the HPTE encoding mask for the "LP" field:
  12  *
  13  */
  14 struct mmu_psize_def {
  15         unsigned int    shift;  /* number of bits */
  16         int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
  17         unsigned int    tlbiel; /* tlbiel supported for that page size */
  18         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
  19         union {
  20                 unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
  21                 unsigned long ap;       /* Ap encoding used by PowerISA 3.0 */
  22         };
  23 };
  24 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  25
  26 #ifdef CONFIG_PPC_RADIX_MMU
  27 #define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)
  28 #else
  29 #define radix_enabled() (0)
  30 #endif
  31
  32
  33 #endif /* __ASSEMBLY__ */
  34
  35 /* 64-bit classic hash table MMU */
  36 #include <asm/book3s/64/mmu-hash.h>
  37
  38 #ifndef __ASSEMBLY__
  39 /*
  40  * ISA 3.0 partiton and process table entry format
  41  */
  42 struct prtb_entry {
  43         __be64 prtb0;
  44         __be64 prtb1;
  45 };
  46 extern struct prtb_entry *process_tb;
  47
  48 struct patb_entry {
  49         __be64 patb0;
  50         __be64 patb1;
  51 };
  52 extern struct patb_entry *partition_tb;
  53
  54 #define PATB_HR         (1UL << 63)
  55 #define PATB_GR         (1UL << 63)
  56 #define RPDB_MASK       0x0ffffffffffff00fUL
  57 #define RPDB_SHIFT      (1UL << 8)
  58 /*
  59  * Limit process table to PAGE_SIZE table. This
  60  * also limit the max pid we can support.
  61  * MAX_USER_CONTEXT * 16 bytes of space.
  62  */
  63 #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
  64 /*
  65  * Power9 currently only support 64K partition table size.
  66  */
  67 #define PATB_SIZE_SHIFT 16
  68
  69 typedef unsigned long mm_context_id_t;
  70 struct spinlock;
  71
  72 typedef struct {
  73         mm_context_id_t id;
  74         u16 user_psize;         /* page size index */
  75
  76 #ifdef CONFIG_PPC_MM_SLICES
  77         u64 low_slices_psize;   /* SLB page size encodings */
  78         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
  79 #else
  80         u16 sllp;               /* SLB page size encoding */
  81 #endif
  82         unsigned long vdso_base;
  83 #ifdef CONFIG_PPC_SUBPAGE_PROT
  84         struct subpage_prot_table spt;
  85 #endif /* CONFIG_PPC_SUBPAGE_PROT */
  86 #ifdef CONFIG_PPC_ICSWX
  87         struct spinlock *cop_lockp; /* guard acop and cop_pid */
  88         unsigned long acop;     /* mask of enabled coprocessor types */
  89         unsigned int cop_pid;   /* pid value used with coprocessors */
  90 #endif /* CONFIG_PPC_ICSWX */
  91 #ifdef CONFIG_PPC_64K_PAGES
  92         /* for 4K PTE fragment support */
  93         void *pte_frag;
  94 #endif
  95 #ifdef CONFIG_SPAPR_TCE_IOMMU
  96         struct list_head iommu_group_mem_list;
  97 #endif
  98 } mm_context_t;
  99
 100 /*
 101  * The current system page and segment sizes
 102  */
 103 extern int mmu_linear_psize;
 104 extern int mmu_virtual_psize;
 105 extern int mmu_vmalloc_psize;
 106 extern int mmu_vmemmap_psize;
 107 extern int mmu_io_psize;
 108
 109 /* MMU initialization */
 110 extern void radix_init_native(void);
 111 extern void hash__early_init_mmu(void);
 112 extern void radix__early_init_mmu(void);
 113 static inline void early_init_mmu(void)
 114 {
 115         if (radix_enabled())
 116                 return radix__early_init_mmu();
 117         return hash__early_init_mmu();
 118 }
 119 extern void hash__early_init_mmu_secondary(void);
 120 extern void radix__early_init_mmu_secondary(void);
 121 static inline void early_init_mmu_secondary(void)
 122 {
 123         if (radix_enabled())
 124                 return radix__early_init_mmu_secondary();
 125         return hash__early_init_mmu_secondary();
 126 }
 127
 128 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 129                                          phys_addr_t first_memblock_size);
 130 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 131                                          phys_addr_t first_memblock_size);
 132 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 133                                               phys_addr_t first_memblock_size)
 134 {
 135         if (radix_enabled())
 136                 return radix__setup_initial_memory_limit(first_memblock_base,
 137                                                    first_memblock_size);
 138         return hash__setup_initial_memory_limit(first_memblock_base,
 139                                            first_memblock_size);
 140 }
 141 #endif /* __ASSEMBLY__ */
 142 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */