arch/powerpc/include/asm/kvm_book3s_64.h

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright SUSE Linux Products GmbH 2010
  16  *
  17  * Authors: Alexander Graf <agraf@suse.de>
  18  */
  19
  20 #ifndef __ASM_KVM_BOOK3S_64_H__
  21 #define __ASM_KVM_BOOK3S_64_H__
  22
  23 #ifdef CONFIG_KVM_BOOK3S_PR
  24 static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
  25 {
  26         preempt_disable();
  27         return &get_paca()->shadow_vcpu;
  28 }
  29
  30 static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
  31 {
  32         preempt_enable();
  33 }
  34 #endif
  35
  36 #define SPAPR_TCE_SHIFT         12
  37
  38 #ifdef CONFIG_KVM_BOOK3S_64_HV
  39 /* For now use fixed-size 16MB page table */
  40 #define HPT_ORDER       24
  41 #define HPT_NPTEG       (1ul << (HPT_ORDER - 7))        /* 128B per pteg */
  42 #define HPT_NPTE        (HPT_NPTEG << 3)                /* 8 PTEs per PTEG */
  43 #define HPT_HASH_MASK   (HPT_NPTEG - 1)
  44 #endif
  45
  46 /*
  47  * We use a lock bit in HPTE dword 0 to synchronize updates and
  48  * accesses to each HPTE, and another bit to indicate non-present
  49  * HPTEs.
  50  */
  51 #define HPTE_V_HVLOCK   0x40UL
  52
  53 static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
  54 {
  55         unsigned long tmp, old;
  56
  57         asm volatile("  ldarx   %0,0,%2\n"
  58                      "  and.    %1,%0,%3\n"
  59                      "  bne     2f\n"
  60                      "  ori     %0,%0,%4\n"
  61                      "  stdcx.  %0,0,%2\n"
  62                      "  beq+    2f\n"
  63                      "  li      %1,%3\n"
  64                      "2:        isync"
  65                      : "=&r" (tmp), "=&r" (old)
  66                      : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
  67                      : "cc", "memory");
  68         return old == 0;
  69 }
  70
  71 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
  72                                              unsigned long pte_index)
  73 {
  74         unsigned long rb, va_low;
  75
  76         rb = (v & ~0x7fUL) << 16;               /* AVA field */
  77         va_low = pte_index >> 3;
  78         if (v & HPTE_V_SECONDARY)
  79                 va_low = ~va_low;
  80         /* xor vsid from AVA */
  81         if (!(v & HPTE_V_1TB_SEG))
  82                 va_low ^= v >> 12;
  83         else
  84                 va_low ^= v >> 24;
  85         va_low &= 0x7ff;
  86         if (v & HPTE_V_LARGE) {
  87                 rb |= 1;                        /* L field */
  88                 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
  89                     (r & 0xff000)) {
  90                         /* non-16MB large page, must be 64k */
  91                         /* (masks depend on page size) */
  92                         rb |= 0x1000;           /* page encoding in LP field */
  93                         rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
  94                         rb |= (va_low & 0xfe);  /* AVAL field (P7 doesn't seem to care) */
  95                 }
  96         } else {
  97                 /* 4kB page */
  98                 rb |= (va_low & 0x7ff) << 12;   /* remaining 11b of VA */
  99         }
 100         rb |= (v >> 54) & 0x300;                /* B field */
 101         return rb;
 102 }
 103
 104 static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
 105 {
 106         /* only handle 4k, 64k and 16M pages for now */
 107         if (!(h & HPTE_V_LARGE))
 108                 return 1ul << 12;               /* 4k page */
 109         if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
 110                 return 1ul << 16;               /* 64k page */
 111         if ((l & 0xff000) == 0)
 112                 return 1ul << 24;               /* 16M page */
 113         return 0;                               /* error */
 114 }
 115
 116 static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
 117 {
 118         return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
 119 }
 120
 121 static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
 122 {
 123         unsigned int wimg = ptel & HPTE_R_WIMG;
 124
 125         /* Handle SAO */
 126         if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
 127             cpu_has_feature(CPU_FTR_ARCH_206))
 128                 wimg = HPTE_R_M;
 129
 130         if (!io_type)
 131                 return wimg == HPTE_R_M;
 132
 133         return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
 134 }
 135
 136 /* Return HPTE cache control bits corresponding to Linux pte bits */
 137 static inline unsigned long hpte_cache_bits(unsigned long pte_val)
 138 {
 139 #if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
 140         return pte_val & (HPTE_R_W | HPTE_R_I);
 141 #else
 142         return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
 143                 ((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
 144 #endif
 145 }
 146
 147 static inline void lock_rmap(unsigned long *rmap)
 148 {
 149         do {
 150                 while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
 151                         cpu_relax();
 152         } while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
 153 }
 154
 155 static inline void unlock_rmap(unsigned long *rmap)
 156 {
 157         __clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
 158 }
 159
 160 static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
 161                                    unsigned long pagesize)
 162 {
 163         unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
 164
 165         if (pagesize <= PAGE_SIZE)
 166                 return 1;
 167         return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
 168 }
 169
 170 #endif /* __ASM_KVM_BOOK3S_64_H__ */