arch/powerpc/include/asm/mmu-hash64.h

   1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
   2 #define _ASM_POWERPC_MMU_HASH64_H_
   3 /*
   4  * PowerPC64 memory management structures
   5  *
   6  * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   7  *   PPC64 rework.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <asm/asm-compat.h>
  16 #include <asm/page.h>
  17
  18 /*
  19  * This is necessary to get the definition of PGTABLE_RANGE which we
  20  * need for various slices related matters. Note that this isn't the
  21  * complete pgtable.h but only a portion of it.
  22  */
  23 #include <asm/pgtable-ppc64.h>
  24
  25 /*
  26  * Segment table
  27  */
  28
  29 #define STE_ESID_V      0x80
  30 #define STE_ESID_KS     0x20
  31 #define STE_ESID_KP     0x10
  32 #define STE_ESID_N      0x08
  33
  34 #define STE_VSID_SHIFT  12
  35
  36 /* Location of cpu0's segment table */
  37 #define STAB0_PAGE      0x8
  38 #define STAB0_OFFSET    (STAB0_PAGE << 12)
  39 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
  40
  41 #ifndef __ASSEMBLY__
  42 extern char initial_stab[];
  43 #endif /* ! __ASSEMBLY */
  44
  45 /*
  46  * SLB
  47  */
  48
  49 #define SLB_NUM_BOLTED          3
  50 #define SLB_CACHE_ENTRIES       8
  51 #define SLB_MIN_SIZE            32
  52
  53 /* Bits in the SLB ESID word */
  54 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  55
  56 /* Bits in the SLB VSID word */
  57 #define SLB_VSID_SHIFT          12
  58 #define SLB_VSID_SHIFT_1T       24
  59 #define SLB_VSID_SSIZE_SHIFT    62
  60 #define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  61 #define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  62 #define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  63 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  64 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  65 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  66 #define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  67 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  68 #define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  69 #define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  70 #define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  71 #define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  72 #define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  73 #define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  74
  75 #define SLB_VSID_KERNEL         (SLB_VSID_KP)
  76 #define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  77
  78 #define SLBIE_C                 (0x08000000)
  79 #define SLBIE_SSIZE_SHIFT       25
  80
  81 /*
  82  * Hash table
  83  */
  84
  85 #define HPTES_PER_GROUP 8
  86
  87 #define HPTE_V_SSIZE_SHIFT      62
  88 #define HPTE_V_AVPN_SHIFT       7
  89 #define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  90 #define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  91 #define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  92 #define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  93 #define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  94 #define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  95 #define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  96 #define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  97
  98 #define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
  99 #define HPTE_R_TS               ASM_CONST(0x4000000000000000)
 100 #define HPTE_R_KEY_HI           ASM_CONST(0x3000000000000000)
 101 #define HPTE_R_RPN_SHIFT        12
 102 #define HPTE_R_RPN              ASM_CONST(0x0ffffffffffff000)
 103 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
 104 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
 105 #define HPTE_R_G                ASM_CONST(0x0000000000000008)
 106 #define HPTE_R_M                ASM_CONST(0x0000000000000010)
 107 #define HPTE_R_I                ASM_CONST(0x0000000000000020)
 108 #define HPTE_R_W                ASM_CONST(0x0000000000000040)
 109 #define HPTE_R_WIMG             ASM_CONST(0x0000000000000078)
 110 #define HPTE_R_C                ASM_CONST(0x0000000000000080)
 111 #define HPTE_R_R                ASM_CONST(0x0000000000000100)
 112 #define HPTE_R_KEY_LO           ASM_CONST(0x0000000000000e00)
 113
 114 #define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
 115 #define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
 116
 117 /* Values for PP (assumes Ks=0, Kp=1) */
 118 #define PP_RWXX 0       /* Supervisor read/write, User none */
 119 #define PP_RWRX 1       /* Supervisor read/write, User read */
 120 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
 121 #define PP_RXRX 3       /* Supervisor read,       User read */
 122 #define PP_RXXX (HPTE_R_PP0 | 2)        /* Supervisor read, user none */
 123
 124 /* Fields for tlbiel instruction in architecture 2.06 */
 125 #define TLBIEL_INVAL_SEL_MASK   0xc00   /* invalidation selector */
 126 #define  TLBIEL_INVAL_PAGE      0x000   /* invalidate a single page */
 127 #define  TLBIEL_INVAL_SET_LPID  0x800   /* invalidate a set for current LPID */
 128 #define  TLBIEL_INVAL_SET       0xc00   /* invalidate a set for all LPIDs */
 129 #define TLBIEL_INVAL_SET_MASK   0xfff000        /* set number to inval. */
 130 #define TLBIEL_INVAL_SET_SHIFT  12
 131
 132 #define POWER7_TLB_SETS         128     /* # sets in POWER7 TLB */
 133
 134 #ifndef __ASSEMBLY__
 135
 136 struct hash_pte {
 137         unsigned long v;
 138         unsigned long r;
 139 };
 140
 141 extern struct hash_pte *htab_address;
 142 extern unsigned long htab_size_bytes;
 143 extern unsigned long htab_hash_mask;
 144
 145 /*
 146  * Page size definition
 147  *
 148  *    shift : is the "PAGE_SHIFT" value for that page size
 149  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 150  *            directly to a slbmte "vsid" value
 151  *    penc  : is the HPTE encoding mask for the "LP" field:
 152  *
 153  */
 154 struct mmu_psize_def
 155 {
 156         unsigned int    shift;  /* number of bits */
 157         unsigned int    penc;   /* HPTE encoding */
 158         unsigned int    tlbiel; /* tlbiel supported for that page size */
 159         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
 160         unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 161 };
 162
 163 #endif /* __ASSEMBLY__ */
 164
 165 /*
 166  * Segment sizes.
 167  * These are the values used by hardware in the B field of
 168  * SLB entries and the first dword of MMU hashtable entries.
 169  * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 170  */
 171 #define MMU_SEGSIZE_256M        0
 172 #define MMU_SEGSIZE_1T          1
 173
 174 /*
 175  * encode page number shift.
 176  * in order to fit the 78 bit va in a 64 bit variable we shift the va by
 177  * 12 bits. This enable us to address upto 76 bit va.
 178  * For hpt hash from a va we can ignore the page size bits of va and for
 179  * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
 180  * we work in all cases including 4k page size.
 181  */
 182 #define VPN_SHIFT       12
 183
 184 #ifndef __ASSEMBLY__
 185
 186 static inline int segment_shift(int ssize)
 187 {
 188         if (ssize == MMU_SEGSIZE_256M)
 189                 return SID_SHIFT;
 190         return SID_SHIFT_1T;
 191 }
 192
 193 /*
 194  * The current system page and segment sizes
 195  */
 196 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 197 extern int mmu_linear_psize;
 198 extern int mmu_virtual_psize;
 199 extern int mmu_vmalloc_psize;
 200 extern int mmu_vmemmap_psize;
 201 extern int mmu_io_psize;
 202 extern int mmu_kernel_ssize;
 203 extern int mmu_highuser_ssize;
 204 extern u16 mmu_slb_size;
 205 extern unsigned long tce_alloc_start, tce_alloc_end;
 206
 207 /*
 208  * If the processor supports 64k normal pages but not 64k cache
 209  * inhibited pages, we have to be prepared to switch processes
 210  * to use 4k pages when they create cache-inhibited mappings.
 211  * If this is the case, mmu_ci_restrictions will be set to 1.
 212  */
 213 extern int mmu_ci_restrictions;
 214
 215 /*
 216  * This computes the AVPN and B fields of the first dword of a HPTE,
 217  * for use when we want to match an existing PTE.  The bottom 7 bits
 218  * of the returned value are zero.
 219  */
 220 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
 221                                              int ssize)
 222 {
 223         unsigned long v;
 224         /*
 225          * The AVA field omits the low-order 23 bits of the 78 bits VA.
 226          * These bits are not needed in the PTE, because the
 227          * low-order b of these bits are part of the byte offset
 228          * into the virtual page and, if b < 23, the high-order
 229          * 23-b of these bits are always used in selecting the
 230          * PTEGs to be searched
 231          */
 232         v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
 233         v <<= HPTE_V_AVPN_SHIFT;
 234         v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
 235         return v;
 236 }
 237
 238 /*
 239  * This function sets the AVPN and L fields of the HPTE  appropriately
 240  * for the page size
 241  */
 242 static inline unsigned long hpte_encode_v(unsigned long vpn,
 243                                           int psize, int ssize)
 244 {
 245         unsigned long v;
 246         v = hpte_encode_avpn(vpn, psize, ssize);
 247         if (psize != MMU_PAGE_4K)
 248                 v |= HPTE_V_LARGE;
 249         return v;
 250 }
 251
 252 /*
 253  * This function sets the ARPN, and LP fields of the HPTE appropriately
 254  * for the page size. We assume the pa is already "clean" that is properly
 255  * aligned for the requested page size
 256  */
 257 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
 258 {
 259         unsigned long r;
 260
 261         /* A 4K page needs no special encoding */
 262         if (psize == MMU_PAGE_4K)
 263                 return pa & HPTE_R_RPN;
 264         else {
 265                 unsigned int penc = mmu_psize_defs[psize].penc;
 266                 unsigned int shift = mmu_psize_defs[psize].shift;
 267                 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
 268         }
 269         return r;
 270 }
 271
 272 /*
 273  * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
 274  */
 275 static inline unsigned long hpt_vpn(unsigned long ea,
 276                                     unsigned long vsid, int ssize)
 277 {
 278         unsigned long mask;
 279         int s_shift = segment_shift(ssize);
 280
 281         mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
 282         return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
 283 }
 284
 285 /*
 286  * This hashes a virtual address
 287  */
 288 static inline unsigned long hpt_hash(unsigned long vpn,
 289                                      unsigned int shift, int ssize)
 290 {
 291         int mask;
 292         unsigned long hash, vsid;
 293
 294         /* VPN_SHIFT can be atmost 12 */
 295         if (ssize == MMU_SEGSIZE_256M) {
 296                 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
 297                 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
 298                         ((vpn & mask) >> (shift - VPN_SHIFT));
 299         } else {
 300                 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
 301                 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
 302                 hash = vsid ^ (vsid << 25) ^
 303                         ((vpn & mask) >> (shift - VPN_SHIFT)) ;
 304         }
 305         return hash & 0x7fffffffffUL;
 306 }
 307
 308 extern int __hash_page_4K(unsigned long ea, unsigned long access,
 309                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 310                           unsigned int local, int ssize, int subpage_prot);
 311 extern int __hash_page_64K(unsigned long ea, unsigned long access,
 312                            unsigned long vsid, pte_t *ptep, unsigned long trap,
 313                            unsigned int local, int ssize);
 314 struct mm_struct;
 315 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
 316 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
 317 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 318                      pte_t *ptep, unsigned long trap, int local, int ssize,
 319                      unsigned int shift, unsigned int mmu_psize);
 320 extern void hash_failure_debug(unsigned long ea, unsigned long access,
 321                                unsigned long vsid, unsigned long trap,
 322                                int ssize, int psize, unsigned long pte);
 323 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 324                              unsigned long pstart, unsigned long prot,
 325                              int psize, int ssize);
 326 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
 327 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 328
 329 extern void hpte_init_native(void);
 330 extern void hpte_init_lpar(void);
 331 extern void hpte_init_beat(void);
 332 extern void hpte_init_beat_v3(void);
 333
 334 extern void stabs_alloc(void);
 335 extern void slb_initialize(void);
 336 extern void slb_flush_and_rebolt(void);
 337 extern void stab_initialize(unsigned long stab);
 338
 339 extern void slb_vmalloc_update(void);
 340 extern void slb_set_size(u16 size);
 341 #endif /* __ASSEMBLY__ */
 342
 343 /*
 344  * VSID allocation (256MB segment)
 345  *
 346  * We first generate a 38-bit "proto-VSID".  For kernel addresses this
 347  * is equal to the ESID | 1 << 37, for user addresses it is:
 348  *      (context << USER_ESID_BITS) | (esid & ((1U << USER_ESID_BITS) - 1)
 349  *
 350  * This splits the proto-VSID into the below range
 351  *  0 - (2^(CONTEXT_BITS + USER_ESID_BITS) - 1) : User proto-VSID range
 352  *  2^(CONTEXT_BITS + USER_ESID_BITS) - 2^(VSID_BITS) : Kernel proto-VSID range
 353  *
 354  * We also have CONTEXT_BITS + USER_ESID_BITS = VSID_BITS - 1
 355  * That is, we assign half of the space to user processes and half
 356  * to the kernel.
 357  *
 358  * The proto-VSIDs are then scrambled into real VSIDs with the
 359  * multiplicative hash:
 360  *
 361  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 362  *
 363  * VSID_MULTIPLIER is prime, so in particular it is
 364  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 365  * Because the modulus is 2^n-1 we can compute it efficiently without
 366  * a divide or extra multiply (see below).
 367  *
 368  * This scheme has several advantages over older methods:
 369  *
 370  *      - We have VSIDs allocated for every kernel address
 371  * (i.e. everything above 0xC000000000000000), except the very top
 372  * segment, which simplifies several things.
 373  *
 374  *      - We allow for USER_ESID_BITS significant bits of ESID and
 375  * CONTEXT_BITS  bits of context for user addresses.
 376  *  i.e. 64T (46 bits) of address space for up to half a million contexts.
 377  *
 378  *      - The scramble function gives robust scattering in the hash
 379  * table (at least based on some initial results).  The previous
 380  * method was more susceptible to pathological cases giving excessive
 381  * hash collisions.
 382  */
 383
 384 /*
 385  * This should be computed such that protovosid * vsid_mulitplier
 386  * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
 387  */
 388 #define VSID_MULTIPLIER_256M    ASM_CONST(12538073)     /* 24-bit prime */
 389 #define VSID_BITS_256M          38
 390 #define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
 391
 392 #define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
 393 #define VSID_BITS_1T            26
 394 #define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
 395
 396 #define CONTEXT_BITS            19
 397 #define USER_ESID_BITS          18
 398 #define USER_ESID_BITS_1T       6
 399
 400 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
 401
 402 /*
 403  * This macro generates asm code to compute the VSID scramble
 404  * function.  Used in slb_allocate() and do_stab_bolted.  The function
 405  * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 406  *
 407  *      rt = register continaing the proto-VSID and into which the
 408  *              VSID will be stored
 409  *      rx = scratch register (clobbered)
 410  *
 411  *      - rt and rx must be different registers
 412  *      - The answer will end up in the low VSID_BITS bits of rt.  The higher
 413  *        bits may contain other garbage, so you may need to mask the
 414  *        result.
 415  */
 416 #define ASM_VSID_SCRAMBLE(rt, rx, size)                                 \
 417         lis     rx,VSID_MULTIPLIER_##size@h;                            \
 418         ori     rx,rx,VSID_MULTIPLIER_##size@l;                         \
 419         mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 420                                                                         \
 421         srdi    rx,rt,VSID_BITS_##size;                                 \
 422         clrldi  rt,rt,(64-VSID_BITS_##size);                            \
 423         add     rt,rt,rx;               /* add high and low bits */     \
 424         /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 425          * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 426          * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 427          * the bit clear, r3 already has the answer we want, if it      \
 428          * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 429          * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 430         addi    rx,rt,1;                                                \
 431         srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
 432         add     rt,rt,rx
 433
 434 /* 4 bits per slice and we have one slice per 1TB */
 435 #define SLICE_ARRAY_SIZE  (PGTABLE_RANGE >> 41)
 436
 437 #ifndef __ASSEMBLY__
 438
 439 #ifdef CONFIG_PPC_SUBPAGE_PROT
 440 /*
 441  * For the sub-page protection option, we extend the PGD with one of
 442  * these.  Basically we have a 3-level tree, with the top level being
 443  * the protptrs array.  To optimize speed and memory consumption when
 444  * only addresses < 4GB are being protected, pointers to the first
 445  * four pages of sub-page protection words are stored in the low_prot
 446  * array.
 447  * Each page of sub-page protection words protects 1GB (4 bytes
 448  * protects 64k).  For the 3-level tree, each page of pointers then
 449  * protects 8TB.
 450  */
 451 struct subpage_prot_table {
 452         unsigned long maxaddr;  /* only addresses < this are protected */
 453         unsigned int **protptrs[2];
 454         unsigned int *low_prot[4];
 455 };
 456
 457 #define SBP_L1_BITS             (PAGE_SHIFT - 2)
 458 #define SBP_L2_BITS             (PAGE_SHIFT - 3)
 459 #define SBP_L1_COUNT            (1 << SBP_L1_BITS)
 460 #define SBP_L2_COUNT            (1 << SBP_L2_BITS)
 461 #define SBP_L2_SHIFT            (PAGE_SHIFT + SBP_L1_BITS)
 462 #define SBP_L3_SHIFT            (SBP_L2_SHIFT + SBP_L2_BITS)
 463
 464 extern void subpage_prot_free(struct mm_struct *mm);
 465 extern void subpage_prot_init_new_context(struct mm_struct *mm);
 466 #else
 467 static inline void subpage_prot_free(struct mm_struct *mm) {}
 468 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
 469 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 470
 471 typedef unsigned long mm_context_id_t;
 472 struct spinlock;
 473
 474 typedef struct {
 475         mm_context_id_t id;
 476         u16 user_psize;         /* page size index */
 477
 478 #ifdef CONFIG_PPC_MM_SLICES
 479         u64 low_slices_psize;   /* SLB page size encodings */
 480         unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
 481 #else
 482         u16 sllp;               /* SLB page size encoding */
 483 #endif
 484         unsigned long vdso_base;
 485 #ifdef CONFIG_PPC_SUBPAGE_PROT
 486         struct subpage_prot_table spt;
 487 #endif /* CONFIG_PPC_SUBPAGE_PROT */
 488 #ifdef CONFIG_PPC_ICSWX
 489         struct spinlock *cop_lockp; /* guard acop and cop_pid */
 490         unsigned long acop;     /* mask of enabled coprocessor types */
 491         unsigned int cop_pid;   /* pid value used with coprocessors */
 492 #endif /* CONFIG_PPC_ICSWX */
 493 } mm_context_t;
 494
 495
 496 #if 0
 497 /*
 498  * The code below is equivalent to this function for arguments
 499  * < 2^VSID_BITS, which is all this should ever be called
 500  * with.  However gcc is not clever enough to compute the
 501  * modulus (2^n-1) without a second multiply.
 502  */
 503 #define vsid_scramble(protovsid, size) \
 504         ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
 505
 506 #else /* 1 */
 507 #define vsid_scramble(protovsid, size) \
 508         ({                                                               \
 509                 unsigned long x;                                         \
 510                 x = (protovsid) * VSID_MULTIPLIER_##size;                \
 511                 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
 512                 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
 513         })
 514 #endif /* 1 */
 515
 516 /*
 517  * This is only valid for addresses >= PAGE_OFFSET
 518  * The proto-VSID space is divided into two class
 519  * User:   0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
 520  * kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
 521  *
 522  * With KERNEL_START at 0xc000000000000000, the proto vsid for
 523  * the kernel ends up with 0xc00000000 (36 bits). With 64TB
 524  * support we need to have kernel proto-VSID in the
 525  * [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
 526  */
 527 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 528 {
 529         unsigned long proto_vsid;
 530         /*
 531          * We need to make sure proto_vsid for the kernel is
 532          * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
 533          */
 534         if (ssize == MMU_SEGSIZE_256M) {
 535                 proto_vsid = ea >> SID_SHIFT;
 536                 proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
 537                 return vsid_scramble(proto_vsid, 256M);
 538         }
 539         proto_vsid = ea >> SID_SHIFT_1T;
 540         proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
 541         return vsid_scramble(proto_vsid, 1T);
 542 }
 543
 544 /* Returns the segment size indicator for a user address */
 545 static inline int user_segment_size(unsigned long addr)
 546 {
 547         /* Use 1T segments if possible for addresses >= 1T */
 548         if (addr >= (1UL << SID_SHIFT_1T))
 549                 return mmu_highuser_ssize;
 550         return MMU_SEGSIZE_256M;
 551 }
 552
 553 /* This is only valid for user addresses (which are below 2^44) */
 554 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
 555                                      int ssize)
 556 {
 557         if (ssize == MMU_SEGSIZE_256M)
 558                 return vsid_scramble((context << USER_ESID_BITS)
 559                                      | (ea >> SID_SHIFT), 256M);
 560         return vsid_scramble((context << USER_ESID_BITS_1T)
 561                              | (ea >> SID_SHIFT_1T), 1T);
 562 }
 563
 564 #endif /* __ASSEMBLY__ */
 565
 566 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */