2 * PowerNV OPAL definitions.
4 * Copyright 2011 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
19 * WARNING: The current implementation requires each entry
20 * to represent a block that is 4k aligned *and* each block
21 * size except the last one in the list to be as well.
23 struct opal_sg_entry
{
32 struct opal_sg_entry entry
[];
35 /* We calculate number of sg entries based on PAGE_SIZE */
36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
38 #endif /* __ASSEMBLY__ */
40 /****** OPAL APIs ******/
43 #define OPAL_SUCCESS 0
44 #define OPAL_PARAMETER -1
46 #define OPAL_PARTIAL -3
47 #define OPAL_CONSTRAINED -4
48 #define OPAL_CLOSED -5
49 #define OPAL_HARDWARE -6
50 #define OPAL_UNSUPPORTED -7
51 #define OPAL_PERMISSION -8
52 #define OPAL_NO_MEM -9
53 #define OPAL_RESOURCE -10
54 #define OPAL_INTERNAL_ERROR -11
55 #define OPAL_BUSY_EVENT -12
56 #define OPAL_HARDWARE_FROZEN -13
57 #define OPAL_WRONG_STATE -14
58 #define OPAL_ASYNC_COMPLETION -15
59 #define OPAL_I2C_TIMEOUT -17
60 #define OPAL_I2C_INVALID_CMD -18
61 #define OPAL_I2C_LBUS_PARITY -19
62 #define OPAL_I2C_BKEND_OVERRUN -20
63 #define OPAL_I2C_BKEND_ACCESS -21
64 #define OPAL_I2C_ARBT_LOST -22
65 #define OPAL_I2C_NACK_RCVD -23
66 #define OPAL_I2C_STOP_ERR -24
68 /* API Tokens (in r0) */
69 #define OPAL_INVALID_CALL -1
70 #define OPAL_CONSOLE_WRITE 1
71 #define OPAL_CONSOLE_READ 2
72 #define OPAL_RTC_READ 3
73 #define OPAL_RTC_WRITE 4
74 #define OPAL_CEC_POWER_DOWN 5
75 #define OPAL_CEC_REBOOT 6
76 #define OPAL_READ_NVRAM 7
77 #define OPAL_WRITE_NVRAM 8
78 #define OPAL_HANDLE_INTERRUPT 9
79 #define OPAL_POLL_EVENTS 10
80 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
81 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
82 #define OPAL_PCI_CONFIG_READ_BYTE 13
83 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
84 #define OPAL_PCI_CONFIG_READ_WORD 15
85 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
86 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
87 #define OPAL_PCI_CONFIG_WRITE_WORD 18
88 #define OPAL_SET_XIVE 19
89 #define OPAL_GET_XIVE 20
90 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
91 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
92 #define OPAL_PCI_EEH_FREEZE_STATUS 23
93 #define OPAL_PCI_SHPC 24
94 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
95 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
96 #define OPAL_PCI_PHB_MMIO_ENABLE 27
97 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
98 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
99 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
100 #define OPAL_PCI_SET_PE 31
101 #define OPAL_PCI_SET_PELTV 32
102 #define OPAL_PCI_SET_MVE 33
103 #define OPAL_PCI_SET_MVE_ENABLE 34
104 #define OPAL_PCI_GET_XIVE_REISSUE 35
105 #define OPAL_PCI_SET_XIVE_REISSUE 36
106 #define OPAL_PCI_SET_XIVE_PE 37
107 #define OPAL_GET_XIVE_SOURCE 38
108 #define OPAL_GET_MSI_32 39
109 #define OPAL_GET_MSI_64 40
110 #define OPAL_START_CPU 41
111 #define OPAL_QUERY_CPU_STATUS 42
112 #define OPAL_WRITE_OPPANEL 43
113 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
114 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
115 #define OPAL_PCI_RESET 49
116 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
117 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
118 #define OPAL_PCI_FENCE_PHB 52
119 #define OPAL_PCI_REINIT 53
120 #define OPAL_PCI_MASK_PE_ERROR 54
121 #define OPAL_SET_SLOT_LED_STATUS 55
122 #define OPAL_GET_EPOW_STATUS 56
123 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
124 #define OPAL_RESERVED1 58
125 #define OPAL_RESERVED2 59
126 #define OPAL_PCI_NEXT_ERROR 60
127 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
128 #define OPAL_PCI_POLL 62
129 #define OPAL_PCI_MSI_EOI 63
130 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
131 #define OPAL_XSCOM_READ 65
132 #define OPAL_XSCOM_WRITE 66
133 #define OPAL_LPC_READ 67
134 #define OPAL_LPC_WRITE 68
135 #define OPAL_RETURN_CPU 69
136 #define OPAL_REINIT_CPUS 70
137 #define OPAL_ELOG_READ 71
138 #define OPAL_ELOG_WRITE 72
139 #define OPAL_ELOG_ACK 73
140 #define OPAL_ELOG_RESEND 74
141 #define OPAL_ELOG_SIZE 75
142 #define OPAL_FLASH_VALIDATE 76
143 #define OPAL_FLASH_MANAGE 77
144 #define OPAL_FLASH_UPDATE 78
145 #define OPAL_RESYNC_TIMEBASE 79
146 #define OPAL_CHECK_TOKEN 80
147 #define OPAL_DUMP_INIT 81
148 #define OPAL_DUMP_INFO 82
149 #define OPAL_DUMP_READ 83
150 #define OPAL_DUMP_ACK 84
151 #define OPAL_GET_MSG 85
152 #define OPAL_CHECK_ASYNC_COMPLETION 86
153 #define OPAL_SYNC_HOST_REBOOT 87
154 #define OPAL_SENSOR_READ 88
155 #define OPAL_GET_PARAM 89
156 #define OPAL_SET_PARAM 90
157 #define OPAL_DUMP_RESEND 91
158 #define OPAL_PCI_SET_PHB_CXL_MODE 93
159 #define OPAL_DUMP_INFO2 94
160 #define OPAL_PCI_ERR_INJECT 96
161 #define OPAL_PCI_EEH_FREEZE_SET 97
162 #define OPAL_HANDLE_HMI 98
163 #define OPAL_CONFIG_CPU_IDLE_STATE 99
164 #define OPAL_REGISTER_DUMP_REGION 101
165 #define OPAL_UNREGISTER_DUMP_REGION 102
166 #define OPAL_WRITE_TPO 103
167 #define OPAL_READ_TPO 104
168 #define OPAL_IPMI_SEND 107
169 #define OPAL_IPMI_RECV 108
170 #define OPAL_I2C_REQUEST 109
172 /* Device tree flags */
174 /* Flags set in power-mgmt nodes in device tree if
175 * respective idle states are supported in the platform.
177 #define OPAL_PM_NAP_ENABLED 0x00010000
178 #define OPAL_PM_SLEEP_ENABLED 0x00020000
179 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000
183 #include <linux/notifier.h>
186 enum OpalVendorApiTokens
{
187 OPAL_START_VENDOR_API_RANGE
= 1000, OPAL_END_VENDOR_API_RANGE
= 1999
190 enum OpalFreezeState
{
191 OPAL_EEH_STOPPED_NOT_FROZEN
= 0,
192 OPAL_EEH_STOPPED_MMIO_FREEZE
= 1,
193 OPAL_EEH_STOPPED_DMA_FREEZE
= 2,
194 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE
= 3,
195 OPAL_EEH_STOPPED_RESET
= 4,
196 OPAL_EEH_STOPPED_TEMP_UNAVAIL
= 5,
197 OPAL_EEH_STOPPED_PERM_UNAVAIL
= 6
200 enum OpalEehFreezeActionToken
{
201 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO
= 1,
202 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA
= 2,
203 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
= 3,
205 OPAL_EEH_ACTION_SET_FREEZE_MMIO
= 1,
206 OPAL_EEH_ACTION_SET_FREEZE_DMA
= 2,
207 OPAL_EEH_ACTION_SET_FREEZE_ALL
= 3
210 enum OpalPciStatusToken
{
211 OPAL_EEH_NO_ERROR
= 0,
212 OPAL_EEH_IOC_ERROR
= 1,
213 OPAL_EEH_PHB_ERROR
= 2,
214 OPAL_EEH_PE_ERROR
= 3,
215 OPAL_EEH_PE_MMIO_ERROR
= 4,
216 OPAL_EEH_PE_DMA_ERROR
= 5
219 enum OpalPciErrorSeverity
{
220 OPAL_EEH_SEV_NO_ERROR
= 0,
221 OPAL_EEH_SEV_IOC_DEAD
= 1,
222 OPAL_EEH_SEV_PHB_DEAD
= 2,
223 OPAL_EEH_SEV_PHB_FENCED
= 3,
224 OPAL_EEH_SEV_PE_ER
= 4,
228 enum OpalErrinjectType
{
229 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR
= 0,
230 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64
= 1,
233 enum OpalErrinjectFunc
{
234 /* IOA bus specific errors */
235 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR
= 0,
236 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA
= 1,
237 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR
= 2,
238 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA
= 3,
239 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR
= 4,
240 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA
= 5,
241 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR
= 6,
242 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA
= 7,
243 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR
= 8,
244 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA
= 9,
245 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR
= 10,
246 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA
= 11,
247 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR
= 12,
248 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA
= 13,
249 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER
= 14,
250 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET
= 15,
251 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR
= 16,
252 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA
= 17,
253 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER
= 18,
254 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET
= 19,
257 enum OpalShpcAction
{
258 OPAL_SHPC_GET_LINK_STATE
= 0,
259 OPAL_SHPC_GET_SLOT_STATE
= 1
262 enum OpalShpcLinkState
{
263 OPAL_SHPC_LINK_DOWN
= 0,
264 OPAL_SHPC_LINK_UP
= 1
267 enum OpalMmioWindowType
{
268 OPAL_M32_WINDOW_TYPE
= 1,
269 OPAL_M64_WINDOW_TYPE
= 2,
270 OPAL_IO_WINDOW_TYPE
= 3
273 enum OpalShpcSlotState
{
274 OPAL_SHPC_DEV_NOT_PRESENT
= 0,
275 OPAL_SHPC_DEV_PRESENT
= 1
278 enum OpalExceptionHandler
{
279 OPAL_MACHINE_CHECK_HANDLER
= 1,
280 OPAL_HYPERVISOR_MAINTENANCE_HANDLER
= 2,
281 OPAL_SOFTPATCH_HANDLER
= 3
284 enum OpalPendingState
{
285 OPAL_EVENT_OPAL_INTERNAL
= 0x1,
286 OPAL_EVENT_NVRAM
= 0x2,
287 OPAL_EVENT_RTC
= 0x4,
288 OPAL_EVENT_CONSOLE_OUTPUT
= 0x8,
289 OPAL_EVENT_CONSOLE_INPUT
= 0x10,
290 OPAL_EVENT_ERROR_LOG_AVAIL
= 0x20,
291 OPAL_EVENT_ERROR_LOG
= 0x40,
292 OPAL_EVENT_EPOW
= 0x80,
293 OPAL_EVENT_LED_STATUS
= 0x100,
294 OPAL_EVENT_PCI_ERROR
= 0x200,
295 OPAL_EVENT_DUMP_AVAIL
= 0x400,
296 OPAL_EVENT_MSG_PENDING
= 0x800,
299 enum OpalMessageType
{
300 OPAL_MSG_ASYNC_COMP
= 0, /* params[0] = token, params[1] = rc,
301 * additional params function-specific
310 enum OpalThreadStatus
{
311 OPAL_THREAD_INACTIVE
= 0x0,
312 OPAL_THREAD_STARTED
= 0x1,
313 OPAL_THREAD_UNAVAILABLE
= 0x2 /* opal-v3 */
316 enum OpalPciBusCompare
{
317 OpalPciBusAny
= 0, /* Any bus number match */
318 OpalPciBus3Bits
= 2, /* Match top 3 bits of bus number */
319 OpalPciBus4Bits
= 3, /* Match top 4 bits of bus number */
320 OpalPciBus5Bits
= 4, /* Match top 5 bits of bus number */
321 OpalPciBus6Bits
= 5, /* Match top 6 bits of bus number */
322 OpalPciBus7Bits
= 6, /* Match top 7 bits of bus number */
323 OpalPciBusAll
= 7, /* Match bus number exactly */
326 enum OpalDeviceCompare
{
327 OPAL_IGNORE_RID_DEVICE_NUMBER
= 0,
328 OPAL_COMPARE_RID_DEVICE_NUMBER
= 1
331 enum OpalFuncCompare
{
332 OPAL_IGNORE_RID_FUNCTION_NUMBER
= 0,
333 OPAL_COMPARE_RID_FUNCTION_NUMBER
= 1
341 enum OpalPeltvAction
{
342 OPAL_REMOVE_PE_FROM_DOMAIN
= 0,
343 OPAL_ADD_PE_TO_DOMAIN
= 1
346 enum OpalMveEnableAction
{
347 OPAL_DISABLE_MVE
= 0,
351 enum OpalM64EnableAction
{
352 OPAL_DISABLE_M64
= 0,
353 OPAL_ENABLE_M64_SPLIT
= 1,
354 OPAL_ENABLE_M64_NON_SPLIT
= 2
357 enum OpalPciResetScope
{
358 OPAL_RESET_PHB_COMPLETE
= 1,
359 OPAL_RESET_PCI_LINK
= 2,
360 OPAL_RESET_PHB_ERROR
= 3,
361 OPAL_RESET_PCI_HOT
= 4,
362 OPAL_RESET_PCI_FUNDAMENTAL
= 5,
363 OPAL_RESET_PCI_IODA_TABLE
= 6
366 enum OpalPciReinitScope
{
367 OPAL_REINIT_PCI_DEV
= 1000
370 enum OpalPciResetState
{
371 OPAL_DEASSERT_RESET
= 0,
372 OPAL_ASSERT_RESET
= 1
375 enum OpalPciMaskAction
{
376 OPAL_UNMASK_ERROR_TYPE
= 0,
377 OPAL_MASK_ERROR_TYPE
= 1
380 enum OpalSlotLedType
{
381 OPAL_SLOT_LED_ID_TYPE
= 0,
382 OPAL_SLOT_LED_FAULT_TYPE
= 1
386 OPAL_TURN_OFF_LED
= 0,
387 OPAL_TURN_ON_LED
= 1,
388 OPAL_QUERY_LED_STATE_AFTER_BUSY
= 2
391 enum OpalEpowStatus
{
394 OPAL_EPOW_OVER_AMBIENT_TEMP
= 2,
395 OPAL_EPOW_OVER_INTERNAL_TEMP
= 3
399 * Address cycle types for LPC accesses. These also correspond
400 * to the content of the first cell of the "reg" property for
401 * device nodes on the LPC bus
403 enum OpalLPCAddressType
{
409 /* System parameter permission */
410 enum OpalSysparamPerm
{
411 OPAL_SYSPARAM_READ
= 0x1,
412 OPAL_SYSPARAM_WRITE
= 0x2,
413 OPAL_SYSPARAM_RW
= (OPAL_SYSPARAM_READ
| OPAL_SYSPARAM_WRITE
),
423 OPAL_IPMI_MSG_FORMAT_VERSION_1
= 1,
426 struct opal_ipmi_msg
{
433 /* FSP memory errors handling */
434 enum OpalMemErr_Version
{
438 enum OpalMemErrType
{
439 OPAL_MEM_ERR_TYPE_RESILIENCE
= 0,
440 OPAL_MEM_ERR_TYPE_DYN_DALLOC
,
441 OPAL_MEM_ERR_TYPE_SCRUB
,
444 /* Memory Reilience error type */
445 enum OpalMemErr_ResilErrType
{
446 OPAL_MEM_RESILIENCE_CE
= 0,
447 OPAL_MEM_RESILIENCE_UE
,
448 OPAL_MEM_RESILIENCE_UE_SCRUB
,
451 /* Dynamic Memory Deallocation type */
452 enum OpalMemErr_DynErrType
{
453 OPAL_MEM_DYNAMIC_DEALLOC
= 0,
456 /* OpalMemoryErrorData->flags */
457 #define OPAL_MEM_CORRECTED_ERROR 0x0001
458 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
459 #define OPAL_MEM_ACK_REQUIRED 0x8000
461 struct OpalMemoryErrorData
{
462 enum OpalMemErr_Version version
:8; /* 0x00 */
463 enum OpalMemErrType type
:8; /* 0x01 */
464 __be16 flags
; /* 0x02 */
465 uint8_t reserved_1
[4]; /* 0x04 */
468 /* Memory Resilience corrected/uncorrected error info */
470 enum OpalMemErr_ResilErrType resil_err_type
:8;
471 uint8_t reserved_1
[7];
472 __be64 physical_address_start
;
473 __be64 physical_address_end
;
475 /* Dynamic memory deallocation error info */
477 enum OpalMemErr_DynErrType dyn_err_type
:8;
478 uint8_t reserved_1
[7];
479 __be64 physical_address_start
;
480 __be64 physical_address_end
;
485 /* HMI interrupt event */
486 enum OpalHMI_Version
{
490 enum OpalHMI_Severity
{
491 OpalHMI_SEV_NO_ERROR
= 0,
492 OpalHMI_SEV_WARNING
= 1,
493 OpalHMI_SEV_ERROR_SYNC
= 2,
494 OpalHMI_SEV_FATAL
= 3,
497 enum OpalHMI_Disposition
{
498 OpalHMI_DISPOSITION_RECOVERED
= 0,
499 OpalHMI_DISPOSITION_NOT_RECOVERED
= 1,
502 enum OpalHMI_ErrType
{
503 OpalHMI_ERROR_MALFUNC_ALERT
= 0,
504 OpalHMI_ERROR_PROC_RECOV_DONE
,
505 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN
,
506 OpalHMI_ERROR_PROC_RECOV_MASKED
,
508 OpalHMI_ERROR_TFMR_PARITY
,
509 OpalHMI_ERROR_HA_OVERFLOW_WARN
,
510 OpalHMI_ERROR_XSCOM_FAIL
,
511 OpalHMI_ERROR_XSCOM_DONE
,
512 OpalHMI_ERROR_SCOM_FIR
,
513 OpalHMI_ERROR_DEBUG_TRIG_FIR
,
514 OpalHMI_ERROR_HYP_RESOURCE
,
517 struct OpalHMIEvent
{
518 uint8_t version
; /* 0x00 */
519 uint8_t severity
; /* 0x01 */
520 uint8_t type
; /* 0x02 */
521 uint8_t disposition
; /* 0x03 */
522 uint8_t reserved_1
[4]; /* 0x04 */
525 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
530 OPAL_P7IOC_DIAG_TYPE_NONE
= 0,
531 OPAL_P7IOC_DIAG_TYPE_RGC
= 1,
532 OPAL_P7IOC_DIAG_TYPE_BI
= 2,
533 OPAL_P7IOC_DIAG_TYPE_CI
= 3,
534 OPAL_P7IOC_DIAG_TYPE_MISC
= 4,
535 OPAL_P7IOC_DIAG_TYPE_I2C
= 5,
536 OPAL_P7IOC_DIAG_TYPE_LAST
= 6
539 struct OpalIoP7IOCErrorData
{
557 struct OpalIoP7IOCRgcErrorData
{
558 __be64 rgcStatus
; /* 3E1C10 */
559 __be64 rgcLdcp
; /* 3E1C18 */
561 struct OpalIoP7IOCBiErrorData
{
562 __be64 biLdcp0
; /* 3C0100, 3C0118 */
563 __be64 biLdcp1
; /* 3C0108, 3C0120 */
564 __be64 biLdcp2
; /* 3C0110, 3C0128 */
565 __be64 biFenceStatus
; /* 3C0130, 3C0130 */
567 u8 biDownbound
; /* BI Downbound or Upbound */
569 struct OpalIoP7IOCCiErrorData
{
570 __be64 ciPortStatus
; /* 3Dn008 */
571 __be64 ciPortLdcp
; /* 3Dn010 */
573 u8 ciPort
; /* Index of CI port: 0/1 */
579 * This structure defines the overlay which will be used to store PHB error
583 OPAL_PHB_ERROR_DATA_VERSION_1
= 1,
587 OPAL_PHB_ERROR_DATA_TYPE_P7IOC
= 1,
588 OPAL_PHB_ERROR_DATA_TYPE_PHB3
= 2
592 OPAL_P7IOC_NUM_PEST_REGS
= 128,
593 OPAL_PHB3_NUM_PEST_REGS
= 256
596 struct OpalIoPhbErrorCommon
{
602 struct OpalIoP7IOCPhbErrorData
{
603 struct OpalIoPhbErrorCommon common
;
608 __be32 portStatusReg
;
609 __be32 rootCmplxStatus
;
610 __be32 busAgentStatus
;
620 __be32 rootErrorStatus
;
621 __be32 uncorrErrorStatus
;
622 __be32 corrErrorStatus
;
631 // Record data about the call to allocate a buffer.
635 //P7IOC MMIO Error Regs
636 __be64 p7iocPlssr
; // n120
637 __be64 p7iocCsr
; // n110
638 __be64 lemFir
; // nC00
639 __be64 lemErrorMask
; // nC18
640 __be64 lemWOF
; // nC40
641 __be64 phbErrorStatus
; // nC80
642 __be64 phbFirstErrorStatus
; // nC88
643 __be64 phbErrorLog0
; // nCC0
644 __be64 phbErrorLog1
; // nCC8
645 __be64 mmioErrorStatus
; // nD00
646 __be64 mmioFirstErrorStatus
; // nD08
647 __be64 mmioErrorLog0
; // nD40
648 __be64 mmioErrorLog1
; // nD48
649 __be64 dma0ErrorStatus
; // nD80
650 __be64 dma0FirstErrorStatus
; // nD88
651 __be64 dma0ErrorLog0
; // nDC0
652 __be64 dma0ErrorLog1
; // nDC8
653 __be64 dma1ErrorStatus
; // nE00
654 __be64 dma1FirstErrorStatus
; // nE08
655 __be64 dma1ErrorLog0
; // nE40
656 __be64 dma1ErrorLog1
; // nE48
657 __be64 pestA
[OPAL_P7IOC_NUM_PEST_REGS
];
658 __be64 pestB
[OPAL_P7IOC_NUM_PEST_REGS
];
661 struct OpalIoPhb3ErrorData
{
662 struct OpalIoPhbErrorCommon common
;
667 __be32 portStatusReg
;
668 __be32 rootCmplxStatus
;
669 __be32 busAgentStatus
;
679 __be32 rootErrorStatus
;
680 __be32 uncorrErrorStatus
;
681 __be32 corrErrorStatus
;
690 /* Record data about the call to allocate a buffer */
694 __be64 nFir
; /* 000 */
695 __be64 nFirMask
; /* 003 */
696 __be64 nFirWOF
; /* 008 */
698 /* PHB3 MMIO Error Regs */
699 __be64 phbPlssr
; /* 120 */
700 __be64 phbCsr
; /* 110 */
701 __be64 lemFir
; /* C00 */
702 __be64 lemErrorMask
; /* C18 */
703 __be64 lemWOF
; /* C40 */
704 __be64 phbErrorStatus
; /* C80 */
705 __be64 phbFirstErrorStatus
; /* C88 */
706 __be64 phbErrorLog0
; /* CC0 */
707 __be64 phbErrorLog1
; /* CC8 */
708 __be64 mmioErrorStatus
; /* D00 */
709 __be64 mmioFirstErrorStatus
; /* D08 */
710 __be64 mmioErrorLog0
; /* D40 */
711 __be64 mmioErrorLog1
; /* D48 */
712 __be64 dma0ErrorStatus
; /* D80 */
713 __be64 dma0FirstErrorStatus
; /* D88 */
714 __be64 dma0ErrorLog0
; /* DC0 */
715 __be64 dma0ErrorLog1
; /* DC8 */
716 __be64 dma1ErrorStatus
; /* E00 */
717 __be64 dma1FirstErrorStatus
; /* E08 */
718 __be64 dma1ErrorLog0
; /* E40 */
719 __be64 dma1ErrorLog1
; /* E48 */
720 __be64 pestA
[OPAL_PHB3_NUM_PEST_REGS
];
721 __be64 pestB
[OPAL_PHB3_NUM_PEST_REGS
];
725 OPAL_REINIT_CPUS_HILE_BE
= (1 << 0),
726 OPAL_REINIT_CPUS_HILE_LE
= (1 << 1),
729 typedef struct oppanel_line
{
734 /* OPAL I2C request */
735 struct opal_i2c_request
{
737 #define OPAL_I2C_RAW_READ 0
738 #define OPAL_I2C_RAW_WRITE 1
739 #define OPAL_I2C_SM_READ 2
740 #define OPAL_I2C_SM_WRITE 3
742 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
743 uint8_t subaddr_sz
; /* Max 4 */
745 __be16 addr
; /* 7 or 10 bit address */
747 __be32 subaddr
; /* Sub-address if any */
748 __be32 size
; /* Data size */
749 __be64 buffer_ra
; /* Buffer real address */
752 /* /sys/firmware/opal */
753 extern struct kobject
*opal_kobj
;
756 extern struct device_node
*opal_node
;
759 int64_t opal_invalid_call(void);
760 int64_t opal_console_write(int64_t term_number
, __be64
*length
,
761 const uint8_t *buffer
);
762 int64_t opal_console_read(int64_t term_number
, __be64
*length
,
764 int64_t opal_console_write_buffer_space(int64_t term_number
,
766 int64_t opal_rtc_read(__be32
*year_month_day
,
767 __be64
*hour_minute_second_millisecond
);
768 int64_t opal_rtc_write(uint32_t year_month_day
,
769 uint64_t hour_minute_second_millisecond
);
770 int64_t opal_tpo_read(uint64_t token
, __be32
*year_mon_day
, __be32
*hour_min
);
771 int64_t opal_tpo_write(uint64_t token
, uint32_t year_mon_day
,
773 int64_t opal_cec_power_down(uint64_t request
);
774 int64_t opal_cec_reboot(void);
775 int64_t opal_read_nvram(uint64_t buffer
, uint64_t size
, uint64_t offset
);
776 int64_t opal_write_nvram(uint64_t buffer
, uint64_t size
, uint64_t offset
);
777 int64_t opal_handle_interrupt(uint64_t isn
, __be64
*outstanding_event_mask
);
778 int64_t opal_poll_events(__be64
*outstanding_event_mask
);
779 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id
, uint64_t tce_mem_addr
,
780 uint64_t tce_mem_size
);
781 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id
, uint64_t tce_mem_addr
,
782 uint64_t tce_mem_size
);
783 int64_t opal_pci_config_read_byte(uint64_t phb_id
, uint64_t bus_dev_func
,
784 uint64_t offset
, uint8_t *data
);
785 int64_t opal_pci_config_read_half_word(uint64_t phb_id
, uint64_t bus_dev_func
,
786 uint64_t offset
, __be16
*data
);
787 int64_t opal_pci_config_read_word(uint64_t phb_id
, uint64_t bus_dev_func
,
788 uint64_t offset
, __be32
*data
);
789 int64_t opal_pci_config_write_byte(uint64_t phb_id
, uint64_t bus_dev_func
,
790 uint64_t offset
, uint8_t data
);
791 int64_t opal_pci_config_write_half_word(uint64_t phb_id
, uint64_t bus_dev_func
,
792 uint64_t offset
, uint16_t data
);
793 int64_t opal_pci_config_write_word(uint64_t phb_id
, uint64_t bus_dev_func
,
794 uint64_t offset
, uint32_t data
);
795 int64_t opal_set_xive(uint32_t isn
, uint16_t server
, uint8_t priority
);
796 int64_t opal_get_xive(uint32_t isn
, __be16
*server
, uint8_t *priority
);
797 int64_t opal_register_exception_handler(uint64_t opal_exception
,
798 uint64_t handler_address
,
799 uint64_t glue_cache_line
);
800 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id
, uint64_t pe_number
,
801 uint8_t *freeze_state
,
802 __be16
*pci_error_type
,
804 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id
, uint64_t pe_number
,
805 uint64_t eeh_action_token
);
806 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id
, uint64_t pe_number
,
807 uint64_t eeh_action_token
);
808 int64_t opal_pci_err_inject(uint64_t phb_id
, uint32_t pe_no
, uint32_t type
,
809 uint32_t func
, uint64_t addr
, uint64_t mask
);
810 int64_t opal_pci_shpc(uint64_t phb_id
, uint64_t shpc_action
, uint8_t *state
);
814 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id
, uint16_t window_type
,
815 uint16_t window_num
, uint16_t enable
);
816 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id
, uint16_t window_type
,
818 uint64_t starting_real_address
,
819 uint64_t starting_pci_address
,
821 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id
, uint16_t pe_number
,
822 uint16_t window_type
, uint16_t window_num
,
823 uint16_t segment_num
);
824 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id
, uint64_t rtt_addr
,
825 uint64_t ivt_addr
, uint64_t ivt_len
,
826 uint64_t reject_array_addr
,
827 uint64_t peltv_addr
);
828 int64_t opal_pci_set_pe(uint64_t phb_id
, uint64_t pe_number
, uint64_t bus_dev_func
,
829 uint8_t bus_compare
, uint8_t dev_compare
, uint8_t func_compare
,
831 int64_t opal_pci_set_peltv(uint64_t phb_id
, uint32_t parent_pe
, uint32_t child_pe
,
833 int64_t opal_pci_set_mve(uint64_t phb_id
, uint32_t mve_number
, uint32_t pe_number
);
834 int64_t opal_pci_set_mve_enable(uint64_t phb_id
, uint32_t mve_number
,
836 int64_t opal_pci_get_xive_reissue(uint64_t phb_id
, uint32_t xive_number
,
837 uint8_t *p_bit
, uint8_t *q_bit
);
838 int64_t opal_pci_set_xive_reissue(uint64_t phb_id
, uint32_t xive_number
,
839 uint8_t p_bit
, uint8_t q_bit
);
840 int64_t opal_pci_msi_eoi(uint64_t phb_id
, uint32_t hw_irq
);
841 int64_t opal_pci_set_xive_pe(uint64_t phb_id
, uint32_t pe_number
,
843 int64_t opal_get_xive_source(uint64_t phb_id
, uint32_t xive_num
,
844 __be32
*interrupt_source_number
);
845 int64_t opal_get_msi_32(uint64_t phb_id
, uint32_t mve_number
, uint32_t xive_num
,
846 uint8_t msi_range
, __be32
*msi_address
,
847 __be32
*message_data
);
848 int64_t opal_get_msi_64(uint64_t phb_id
, uint32_t mve_number
,
849 uint32_t xive_num
, uint8_t msi_range
,
850 __be64
*msi_address
, __be32
*message_data
);
851 int64_t opal_start_cpu(uint64_t thread_number
, uint64_t start_address
);
852 int64_t opal_query_cpu_status(uint64_t thread_number
, uint8_t *thread_status
);
853 int64_t opal_write_oppanel(oppanel_line_t
*lines
, uint64_t num_lines
);
854 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id
, uint16_t pe_number
, uint16_t window_id
,
855 uint16_t tce_levels
, uint64_t tce_table_addr
,
856 uint64_t tce_table_size
, uint64_t tce_page_size
);
857 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id
, uint16_t pe_number
,
858 uint16_t dma_window_number
, uint64_t pci_start_addr
,
859 uint64_t pci_mem_size
);
860 int64_t opal_pci_reset(uint64_t phb_id
, uint8_t reset_scope
, uint8_t assert_state
);
862 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id
, void *diag_buffer
,
863 uint64_t diag_buffer_len
);
864 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id
, void *diag_buffer
,
865 uint64_t diag_buffer_len
);
866 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id
, void *diag_buffer
,
867 uint64_t diag_buffer_len
);
868 int64_t opal_pci_fence_phb(uint64_t phb_id
);
869 int64_t opal_pci_reinit(uint64_t phb_id
, uint64_t reinit_scope
, uint64_t data
);
870 int64_t opal_pci_mask_pe_error(uint64_t phb_id
, uint16_t pe_number
, uint8_t error_type
, uint8_t mask_action
);
871 int64_t opal_set_slot_led_status(uint64_t phb_id
, uint64_t slot_id
, uint8_t led_type
, uint8_t led_action
);
872 int64_t opal_get_epow_status(__be64
*status
);
873 int64_t opal_set_system_attention_led(uint8_t led_action
);
874 int64_t opal_pci_next_error(uint64_t phb_id
, __be64
*first_frozen_pe
,
875 __be16
*pci_error_type
, __be16
*severity
);
876 int64_t opal_pci_poll(uint64_t phb_id
);
877 int64_t opal_return_cpu(void);
878 int64_t opal_check_token(uint64_t token
);
879 int64_t opal_reinit_cpus(uint64_t flags
);
881 int64_t opal_xscom_read(uint32_t gcid
, uint64_t pcb_addr
, __be64
*val
);
882 int64_t opal_xscom_write(uint32_t gcid
, uint64_t pcb_addr
, uint64_t val
);
884 int64_t opal_lpc_write(uint32_t chip_id
, enum OpalLPCAddressType addr_type
,
885 uint32_t addr
, uint32_t data
, uint32_t sz
);
886 int64_t opal_lpc_read(uint32_t chip_id
, enum OpalLPCAddressType addr_type
,
887 uint32_t addr
, __be32
*data
, uint32_t sz
);
889 int64_t opal_read_elog(uint64_t buffer
, uint64_t size
, uint64_t log_id
);
890 int64_t opal_get_elog_size(__be64
*log_id
, __be64
*size
, __be64
*elog_type
);
891 int64_t opal_write_elog(uint64_t buffer
, uint64_t size
, uint64_t offset
);
892 int64_t opal_send_ack_elog(uint64_t log_id
);
893 void opal_resend_pending_logs(void);
895 int64_t opal_validate_flash(uint64_t buffer
, uint32_t *size
, uint32_t *result
);
896 int64_t opal_manage_flash(uint8_t op
);
897 int64_t opal_update_flash(uint64_t blk_list
);
898 int64_t opal_dump_init(uint8_t dump_type
);
899 int64_t opal_dump_info(__be32
*dump_id
, __be32
*dump_size
);
900 int64_t opal_dump_info2(__be32
*dump_id
, __be32
*dump_size
, __be32
*dump_type
);
901 int64_t opal_dump_read(uint32_t dump_id
, uint64_t buffer
);
902 int64_t opal_dump_ack(uint32_t dump_id
);
903 int64_t opal_dump_resend_notification(void);
905 int64_t opal_get_msg(uint64_t buffer
, uint64_t size
);
906 int64_t opal_check_completion(uint64_t buffer
, uint64_t size
, uint64_t token
);
907 int64_t opal_sync_host_reboot(void);
908 int64_t opal_get_param(uint64_t token
, uint32_t param_id
, uint64_t buffer
,
910 int64_t opal_set_param(uint64_t token
, uint32_t param_id
, uint64_t buffer
,
912 int64_t opal_sensor_read(uint32_t sensor_hndl
, int token
, __be32
*sensor_data
);
913 int64_t opal_handle_hmi(void);
914 int64_t opal_register_dump_region(uint32_t id
, uint64_t start
, uint64_t end
);
915 int64_t opal_unregister_dump_region(uint32_t id
);
916 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id
, uint64_t mode
, uint64_t pe_number
);
917 int64_t opal_ipmi_send(uint64_t interface
, struct opal_ipmi_msg
*msg
,
919 int64_t opal_ipmi_recv(uint64_t interface
, struct opal_ipmi_msg
*msg
,
921 int64_t opal_i2c_request(uint64_t async_token
, uint32_t bus_id
,
922 struct opal_i2c_request
*oreq
);
924 /* Internal functions */
925 extern int early_init_dt_scan_opal(unsigned long node
, const char *uname
,
926 int depth
, void *data
);
927 extern int early_init_dt_scan_recoverable_ranges(unsigned long node
,
928 const char *uname
, int depth
, void *data
);
930 extern int opal_get_chars(uint32_t vtermno
, char *buf
, int count
);
931 extern int opal_put_chars(uint32_t vtermno
, const char *buf
, int total_len
);
933 extern void hvc_opal_init_early(void);
935 extern int opal_notifier_register(struct notifier_block
*nb
);
936 extern int opal_notifier_unregister(struct notifier_block
*nb
);
938 extern int opal_message_notifier_register(enum OpalMessageType msg_type
,
939 struct notifier_block
*nb
);
940 extern void opal_notifier_enable(void);
941 extern void opal_notifier_disable(void);
942 extern void opal_notifier_update_evt(uint64_t evt_mask
, uint64_t evt_val
);
944 extern int __opal_async_get_token(void);
945 extern int opal_async_get_token_interruptible(void);
946 extern int __opal_async_release_token(int token
);
947 extern int opal_async_release_token(int token
);
948 extern int opal_async_wait_response(uint64_t token
, struct opal_msg
*msg
);
949 extern int opal_get_sensor_data(u32 sensor_hndl
, u32
*sensor_data
);
952 extern unsigned long opal_get_boot_time(void);
953 extern void opal_nvram_init(void);
954 extern void opal_flash_init(void);
955 extern void opal_flash_term_callback(void);
956 extern int opal_elog_init(void);
957 extern void opal_platform_dump_init(void);
958 extern void opal_sys_param_init(void);
959 extern void opal_msglog_init(void);
961 extern int opal_machine_check(struct pt_regs
*regs
);
962 extern bool opal_mce_check_early_recovery(struct pt_regs
*regs
);
963 extern int opal_hmi_exception_early(struct pt_regs
*regs
);
964 extern int opal_handle_hmi_exception(struct pt_regs
*regs
);
966 extern void opal_shutdown(void);
967 extern int opal_resync_timebase(void);
969 extern void opal_lpc_init(void);
971 struct opal_sg_list
*opal_vmalloc_to_sg_list(void *vmalloc_addr
,
972 unsigned long vmalloc_size
);
973 void opal_free_sg_list(struct opal_sg_list
*sg
);
976 * Dump region ID range usable by the OS
978 #define OPAL_DUMP_REGION_HOST_START 0x80
979 #define OPAL_DUMP_REGION_LOG_BUF 0x80
980 #define OPAL_DUMP_REGION_HOST_END 0xFF
982 #endif /* __ASSEMBLY__ */
984 #endif /* __OPAL_H */