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powerpc/powernv: Enable fetching of platform sensor data
[deliverable/linux.git] / arch / powerpc / include / asm / opal.h
1 /*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_H
13 #define __OPAL_H
14
15 /****** Takeover interface ********/
16
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23 #ifndef __ASSEMBLY__
24
25 struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34 };
35
36 /*
37 * SG entry
38 *
39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well.
42 */
43 struct opal_sg_entry {
44 void *data;
45 long length;
46 };
47
48 /* sg list */
49 struct opal_sg_list {
50 unsigned long num_entries;
51 struct opal_sg_list *next;
52 struct opal_sg_entry entry[];
53 };
54
55 /* We calculate number of sg entries based on PAGE_SIZE */
56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
57
58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
59
60 extern long opal_do_takeover(struct opal_takeover_args *args);
61
62 struct rtas_args;
63 extern int opal_enter_rtas(struct rtas_args *args,
64 unsigned long data,
65 unsigned long entry);
66
67 #endif /* __ASSEMBLY__ */
68
69 /****** OPAL APIs ******/
70
71 /* Return codes */
72 #define OPAL_SUCCESS 0
73 #define OPAL_PARAMETER -1
74 #define OPAL_BUSY -2
75 #define OPAL_PARTIAL -3
76 #define OPAL_CONSTRAINED -4
77 #define OPAL_CLOSED -5
78 #define OPAL_HARDWARE -6
79 #define OPAL_UNSUPPORTED -7
80 #define OPAL_PERMISSION -8
81 #define OPAL_NO_MEM -9
82 #define OPAL_RESOURCE -10
83 #define OPAL_INTERNAL_ERROR -11
84 #define OPAL_BUSY_EVENT -12
85 #define OPAL_HARDWARE_FROZEN -13
86 #define OPAL_WRONG_STATE -14
87 #define OPAL_ASYNC_COMPLETION -15
88
89 /* API Tokens (in r0) */
90 #define OPAL_CONSOLE_WRITE 1
91 #define OPAL_CONSOLE_READ 2
92 #define OPAL_RTC_READ 3
93 #define OPAL_RTC_WRITE 4
94 #define OPAL_CEC_POWER_DOWN 5
95 #define OPAL_CEC_REBOOT 6
96 #define OPAL_READ_NVRAM 7
97 #define OPAL_WRITE_NVRAM 8
98 #define OPAL_HANDLE_INTERRUPT 9
99 #define OPAL_POLL_EVENTS 10
100 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
101 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
102 #define OPAL_PCI_CONFIG_READ_BYTE 13
103 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
104 #define OPAL_PCI_CONFIG_READ_WORD 15
105 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
106 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
107 #define OPAL_PCI_CONFIG_WRITE_WORD 18
108 #define OPAL_SET_XIVE 19
109 #define OPAL_GET_XIVE 20
110 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
111 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
112 #define OPAL_PCI_EEH_FREEZE_STATUS 23
113 #define OPAL_PCI_SHPC 24
114 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
115 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
116 #define OPAL_PCI_PHB_MMIO_ENABLE 27
117 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
118 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
119 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
120 #define OPAL_PCI_SET_PE 31
121 #define OPAL_PCI_SET_PELTV 32
122 #define OPAL_PCI_SET_MVE 33
123 #define OPAL_PCI_SET_MVE_ENABLE 34
124 #define OPAL_PCI_GET_XIVE_REISSUE 35
125 #define OPAL_PCI_SET_XIVE_REISSUE 36
126 #define OPAL_PCI_SET_XIVE_PE 37
127 #define OPAL_GET_XIVE_SOURCE 38
128 #define OPAL_GET_MSI_32 39
129 #define OPAL_GET_MSI_64 40
130 #define OPAL_START_CPU 41
131 #define OPAL_QUERY_CPU_STATUS 42
132 #define OPAL_WRITE_OPPANEL 43
133 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
134 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
135 #define OPAL_PCI_RESET 49
136 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
137 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
138 #define OPAL_PCI_FENCE_PHB 52
139 #define OPAL_PCI_REINIT 53
140 #define OPAL_PCI_MASK_PE_ERROR 54
141 #define OPAL_SET_SLOT_LED_STATUS 55
142 #define OPAL_GET_EPOW_STATUS 56
143 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
144 #define OPAL_RESERVED1 58
145 #define OPAL_RESERVED2 59
146 #define OPAL_PCI_NEXT_ERROR 60
147 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
148 #define OPAL_PCI_POLL 62
149 #define OPAL_PCI_MSI_EOI 63
150 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
151 #define OPAL_XSCOM_READ 65
152 #define OPAL_XSCOM_WRITE 66
153 #define OPAL_LPC_READ 67
154 #define OPAL_LPC_WRITE 68
155 #define OPAL_RETURN_CPU 69
156 #define OPAL_ELOG_READ 71
157 #define OPAL_ELOG_WRITE 72
158 #define OPAL_ELOG_ACK 73
159 #define OPAL_ELOG_RESEND 74
160 #define OPAL_ELOG_SIZE 75
161 #define OPAL_FLASH_VALIDATE 76
162 #define OPAL_FLASH_MANAGE 77
163 #define OPAL_FLASH_UPDATE 78
164 #define OPAL_DUMP_INIT 81
165 #define OPAL_DUMP_INFO 82
166 #define OPAL_DUMP_READ 83
167 #define OPAL_DUMP_ACK 84
168 #define OPAL_GET_MSG 85
169 #define OPAL_CHECK_ASYNC_COMPLETION 86
170 #define OPAL_SYNC_HOST_REBOOT 87
171 #define OPAL_SENSOR_READ 88
172 #define OPAL_GET_PARAM 89
173 #define OPAL_SET_PARAM 90
174 #define OPAL_DUMP_RESEND 91
175 #define OPAL_DUMP_INFO2 94
176
177 #ifndef __ASSEMBLY__
178
179 /* Other enums */
180 enum OpalVendorApiTokens {
181 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
182 };
183
184 enum OpalFreezeState {
185 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
186 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
187 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
188 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
189 OPAL_EEH_STOPPED_RESET = 4,
190 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
191 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
192 };
193
194 enum OpalEehFreezeActionToken {
195 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
196 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
197 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
198 };
199
200 enum OpalPciStatusToken {
201 OPAL_EEH_NO_ERROR = 0,
202 OPAL_EEH_IOC_ERROR = 1,
203 OPAL_EEH_PHB_ERROR = 2,
204 OPAL_EEH_PE_ERROR = 3,
205 OPAL_EEH_PE_MMIO_ERROR = 4,
206 OPAL_EEH_PE_DMA_ERROR = 5
207 };
208
209 enum OpalPciErrorSeverity {
210 OPAL_EEH_SEV_NO_ERROR = 0,
211 OPAL_EEH_SEV_IOC_DEAD = 1,
212 OPAL_EEH_SEV_PHB_DEAD = 2,
213 OPAL_EEH_SEV_PHB_FENCED = 3,
214 OPAL_EEH_SEV_PE_ER = 4,
215 OPAL_EEH_SEV_INF = 5
216 };
217
218 enum OpalShpcAction {
219 OPAL_SHPC_GET_LINK_STATE = 0,
220 OPAL_SHPC_GET_SLOT_STATE = 1
221 };
222
223 enum OpalShpcLinkState {
224 OPAL_SHPC_LINK_DOWN = 0,
225 OPAL_SHPC_LINK_UP = 1
226 };
227
228 enum OpalMmioWindowType {
229 OPAL_M32_WINDOW_TYPE = 1,
230 OPAL_M64_WINDOW_TYPE = 2,
231 OPAL_IO_WINDOW_TYPE = 3
232 };
233
234 enum OpalShpcSlotState {
235 OPAL_SHPC_DEV_NOT_PRESENT = 0,
236 OPAL_SHPC_DEV_PRESENT = 1
237 };
238
239 enum OpalExceptionHandler {
240 OPAL_MACHINE_CHECK_HANDLER = 1,
241 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
242 OPAL_SOFTPATCH_HANDLER = 3
243 };
244
245 enum OpalPendingState {
246 OPAL_EVENT_OPAL_INTERNAL = 0x1,
247 OPAL_EVENT_NVRAM = 0x2,
248 OPAL_EVENT_RTC = 0x4,
249 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
250 OPAL_EVENT_CONSOLE_INPUT = 0x10,
251 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
252 OPAL_EVENT_ERROR_LOG = 0x40,
253 OPAL_EVENT_EPOW = 0x80,
254 OPAL_EVENT_LED_STATUS = 0x100,
255 OPAL_EVENT_PCI_ERROR = 0x200,
256 OPAL_EVENT_DUMP_AVAIL = 0x400,
257 OPAL_EVENT_MSG_PENDING = 0x800,
258 };
259
260 enum OpalMessageType {
261 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
262 * additional params function-specific
263 */
264 OPAL_MSG_MEM_ERR,
265 OPAL_MSG_EPOW,
266 OPAL_MSG_SHUTDOWN,
267 OPAL_MSG_TYPE_MAX,
268 };
269
270 /* Machine check related definitions */
271 enum OpalMCE_Version {
272 OpalMCE_V1 = 1,
273 };
274
275 enum OpalMCE_Severity {
276 OpalMCE_SEV_NO_ERROR = 0,
277 OpalMCE_SEV_WARNING = 1,
278 OpalMCE_SEV_ERROR_SYNC = 2,
279 OpalMCE_SEV_FATAL = 3,
280 };
281
282 enum OpalMCE_Disposition {
283 OpalMCE_DISPOSITION_RECOVERED = 0,
284 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
285 };
286
287 enum OpalMCE_Initiator {
288 OpalMCE_INITIATOR_UNKNOWN = 0,
289 OpalMCE_INITIATOR_CPU = 1,
290 };
291
292 enum OpalMCE_ErrorType {
293 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
294 OpalMCE_ERROR_TYPE_UE = 1,
295 OpalMCE_ERROR_TYPE_SLB = 2,
296 OpalMCE_ERROR_TYPE_ERAT = 3,
297 OpalMCE_ERROR_TYPE_TLB = 4,
298 };
299
300 enum OpalMCE_UeErrorType {
301 OpalMCE_UE_ERROR_INDETERMINATE = 0,
302 OpalMCE_UE_ERROR_IFETCH = 1,
303 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
304 OpalMCE_UE_ERROR_LOAD_STORE = 3,
305 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
306 };
307
308 enum OpalMCE_SlbErrorType {
309 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
310 OpalMCE_SLB_ERROR_PARITY = 1,
311 OpalMCE_SLB_ERROR_MULTIHIT = 2,
312 };
313
314 enum OpalMCE_EratErrorType {
315 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
316 OpalMCE_ERAT_ERROR_PARITY = 1,
317 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
318 };
319
320 enum OpalMCE_TlbErrorType {
321 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
322 OpalMCE_TLB_ERROR_PARITY = 1,
323 OpalMCE_TLB_ERROR_MULTIHIT = 2,
324 };
325
326 enum OpalThreadStatus {
327 OPAL_THREAD_INACTIVE = 0x0,
328 OPAL_THREAD_STARTED = 0x1,
329 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
330 };
331
332 enum OpalPciBusCompare {
333 OpalPciBusAny = 0, /* Any bus number match */
334 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
335 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
336 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
337 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
338 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
339 OpalPciBusAll = 7, /* Match bus number exactly */
340 };
341
342 enum OpalDeviceCompare {
343 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
344 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
345 };
346
347 enum OpalFuncCompare {
348 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
349 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
350 };
351
352 enum OpalPeAction {
353 OPAL_UNMAP_PE = 0,
354 OPAL_MAP_PE = 1
355 };
356
357 enum OpalPeltvAction {
358 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
359 OPAL_ADD_PE_TO_DOMAIN = 1
360 };
361
362 enum OpalMveEnableAction {
363 OPAL_DISABLE_MVE = 0,
364 OPAL_ENABLE_MVE = 1
365 };
366
367 enum OpalPciResetScope {
368 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
369 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
370 OPAL_PCI_IODA_TABLE_RESET = 6,
371 };
372
373 enum OpalPciReinitScope {
374 OPAL_REINIT_PCI_DEV = 1000
375 };
376
377 enum OpalPciResetState {
378 OPAL_DEASSERT_RESET = 0,
379 OPAL_ASSERT_RESET = 1
380 };
381
382 enum OpalPciMaskAction {
383 OPAL_UNMASK_ERROR_TYPE = 0,
384 OPAL_MASK_ERROR_TYPE = 1
385 };
386
387 enum OpalSlotLedType {
388 OPAL_SLOT_LED_ID_TYPE = 0,
389 OPAL_SLOT_LED_FAULT_TYPE = 1
390 };
391
392 enum OpalLedAction {
393 OPAL_TURN_OFF_LED = 0,
394 OPAL_TURN_ON_LED = 1,
395 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
396 };
397
398 enum OpalEpowStatus {
399 OPAL_EPOW_NONE = 0,
400 OPAL_EPOW_UPS = 1,
401 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
402 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
403 };
404
405 /*
406 * Address cycle types for LPC accesses. These also correspond
407 * to the content of the first cell of the "reg" property for
408 * device nodes on the LPC bus
409 */
410 enum OpalLPCAddressType {
411 OPAL_LPC_MEM = 0,
412 OPAL_LPC_IO = 1,
413 OPAL_LPC_FW = 2,
414 };
415
416 /* System parameter permission */
417 enum OpalSysparamPerm {
418 OPAL_SYSPARAM_READ = 0x1,
419 OPAL_SYSPARAM_WRITE = 0x2,
420 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
421 };
422
423 struct opal_msg {
424 uint32_t msg_type;
425 uint32_t reserved;
426 uint64_t params[8];
427 };
428
429 struct opal_machine_check_event {
430 enum OpalMCE_Version version:8; /* 0x00 */
431 uint8_t in_use; /* 0x01 */
432 enum OpalMCE_Severity severity:8; /* 0x02 */
433 enum OpalMCE_Initiator initiator:8; /* 0x03 */
434 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
435 enum OpalMCE_Disposition disposition:8; /* 0x05 */
436 uint8_t reserved_1[2]; /* 0x06 */
437 uint64_t gpr3; /* 0x08 */
438 uint64_t srr0; /* 0x10 */
439 uint64_t srr1; /* 0x18 */
440 union { /* 0x20 */
441 struct {
442 enum OpalMCE_UeErrorType ue_error_type:8;
443 uint8_t effective_address_provided;
444 uint8_t physical_address_provided;
445 uint8_t reserved_1[5];
446 uint64_t effective_address;
447 uint64_t physical_address;
448 uint8_t reserved_2[8];
449 } ue_error;
450
451 struct {
452 enum OpalMCE_SlbErrorType slb_error_type:8;
453 uint8_t effective_address_provided;
454 uint8_t reserved_1[6];
455 uint64_t effective_address;
456 uint8_t reserved_2[16];
457 } slb_error;
458
459 struct {
460 enum OpalMCE_EratErrorType erat_error_type:8;
461 uint8_t effective_address_provided;
462 uint8_t reserved_1[6];
463 uint64_t effective_address;
464 uint8_t reserved_2[16];
465 } erat_error;
466
467 struct {
468 enum OpalMCE_TlbErrorType tlb_error_type:8;
469 uint8_t effective_address_provided;
470 uint8_t reserved_1[6];
471 uint64_t effective_address;
472 uint8_t reserved_2[16];
473 } tlb_error;
474 } u;
475 };
476
477 /* FSP memory errors handling */
478 enum OpalMemErr_Version {
479 OpalMemErr_V1 = 1,
480 };
481
482 enum OpalMemErrType {
483 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
484 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
485 OPAL_MEM_ERR_TYPE_SCRUB,
486 };
487
488 /* Memory Reilience error type */
489 enum OpalMemErr_ResilErrType {
490 OPAL_MEM_RESILIENCE_CE = 0,
491 OPAL_MEM_RESILIENCE_UE,
492 OPAL_MEM_RESILIENCE_UE_SCRUB,
493 };
494
495 /* Dynamic Memory Deallocation type */
496 enum OpalMemErr_DynErrType {
497 OPAL_MEM_DYNAMIC_DEALLOC = 0,
498 };
499
500 /* OpalMemoryErrorData->flags */
501 #define OPAL_MEM_CORRECTED_ERROR 0x0001
502 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
503 #define OPAL_MEM_ACK_REQUIRED 0x8000
504
505 struct OpalMemoryErrorData {
506 enum OpalMemErr_Version version:8; /* 0x00 */
507 enum OpalMemErrType type:8; /* 0x01 */
508 uint16_t flags; /* 0x02 */
509 uint8_t reserved_1[4]; /* 0x04 */
510
511 union {
512 /* Memory Resilience corrected/uncorrected error info */
513 struct {
514 enum OpalMemErr_ResilErrType resil_err_type:8;
515 uint8_t reserved_1[7];
516 uint64_t physical_address_start;
517 uint64_t physical_address_end;
518 } resilience;
519 /* Dynamic memory deallocation error info */
520 struct {
521 enum OpalMemErr_DynErrType dyn_err_type:8;
522 uint8_t reserved_1[7];
523 uint64_t physical_address_start;
524 uint64_t physical_address_end;
525 } dyn_dealloc;
526 } u;
527 };
528
529 enum {
530 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
531 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
532 OPAL_P7IOC_DIAG_TYPE_BI = 2,
533 OPAL_P7IOC_DIAG_TYPE_CI = 3,
534 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
535 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
536 OPAL_P7IOC_DIAG_TYPE_LAST = 6
537 };
538
539 struct OpalIoP7IOCErrorData {
540 uint16_t type;
541
542 /* GEM */
543 uint64_t gemXfir;
544 uint64_t gemRfir;
545 uint64_t gemRirqfir;
546 uint64_t gemMask;
547 uint64_t gemRwof;
548
549 /* LEM */
550 uint64_t lemFir;
551 uint64_t lemErrMask;
552 uint64_t lemAction0;
553 uint64_t lemAction1;
554 uint64_t lemWof;
555
556 union {
557 struct OpalIoP7IOCRgcErrorData {
558 uint64_t rgcStatus; /* 3E1C10 */
559 uint64_t rgcLdcp; /* 3E1C18 */
560 }rgc;
561 struct OpalIoP7IOCBiErrorData {
562 uint64_t biLdcp0; /* 3C0100, 3C0118 */
563 uint64_t biLdcp1; /* 3C0108, 3C0120 */
564 uint64_t biLdcp2; /* 3C0110, 3C0128 */
565 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
566
567 uint8_t biDownbound; /* BI Downbound or Upbound */
568 }bi;
569 struct OpalIoP7IOCCiErrorData {
570 uint64_t ciPortStatus; /* 3Dn008 */
571 uint64_t ciPortLdcp; /* 3Dn010 */
572
573 uint8_t ciPort; /* Index of CI port: 0/1 */
574 }ci;
575 };
576 };
577
578 /**
579 * This structure defines the overlay which will be used to store PHB error
580 * data upon request.
581 */
582 enum {
583 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
584 };
585
586 enum {
587 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
588 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
589 };
590
591 enum {
592 OPAL_P7IOC_NUM_PEST_REGS = 128,
593 OPAL_PHB3_NUM_PEST_REGS = 256
594 };
595
596 struct OpalIoPhbErrorCommon {
597 uint32_t version;
598 uint32_t ioType;
599 uint32_t len;
600 };
601
602 struct OpalIoP7IOCPhbErrorData {
603 struct OpalIoPhbErrorCommon common;
604
605 uint32_t brdgCtl;
606
607 // P7IOC utl regs
608 uint32_t portStatusReg;
609 uint32_t rootCmplxStatus;
610 uint32_t busAgentStatus;
611
612 // P7IOC cfg regs
613 uint32_t deviceStatus;
614 uint32_t slotStatus;
615 uint32_t linkStatus;
616 uint32_t devCmdStatus;
617 uint32_t devSecStatus;
618
619 // cfg AER regs
620 uint32_t rootErrorStatus;
621 uint32_t uncorrErrorStatus;
622 uint32_t corrErrorStatus;
623 uint32_t tlpHdr1;
624 uint32_t tlpHdr2;
625 uint32_t tlpHdr3;
626 uint32_t tlpHdr4;
627 uint32_t sourceId;
628
629 uint32_t rsv3;
630
631 // Record data about the call to allocate a buffer.
632 uint64_t errorClass;
633 uint64_t correlator;
634
635 //P7IOC MMIO Error Regs
636 uint64_t p7iocPlssr; // n120
637 uint64_t p7iocCsr; // n110
638 uint64_t lemFir; // nC00
639 uint64_t lemErrorMask; // nC18
640 uint64_t lemWOF; // nC40
641 uint64_t phbErrorStatus; // nC80
642 uint64_t phbFirstErrorStatus; // nC88
643 uint64_t phbErrorLog0; // nCC0
644 uint64_t phbErrorLog1; // nCC8
645 uint64_t mmioErrorStatus; // nD00
646 uint64_t mmioFirstErrorStatus; // nD08
647 uint64_t mmioErrorLog0; // nD40
648 uint64_t mmioErrorLog1; // nD48
649 uint64_t dma0ErrorStatus; // nD80
650 uint64_t dma0FirstErrorStatus; // nD88
651 uint64_t dma0ErrorLog0; // nDC0
652 uint64_t dma0ErrorLog1; // nDC8
653 uint64_t dma1ErrorStatus; // nE00
654 uint64_t dma1FirstErrorStatus; // nE08
655 uint64_t dma1ErrorLog0; // nE40
656 uint64_t dma1ErrorLog1; // nE48
657 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
658 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
659 };
660
661 struct OpalIoPhb3ErrorData {
662 struct OpalIoPhbErrorCommon common;
663
664 uint32_t brdgCtl;
665
666 /* PHB3 UTL regs */
667 uint32_t portStatusReg;
668 uint32_t rootCmplxStatus;
669 uint32_t busAgentStatus;
670
671 /* PHB3 cfg regs */
672 uint32_t deviceStatus;
673 uint32_t slotStatus;
674 uint32_t linkStatus;
675 uint32_t devCmdStatus;
676 uint32_t devSecStatus;
677
678 /* cfg AER regs */
679 uint32_t rootErrorStatus;
680 uint32_t uncorrErrorStatus;
681 uint32_t corrErrorStatus;
682 uint32_t tlpHdr1;
683 uint32_t tlpHdr2;
684 uint32_t tlpHdr3;
685 uint32_t tlpHdr4;
686 uint32_t sourceId;
687
688 uint32_t rsv3;
689
690 /* Record data about the call to allocate a buffer */
691 uint64_t errorClass;
692 uint64_t correlator;
693
694 uint64_t nFir; /* 000 */
695 uint64_t nFirMask; /* 003 */
696 uint64_t nFirWOF; /* 008 */
697
698 /* PHB3 MMIO Error Regs */
699 uint64_t phbPlssr; /* 120 */
700 uint64_t phbCsr; /* 110 */
701 uint64_t lemFir; /* C00 */
702 uint64_t lemErrorMask; /* C18 */
703 uint64_t lemWOF; /* C40 */
704 uint64_t phbErrorStatus; /* C80 */
705 uint64_t phbFirstErrorStatus; /* C88 */
706 uint64_t phbErrorLog0; /* CC0 */
707 uint64_t phbErrorLog1; /* CC8 */
708 uint64_t mmioErrorStatus; /* D00 */
709 uint64_t mmioFirstErrorStatus; /* D08 */
710 uint64_t mmioErrorLog0; /* D40 */
711 uint64_t mmioErrorLog1; /* D48 */
712 uint64_t dma0ErrorStatus; /* D80 */
713 uint64_t dma0FirstErrorStatus; /* D88 */
714 uint64_t dma0ErrorLog0; /* DC0 */
715 uint64_t dma0ErrorLog1; /* DC8 */
716 uint64_t dma1ErrorStatus; /* E00 */
717 uint64_t dma1FirstErrorStatus; /* E08 */
718 uint64_t dma1ErrorLog0; /* E40 */
719 uint64_t dma1ErrorLog1; /* E48 */
720 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
721 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
722 };
723
724 typedef struct oppanel_line {
725 const char * line;
726 uint64_t line_len;
727 } oppanel_line_t;
728
729 /* /sys/firmware/opal */
730 extern struct kobject *opal_kobj;
731
732 /* API functions */
733 int64_t opal_console_write(int64_t term_number, __be64 *length,
734 const uint8_t *buffer);
735 int64_t opal_console_read(int64_t term_number, __be64 *length,
736 uint8_t *buffer);
737 int64_t opal_console_write_buffer_space(int64_t term_number,
738 __be64 *length);
739 int64_t opal_rtc_read(__be32 *year_month_day,
740 __be64 *hour_minute_second_millisecond);
741 int64_t opal_rtc_write(uint32_t year_month_day,
742 uint64_t hour_minute_second_millisecond);
743 int64_t opal_cec_power_down(uint64_t request);
744 int64_t opal_cec_reboot(void);
745 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
746 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
747 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
748 int64_t opal_poll_events(__be64 *outstanding_event_mask);
749 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
750 uint64_t tce_mem_size);
751 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
752 uint64_t tce_mem_size);
753 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
754 uint64_t offset, uint8_t *data);
755 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
756 uint64_t offset, __be16 *data);
757 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
758 uint64_t offset, __be32 *data);
759 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
760 uint64_t offset, uint8_t data);
761 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
762 uint64_t offset, uint16_t data);
763 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
764 uint64_t offset, uint32_t data);
765 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
766 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
767 int64_t opal_register_exception_handler(uint64_t opal_exception,
768 uint64_t handler_address,
769 uint64_t glue_cache_line);
770 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
771 uint8_t *freeze_state,
772 __be16 *pci_error_type,
773 __be64 *phb_status);
774 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
775 uint64_t eeh_action_token);
776 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
777
778
779
780 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
781 uint16_t window_num, uint16_t enable);
782 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
783 uint16_t window_num,
784 uint64_t starting_real_address,
785 uint64_t starting_pci_address,
786 uint16_t segment_size);
787 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
788 uint16_t window_type, uint16_t window_num,
789 uint16_t segment_num);
790 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
791 uint64_t ivt_addr, uint64_t ivt_len,
792 uint64_t reject_array_addr,
793 uint64_t peltv_addr);
794 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
795 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
796 uint8_t pe_action);
797 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
798 uint8_t state);
799 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
800 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
801 uint32_t state);
802 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
803 uint8_t *p_bit, uint8_t *q_bit);
804 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
805 uint8_t p_bit, uint8_t q_bit);
806 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
807 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
808 uint32_t xive_num);
809 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
810 __be32 *interrupt_source_number);
811 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
812 uint8_t msi_range, __be32 *msi_address,
813 __be32 *message_data);
814 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
815 uint32_t xive_num, uint8_t msi_range,
816 __be64 *msi_address, __be32 *message_data);
817 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
818 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
819 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
820 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
821 uint16_t tce_levels, uint64_t tce_table_addr,
822 uint64_t tce_table_size, uint64_t tce_page_size);
823 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
824 uint16_t dma_window_number, uint64_t pci_start_addr,
825 uint64_t pci_mem_size);
826 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
827
828 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
829 uint64_t diag_buffer_len);
830 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
831 uint64_t diag_buffer_len);
832 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
833 uint64_t diag_buffer_len);
834 int64_t opal_pci_fence_phb(uint64_t phb_id);
835 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
836 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
837 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
838 int64_t opal_get_epow_status(__be64 *status);
839 int64_t opal_set_system_attention_led(uint8_t led_action);
840 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
841 uint16_t *pci_error_type, uint16_t *severity);
842 int64_t opal_pci_poll(uint64_t phb_id);
843 int64_t opal_return_cpu(void);
844
845 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
846 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
847
848 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
849 uint32_t addr, uint32_t data, uint32_t sz);
850 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
851 uint32_t addr, __be32 *data, uint32_t sz);
852
853 int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
854 int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
855 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
856 int64_t opal_send_ack_elog(uint64_t log_id);
857 void opal_resend_pending_logs(void);
858
859 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
860 int64_t opal_manage_flash(uint8_t op);
861 int64_t opal_update_flash(uint64_t blk_list);
862 int64_t opal_dump_init(uint8_t dump_type);
863 int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
864 int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
865 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
866 int64_t opal_dump_ack(uint32_t dump_id);
867 int64_t opal_dump_resend_notification(void);
868
869 int64_t opal_get_msg(uint64_t buffer, size_t size);
870 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
871 int64_t opal_sync_host_reboot(void);
872 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
873 size_t length);
874 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
875 size_t length);
876 int64_t opal_sensor_read(uint32_t sensor_hndl, int token,
877 uint32_t *sensor_data);
878
879 /* Internal functions */
880 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
881 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
882 const char *uname, int depth, void *data);
883
884 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
885 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
886
887 extern void hvc_opal_init_early(void);
888
889 /* Internal functions */
890 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
891 int depth, void *data);
892
893 extern int opal_notifier_register(struct notifier_block *nb);
894 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
895 struct notifier_block *nb);
896 extern void opal_notifier_enable(void);
897 extern void opal_notifier_disable(void);
898 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
899
900 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
901 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
902
903 extern int __opal_async_get_token(void);
904 extern int opal_async_get_token_interruptible(void);
905 extern int __opal_async_release_token(int token);
906 extern int opal_async_release_token(int token);
907 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
908 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
909
910 extern void hvc_opal_init_early(void);
911
912 struct rtc_time;
913 extern int opal_set_rtc_time(struct rtc_time *tm);
914 extern void opal_get_rtc_time(struct rtc_time *tm);
915 extern unsigned long opal_get_boot_time(void);
916 extern void opal_nvram_init(void);
917 extern void opal_flash_init(void);
918 extern int opal_elog_init(void);
919 extern void opal_platform_dump_init(void);
920 extern void opal_sys_param_init(void);
921
922 extern int opal_machine_check(struct pt_regs *regs);
923 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
924
925 extern void opal_shutdown(void);
926
927 extern void opal_lpc_init(void);
928
929 #endif /* __ASSEMBLY__ */
930
931 #endif /* __OPAL_H */
Linux kernel - Deliverables
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