arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 /* Return values for pci_controller_ops.probe_mode function */
  16 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
  17 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
  18 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
  19
  20 struct device_node;
  21
  22 /*
  23  * PCI controller operations
  24  */
  25 struct pci_controller_ops {
  26         void            (*dma_dev_setup)(struct pci_dev *dev);
  27         void            (*dma_bus_setup)(struct pci_bus *bus);
  28
  29         int             (*probe_mode)(struct pci_bus *);
  30
  31         /* Called when pci_enable_device() is called. Returns true to
  32          * allow assignment/enabling of the device. */
  33         bool            (*enable_device_hook)(struct pci_dev *);
  34 };
  35
  36 /*
  37  * Structure of a PCI controller (host bridge)
  38  */
  39 struct pci_controller {
  40         struct pci_bus *bus;
  41         char is_dynamic;
  42 #ifdef CONFIG_PPC64
  43         int node;
  44 #endif
  45         struct device_node *dn;
  46         struct list_head list_node;
  47         struct device *parent;
  48
  49         int first_busno;
  50         int last_busno;
  51         int self_busno;
  52         struct resource busn;
  53
  54         void __iomem *io_base_virt;
  55 #ifdef CONFIG_PPC64
  56         void *io_base_alloc;
  57 #endif
  58         resource_size_t io_base_phys;
  59         resource_size_t pci_io_size;
  60
  61         /* Some machines have a special region to forward the ISA
  62          * "memory" cycles such as VGA memory regions. Left to 0
  63          * if unsupported
  64          */
  65         resource_size_t isa_mem_phys;
  66         resource_size_t isa_mem_size;
  67
  68         struct pci_controller_ops controller_ops;
  69         struct pci_ops *ops;
  70         unsigned int __iomem *cfg_addr;
  71         void __iomem *cfg_data;
  72
  73         /*
  74          * Used for variants of PCI indirect handling and possible quirks:
  75          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  76          *  EXT_REG - provides access to PCI-e extended registers
  77          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  78          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  79          *   to determine which bus number to match on when generating type0
  80          *   config cycles
  81          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  82          *   hanging if we don't have link and try to do config cycles to
  83          *   anything but the PHB.  Only allow talking to the PHB if this is
  84          *   set.
  85          *  BIG_ENDIAN - cfg_addr is a big endian register
  86          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  87          *   the PLB4.  Effectively disable MRM commands by setting this.
  88          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  89          *   link status is in a RC PCIe cfg register (vs being a SoC register)
  90          */
  91 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  92 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  93 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  94 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  95 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
  96 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
  97 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
  98         u32 indirect_type;
  99         /* Currently, we limit ourselves to 1 IO range and 3 mem
 100          * ranges since the common pci_bus structure can't handle more
 101          */
 102         struct resource io_resource;
 103         struct resource mem_resources[3];
 104         resource_size_t mem_offset[3];
 105         int global_number;              /* PCI domain number */
 106
 107         resource_size_t dma_window_base_cur;
 108         resource_size_t dma_window_size;
 109
 110 #ifdef CONFIG_PPC64
 111         unsigned long buid;
 112         struct pci_dn *pci_data;
 113 #endif  /* CONFIG_PPC64 */
 114
 115         void *private_data;
 116 };
 117
 118 /* These are used for config access before all the PCI probing
 119    has been done. */
 120 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 121                         int dev_fn, int where, u8 *val);
 122 extern int early_read_config_word(struct pci_controller *hose, int bus,
 123                         int dev_fn, int where, u16 *val);
 124 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 125                         int dev_fn, int where, u32 *val);
 126 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 127                         int dev_fn, int where, u8 val);
 128 extern int early_write_config_word(struct pci_controller *hose, int bus,
 129                         int dev_fn, int where, u16 val);
 130 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 131                         int dev_fn, int where, u32 val);
 132
 133 extern int early_find_capability(struct pci_controller *hose, int bus,
 134                                  int dev_fn, int cap);
 135
 136 extern void setup_indirect_pci(struct pci_controller* hose,
 137                                resource_size_t cfg_addr,
 138                                resource_size_t cfg_data, u32 flags);
 139
 140 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 141                                 int offset, int len, u32 *val);
 142
 143 extern int __indirect_read_config(struct pci_controller *hose,
 144                                   unsigned char bus_number, unsigned int devfn,
 145                                   int offset, int len, u32 *val);
 146
 147 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 148                                  int offset, int len, u32 val);
 149
 150 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 151 {
 152         return bus->sysdata;
 153 }
 154
 155 #ifndef CONFIG_PPC64
 156
 157 extern int pci_device_from_OF_node(struct device_node *node,
 158                                    u8 *bus, u8 *devfn);
 159 extern void pci_create_OF_bus_map(void);
 160
 161 static inline int isa_vaddr_is_ioport(void __iomem *address)
 162 {
 163         /* No specific ISA handling on ppc32 at this stage, it
 164          * all goes through PCI
 165          */
 166         return 0;
 167 }
 168
 169 #else   /* CONFIG_PPC64 */
 170
 171 /*
 172  * PCI stuff, for nodes representing PCI devices, pointed to
 173  * by device_node->data.
 174  */
 175 struct iommu_table;
 176
 177 struct pci_dn {
 178         int     flags;
 179
 180         int     busno;                  /* pci bus number */
 181         int     devfn;                  /* pci device and function number */
 182         int     vendor_id;              /* Vendor ID */
 183         int     device_id;              /* Device ID */
 184         int     class_code;             /* Device class code */
 185
 186         struct  pci_dn *parent;
 187         struct  pci_controller *phb;    /* for pci devices */
 188         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 189         struct  device_node *node;      /* back-pointer to the device_node */
 190
 191         int     pci_ext_config_space;   /* for pci devices */
 192
 193         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 194 #ifdef CONFIG_EEH
 195         struct eeh_dev *edev;           /* eeh device */
 196 #endif
 197 #define IODA_INVALID_PE         (-1)
 198 #ifdef CONFIG_PPC_POWERNV
 199         int     pe_number;
 200 #endif
 201         struct list_head child_list;
 202         struct list_head list;
 203 };
 204
 205 /* Get the pointer to a device_node's pci_dn */
 206 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 207
 208 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
 209                                            int devfn);
 210 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
 211 extern void *update_dn_pci_info(struct device_node *dn, void *data);
 212
 213 static inline int pci_device_from_OF_node(struct device_node *np,
 214                                           u8 *bus, u8 *devfn)
 215 {
 216         if (!PCI_DN(np))
 217                 return -ENODEV;
 218         *bus = PCI_DN(np)->busno;
 219         *devfn = PCI_DN(np)->devfn;
 220         return 0;
 221 }
 222
 223 #if defined(CONFIG_EEH)
 224 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
 225 {
 226         return pdn ? pdn->edev : NULL;
 227 }
 228 #else
 229 #define pdn_to_eeh_dev(x)       (NULL)
 230 #endif
 231
 232 /** Find the bus corresponding to the indicated device node */
 233 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 234
 235 /** Remove all of the PCI devices under this bus */
 236 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 237
 238 /** Discover new pci devices under this bus, and add them */
 239 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 240
 241
 242 extern void isa_bridge_find_early(struct pci_controller *hose);
 243
 244 static inline int isa_vaddr_is_ioport(void __iomem *address)
 245 {
 246         /* Check if address hits the reserved legacy IO range */
 247         unsigned long ea = (unsigned long)address;
 248         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 249 }
 250
 251 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 252 extern int pcibios_map_io_space(struct pci_bus *bus);
 253
 254 #ifdef CONFIG_NUMA
 255 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 256 #else
 257 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 258 #endif
 259
 260 #endif  /* CONFIG_PPC64 */
 261
 262 /* Get the PCI host controller for an OF device */
 263 extern struct pci_controller *pci_find_hose_for_OF_device(
 264                         struct device_node* node);
 265
 266 /* Fill up host controller resources from the OF node */
 267 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 268                         struct device_node *dev, int primary);
 269
 270 /* Allocate & free a PCI host bridge structure */
 271 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 272 extern void pcibios_free_controller(struct pci_controller *phb);
 273
 274 #ifdef CONFIG_PCI
 275 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 276 #else
 277 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 278 {
 279         return 0;
 280 }
 281 #endif  /* CONFIG_PCI */
 282
 283 /*
 284  * Shims to prefer pci_controller version over ppc_md where available.
 285  */
 286 static inline void pci_dma_dev_setup(struct pci_dev *dev)
 287 {
 288         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 289
 290         if (phb->controller_ops.dma_dev_setup)
 291                 phb->controller_ops.dma_dev_setup(dev);
 292         else if (ppc_md.pci_dma_dev_setup)
 293                 ppc_md.pci_dma_dev_setup(dev);
 294 }
 295
 296 static inline void pci_dma_bus_setup(struct pci_bus *bus)
 297 {
 298         struct pci_controller *phb = pci_bus_to_host(bus);
 299
 300         if (phb->controller_ops.dma_bus_setup)
 301                 phb->controller_ops.dma_bus_setup(bus);
 302         else if (ppc_md.pci_dma_bus_setup)
 303                 ppc_md.pci_dma_bus_setup(bus);
 304 }
 305
 306 static inline int pci_probe_mode(struct pci_bus *bus)
 307 {
 308         struct pci_controller *phb = pci_bus_to_host(bus);
 309
 310         if (phb->controller_ops.probe_mode)
 311                 return phb->controller_ops.probe_mode(bus);
 312         if (ppc_md.pci_probe_mode)
 313                 return ppc_md.pci_probe_mode(bus);
 314         return PCI_PROBE_NORMAL;
 315 }
 316
 317 static inline bool pcibios_enable_device_hook(struct pci_dev *dev)
 318 {
 319         struct pci_controller *phb = pci_bus_to_host(dev->bus);
 320
 321         if (phb->controller_ops.enable_device_hook)
 322                 return phb->controller_ops.enable_device_hook(dev);
 323         if (ppc_md.pcibios_enable_device_hook)
 324                 return ppc_md.pcibios_enable_device_hook(dev);
 325         return true;
 326 }
 327
 328 #endif  /* __KERNEL__ */
 329 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */