arch/powerpc/include/asm/perf_counter.h

   1 /*
   2  * Performance counter support - PowerPC-specific definitions.
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/types.h>
  12
  13 #define MAX_HWCOUNTERS          8
  14 #define MAX_EVENT_ALTERNATIVES  8
  15 #define MAX_LIMITED_HWCOUNTERS  2
  16
  17 /*
  18  * This struct provides the constants and functions needed to
  19  * describe the PMU on a particular POWER-family CPU.
  20  */
  21 struct power_pmu {
  22         int     n_counter;
  23         int     max_alternatives;
  24         u64     add_fields;
  25         u64     test_adder;
  26         int     (*compute_mmcr)(u64 events[], int n_ev,
  27                                 unsigned int hwc[], u64 mmcr[]);
  28         int     (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
  29         int     (*get_alternatives)(u64 event, unsigned int flags,
  30                                     u64 alt[]);
  31         void    (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
  32         int     (*limited_pmc_event)(u64 event);
  33         u32     flags;
  34         int     n_generic;
  35         int     *generic_events;
  36         int     (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
  37                                [PERF_COUNT_HW_CACHE_OP_MAX]
  38                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
  39 };
  40
  41 extern struct power_pmu *ppmu;
  42
  43 /*
  44  * Values for power_pmu.flags
  45  */
  46 #define PPMU_LIMITED_PMC5_6     1       /* PMC5/6 have limited function */
  47 #define PPMU_ALT_SIPR           2       /* uses alternate posn for SIPR/HV */
  48
  49 /*
  50  * Values for flags to get_alternatives()
  51  */
  52 #define PPMU_LIMITED_PMC_OK     1       /* can put this on a limited PMC */
  53 #define PPMU_LIMITED_PMC_REQD   2       /* have to put this on a limited PMC */
  54 #define PPMU_ONLY_COUNT_RUN     4       /* only counting in run state */
  55
  56 struct pt_regs;
  57 extern unsigned long perf_misc_flags(struct pt_regs *regs);
  58 #define perf_misc_flags(regs)   perf_misc_flags(regs)
  59
  60 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
  61
  62 /*
  63  * The power_pmu.get_constraint function returns a 64-bit value and
  64  * a 64-bit mask that express the constraints between this event and
  65  * other events.
  66  *
  67  * The value and mask are divided up into (non-overlapping) bitfields
  68  * of three different types:
  69  *
  70  * Select field: this expresses the constraint that some set of bits
  71  * in MMCR* needs to be set to a specific value for this event.  For a
  72  * select field, the mask contains 1s in every bit of the field, and
  73  * the value contains a unique value for each possible setting of the
  74  * MMCR* bits.  The constraint checking code will ensure that two events
  75  * that set the same field in their masks have the same value in their
  76  * value dwords.
  77  *
  78  * Add field: this expresses the constraint that there can be at most
  79  * N events in a particular class.  A field of k bits can be used for
  80  * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
  81  * set (and the other bits 0), and the value has only the least significant
  82  * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
  83  * in the struct power_pmu for this processor come into play.  The
  84  * add_fields value contains 1 in the LSB of the field, and the
  85  * test_adder contains 2^(k-1) - 1 - N in the field.
  86  *
  87  * NAND field: this expresses the constraint that you may not have events
  88  * in all of a set of classes.  (For example, on PPC970, you can't select
  89  * events from the FPU, ISU and IDU simultaneously, although any two are
  90  * possible.)  For N classes, the field is N+1 bits wide, and each class
  91  * is assigned one bit from the least-significant N bits.  The mask has
  92  * only the most-significant bit set, and the value has only the bit
  93  * for the event's class set.  The test_adder has the least significant
  94  * bit set in the field.
  95  *
  96  * If an event is not subject to the constraint expressed by a particular
  97  * field, then it will have 0 in both the mask and value for that field.
  98  */