arch/powerpc/include/asm/pgtable-ppc32.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
   2 #define _ASM_POWERPC_PGTABLE_PPC32_H
   3
   4 #include <asm-generic/pgtable-nopmd.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  10
  11 extern unsigned long va_to_phys(unsigned long address);
  12 extern pte_t *va_to_pte(unsigned long address);
  13 extern unsigned long ioremap_bot;
  14
  15 #ifdef CONFIG_44x
  16 extern int icache_44x_need_flush;
  17 #endif
  18
  19 #endif /* __ASSEMBLY__ */
  20
  21 /*
  22  * The normal case is that PTEs are 32-bits and we have a 1-page
  23  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  24  *
  25  * For any >32-bit physical address platform, we can use the following
  26  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  27  * are an index to the second level table.  The combined pgdir/pmd first
  28  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  29  * -Matt
  30  */
  31 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  32 #define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
  33 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  34 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  35
  36 /*
  37  * entries per page directory level: our page-table tree is two-level, so
  38  * we don't really have any PMD directory.
  39  */
  40 #ifndef __ASSEMBLY__
  41 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_SHIFT)
  42 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
  43 #endif  /* __ASSEMBLY__ */
  44
  45 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  46 #define PTRS_PER_PMD    1
  47 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  48
  49 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  50 #define FIRST_USER_ADDRESS      0
  51
  52 #define pte_ERROR(e) \
  53         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
  54                 (unsigned long long)pte_val(e))
  55 #define pgd_ERROR(e) \
  56         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
  57
  58 /*
  59  * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
  60  * value (for now) on others, from where we can start layout kernel
  61  * virtual space that goes below PKMAP and FIXMAP
  62  */
  63 #ifdef CONFIG_HIGHMEM
  64 #define KVIRT_TOP       PKMAP_BASE
  65 #else
  66 #define KVIRT_TOP       (0xfe000000UL)  /* for now, could be FIXMAP_BASE ? */
  67 #endif
  68
  69 /*
  70  * ioremap_bot starts at that address. Early ioremaps move down from there,
  71  * until mem_init() at which point this becomes the top of the vmalloc
  72  * and ioremap space
  73  */
  74 #define IOREMAP_TOP     KVIRT_TOP
  75
  76 /*
  77  * Just any arbitrary offset to the start of the vmalloc VM area: the
  78  * current 16MB value just means that there will be a 64MB "hole" after the
  79  * physical memory until the kernel virtual memory starts.  That means that
  80  * any out-of-bounds memory accesses will hopefully be caught.
  81  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  82  * area for the same reason. ;)
  83  *
  84  * We no longer map larger than phys RAM with the BATs so we don't have
  85  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
  86  * about clashes between our early calls to ioremap() that start growing down
  87  * from ioremap_base being run into the VM area allocations (growing upwards
  88  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
  89  * we actually run into our mappings setup in the early boot with the VM
  90  * system.  This really does become a problem for machines with good amounts
  91  * of RAM.  -- Cort
  92  */
  93 #define VMALLOC_OFFSET (0x1000000) /* 16M */
  94 #ifdef PPC_PIN_SIZE
  95 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
  96 #else
  97 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
  98 #endif
  99 #define VMALLOC_END     ioremap_bot
 100
 101 /*
 102  * Bits in a linux-style PTE.  These match the bits in the
 103  * (hardware-defined) PowerPC PTE as closely as possible.
 104  */
 105
 106 #if defined(CONFIG_40x)
 107 #include <asm/pte-40x.h>
 108 #elif defined(CONFIG_44x)
 109 #include <asm/pte-44x.h>
 110 #elif defined(CONFIG_FSL_BOOKE)
 111 #include <asm/pte-fsl-booke.h>
 112 #elif defined(CONFIG_8xx)
 113 #include <asm/pte-8xx.h>
 114 #else /* CONFIG_6xx */
 115 #include <asm/pte-hash32.h>
 116 #endif
 117
 118 /* And here we include common definitions */
 119 #include <asm/pte-common.h>
 120
 121 #ifndef __ASSEMBLY__
 122
 123 #define pte_clear(mm, addr, ptep) \
 124         do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
 125
 126 #define pmd_none(pmd)           (!pmd_val(pmd))
 127 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 128 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 129 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 130
 131 /*
 132  * When flushing the tlb entry for a page, we also need to flush the hash
 133  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 134  */
 135 extern int flush_hash_pages(unsigned context, unsigned long va,
 136                             unsigned long pmdval, int count);
 137
 138 /* Add an HPTE to the hash table */
 139 extern void add_hash_page(unsigned context, unsigned long va,
 140                           unsigned long pmdval);
 141
 142 /* Flush an entry from the TLB/hash table */
 143 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
 144                              unsigned long address);
 145
 146 /*
 147  * PTE updates. This function is called whenever an existing
 148  * valid PTE is updated. This does -not- include set_pte_at()
 149  * which nowadays only sets a new PTE.
 150  *
 151  * Depending on the type of MMU, we may need to use atomic updates
 152  * and the PTE may be either 32 or 64 bit wide. In the later case,
 153  * when using atomic updates, only the low part of the PTE is
 154  * accessed atomically.
 155  *
 156  * In addition, on 44x, we also maintain a global flag indicating
 157  * that an executable user mapping was modified, which is needed
 158  * to properly flush the virtually tagged instruction cache of
 159  * those implementations.
 160  */
 161 #ifndef CONFIG_PTE_64BIT
 162 static inline unsigned long pte_update(pte_t *p,
 163                                        unsigned long clr,
 164                                        unsigned long set)
 165 {
 166 #ifdef PTE_ATOMIC_UPDATES
 167         unsigned long old, tmp;
 168
 169         __asm__ __volatile__("\
 170 1:      lwarx   %0,0,%3\n\
 171         andc    %1,%0,%4\n\
 172         or      %1,%1,%5\n"
 173         PPC405_ERR77(0,%3)
 174 "       stwcx.  %1,0,%3\n\
 175         bne-    1b"
 176         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 177         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 178         : "cc" );
 179 #else /* PTE_ATOMIC_UPDATES */
 180         unsigned long old = pte_val(*p);
 181         *p = __pte((old & ~clr) | set);
 182 #endif /* !PTE_ATOMIC_UPDATES */
 183
 184 #ifdef CONFIG_44x
 185         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 186                 icache_44x_need_flush = 1;
 187 #endif
 188         return old;
 189 }
 190 #else /* CONFIG_PTE_64BIT */
 191 static inline unsigned long long pte_update(pte_t *p,
 192                                             unsigned long clr,
 193                                             unsigned long set)
 194 {
 195 #ifdef PTE_ATOMIC_UPDATES
 196         unsigned long long old;
 197         unsigned long tmp;
 198
 199         __asm__ __volatile__("\
 200 1:      lwarx   %L0,0,%4\n\
 201         lwzx    %0,0,%3\n\
 202         andc    %1,%L0,%5\n\
 203         or      %1,%1,%6\n"
 204         PPC405_ERR77(0,%3)
 205 "       stwcx.  %1,0,%4\n\
 206         bne-    1b"
 207         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 208         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 209         : "cc" );
 210 #else /* PTE_ATOMIC_UPDATES */
 211         unsigned long long old = pte_val(*p);
 212         *p = __pte((old & ~(unsigned long long)clr) | set);
 213 #endif /* !PTE_ATOMIC_UPDATES */
 214
 215 #ifdef CONFIG_44x
 216         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 217                 icache_44x_need_flush = 1;
 218 #endif
 219         return old;
 220 }
 221 #endif /* CONFIG_PTE_64BIT */
 222
 223 /*
 224  * 2.6 calls this without flushing the TLB entry; this is wrong
 225  * for our hash-based implementation, we fix that up here.
 226  */
 227 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 228 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 229 {
 230         unsigned long old;
 231         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 232 #if _PAGE_HASHPTE != 0
 233         if (old & _PAGE_HASHPTE) {
 234                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 235                 flush_hash_pages(context, addr, ptephys, 1);
 236         }
 237 #endif
 238         return (old & _PAGE_ACCESSED) != 0;
 239 }
 240 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 241         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 242
 243 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 244 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 245                                        pte_t *ptep)
 246 {
 247         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 248 }
 249
 250 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 251 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 252                                       pte_t *ptep)
 253 {
 254         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 255 }
 256 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 257                                            unsigned long addr, pte_t *ptep)
 258 {
 259         ptep_set_wrprotect(mm, addr, ptep);
 260 }
 261
 262
 263 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 264 {
 265         unsigned long bits = pte_val(entry) &
 266                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
 267                  _PAGE_HWEXEC | _PAGE_EXEC);
 268         pte_update(ptep, 0, bits);
 269 }
 270
 271 #define __HAVE_ARCH_PTE_SAME
 272 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 273
 274 /*
 275  * Note that on Book E processors, the pmd contains the kernel virtual
 276  * (lowmem) address of the pte page.  The physical address is less useful
 277  * because everything runs with translation enabled (even the TLB miss
 278  * handler).  On everything else the pmd contains the physical address
 279  * of the pte page.  -- paulus
 280  */
 281 #ifndef CONFIG_BOOKE
 282 #define pmd_page_vaddr(pmd)     \
 283         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 284 #define pmd_page(pmd)           \
 285         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 286 #else
 287 #define pmd_page_vaddr(pmd)     \
 288         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 289 #define pmd_page(pmd)           \
 290         pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 291 #endif
 292
 293 /* to find an entry in a kernel page-table-directory */
 294 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 295
 296 /* to find an entry in a page-table-directory */
 297 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 298 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 299
 300 /* Find an entry in the third-level page table.. */
 301 #define pte_index(address)              \
 302         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 303 #define pte_offset_kernel(dir, addr)    \
 304         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 305 #define pte_offset_map(dir, addr)               \
 306         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 307 #define pte_offset_map_nested(dir, addr)        \
 308         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 309
 310 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 311 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 312
 313 /*
 314  * Encode and decode a swap entry.
 315  * Note that the bits we use in a PTE for representing a swap entry
 316  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 317  *_PAGE_HASHPTE bit (if used).  -- paulus
 318  */
 319 #define __swp_type(entry)               ((entry).val & 0x1f)
 320 #define __swp_offset(entry)             ((entry).val >> 5)
 321 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 322 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 323 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 324
 325 /* Encode and decode a nonlinear file mapping entry */
 326 #define PTE_FILE_MAX_BITS       29
 327 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 328 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 329
 330 /*
 331  * No page table caches to initialise
 332  */
 333 #define pgtable_cache_init()    do { } while (0)
 334
 335 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 336                       pmd_t **pmdp);
 337
 338 #endif /* !__ASSEMBLY__ */
 339
 340 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */