1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
2 #define _ASM_POWERPC_PGTABLE_PPC32_H
4 #include <asm-generic/pgtable-nopmd.h>
7 #include <linux/sched.h>
8 #include <linux/threads.h>
9 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
11 extern unsigned long va_to_phys(unsigned long address
);
12 extern pte_t
*va_to_pte(unsigned long address
);
13 extern unsigned long ioremap_bot
, ioremap_base
;
16 extern int icache_44x_need_flush
;
19 #endif /* __ASSEMBLY__ */
22 * The normal case is that PTEs are 32-bits and we have a 1-page
23 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
25 * For any >32-bit physical address platform, we can use the following
26 * two level page table layout where the pgdir is 8KB and the MS 13 bits
27 * are an index to the second level table. The combined pgdir/pmd first
28 * level has 2048 entries and the second level has 512 64-bit PTE entries.
31 /* PGDIR_SHIFT determines what a top-level page table entry can map */
32 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
33 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
34 #define PGDIR_MASK (~(PGDIR_SIZE-1))
37 * entries per page directory level: our page-table tree is two-level, so
38 * we don't really have any PMD directory.
41 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
42 #define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
43 #endif /* __ASSEMBLY__ */
45 #define PTRS_PER_PTE (1 << PTE_SHIFT)
46 #define PTRS_PER_PMD 1
47 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
49 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
50 #define FIRST_USER_ADDRESS 0
52 #define pte_ERROR(e) \
53 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
54 (unsigned long long)pte_val(e))
55 #define pgd_ERROR(e) \
56 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
59 * Just any arbitrary offset to the start of the vmalloc VM area: the
60 * current 64MB value just means that there will be a 64MB "hole" after the
61 * physical memory until the kernel virtual memory starts. That means that
62 * any out-of-bounds memory accesses will hopefully be caught.
63 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
64 * area for the same reason. ;)
66 * We no longer map larger than phys RAM with the BATs so we don't have
67 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
68 * about clashes between our early calls to ioremap() that start growing down
69 * from ioremap_base being run into the VM area allocations (growing upwards
70 * from VMALLOC_START). For this reason we have ioremap_bot to check when
71 * we actually run into our mappings setup in the early boot with the VM
72 * system. This really does become a problem for machines with good amounts
75 #define VMALLOC_OFFSET (0x1000000) /* 16M */
77 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
79 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
81 #define VMALLOC_END ioremap_bot
84 * Bits in a linux-style PTE. These match the bits in the
85 * (hardware-defined) PowerPC PTE as closely as possible.
88 #if defined(CONFIG_40x)
89 #include <asm/pte-40x.h>
90 #elif defined(CONFIG_44x)
91 #include <asm/pte-44x.h>
92 #elif defined(CONFIG_FSL_BOOKE)
93 #include <asm/pte-fsl-booke.h>
94 #elif defined(CONFIG_8xx)
95 #include <asm/pte-8xx.h>
96 #else /* CONFIG_6xx */
97 #include <asm/pte-hash32.h>
100 /* If _PAGE_SPECIAL is defined, then we advertise our support for it */
102 #define __HAVE_ARCH_PTE_SPECIAL
106 * Some bits are only used on some cpu families... Make sure that all
107 * the undefined gets defined as 0
109 #ifndef _PAGE_HASHPTE
110 #define _PAGE_HASHPTE 0
112 #ifndef _PTE_NONE_MASK
113 #define _PTE_NONE_MASK 0
116 #define _PAGE_SHARED 0
118 #ifndef _PAGE_HWWRITE
119 #define _PAGE_HWWRITE 0
122 #define _PAGE_HWEXEC 0
128 #define _PAGE_ENDIAN 0
130 #ifndef _PAGE_COHERENT
131 #define _PAGE_COHERENT 0
133 #ifndef _PAGE_WRITETHRU
134 #define _PAGE_WRITETHRU 0
136 #ifndef _PAGE_SPECIAL
137 #define _PAGE_SPECIAL 0
139 #ifndef _PMD_PRESENT_MASK
140 #define _PMD_PRESENT_MASK _PMD_PRESENT
144 #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
147 #ifndef _PAGE_KERNEL_RO
148 #define _PAGE_KERNEL_RO 0
150 #ifndef _PAGE_KERNEL_RW
151 #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
154 #define _PAGE_HPTEFLAGS _PAGE_HASHPTE
156 /* Location of the PFN in the PTE. Most platforms use the same as _PAGE_SHIFT
157 * here (ie, naturally aligned). Platform who don't just pre-define the
158 * value so we don't override it here
160 #ifndef PTE_RPN_SHIFT
161 #define PTE_RPN_SHIFT (PAGE_SHIFT)
164 #ifdef CONFIG_PTE_64BIT
165 #define PTE_RPN_MAX (1ULL << (64 - PTE_RPN_SHIFT))
166 #define PTE_RPN_MASK (~((1ULL<<PTE_RPN_SHIFT)-1))
168 #define PTE_RPN_MAX (1UL << (32 - PTE_RPN_SHIFT))
169 #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
172 /* _PAGE_CHG_MASK masks of bits that are to be preserved accross
175 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
176 _PAGE_ACCESSED | _PAGE_SPECIAL)
178 /* Mask of bits returned by pte_pgprot() */
179 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
180 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
181 _PAGE_USER | _PAGE_ACCESSED | \
182 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
183 _PAGE_EXEC | _PAGE_HWEXEC)
186 * We define 2 sets of base prot bits, one for basic pages (ie,
187 * cacheable kernel and user pages) and one for non cacheable
188 * pages. We always set _PAGE_COHERENT when SMP is enabled or
189 * the processor might need it for DMA coherency.
191 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
192 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
194 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
196 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
198 /* Permission masks used for kernel mappings */
199 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
200 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
202 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
203 _PAGE_NO_CACHE | _PAGE_GUARDED)
204 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW | _PAGE_EXEC)
205 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
206 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO | _PAGE_EXEC)
208 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
209 defined(CONFIG_KPROBES)
210 /* We want the debuggers to be able to set breakpoints anywhere, so
211 * don't write protect the kernel text */
212 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
214 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
217 #define PAGE_NONE __pgprot(_PAGE_BASE)
218 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
219 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
220 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
221 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
222 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
223 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
226 * The PowerPC can only do execute protection on a segment (256MB) basis,
227 * not on a page basis. So we consider execute permission the same as read.
228 * Also, write permissions imply read permissions.
229 * This is the closest we can get..
231 #define __P000 PAGE_NONE
232 #define __P001 PAGE_READONLY_X
233 #define __P010 PAGE_COPY
234 #define __P011 PAGE_COPY_X
235 #define __P100 PAGE_READONLY
236 #define __P101 PAGE_READONLY_X
237 #define __P110 PAGE_COPY
238 #define __P111 PAGE_COPY_X
240 #define __S000 PAGE_NONE
241 #define __S001 PAGE_READONLY_X
242 #define __S010 PAGE_SHARED
243 #define __S011 PAGE_SHARED_X
244 #define __S100 PAGE_READONLY
245 #define __S101 PAGE_READONLY_X
246 #define __S110 PAGE_SHARED
247 #define __S111 PAGE_SHARED_X
250 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
251 * kernel without large page PMD support */
252 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
255 * Conversions between PTE values and page frame numbers.
258 #define pte_pfn(x) (pte_val(x) >> PTE_RPN_SHIFT)
259 #define pte_page(x) pfn_to_page(pte_pfn(x))
261 #define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |\
263 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
264 #endif /* __ASSEMBLY__ */
266 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
267 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
268 #define pte_clear(mm, addr, ptep) \
269 do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
271 #define pmd_none(pmd) (!pmd_val(pmd))
272 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
273 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
274 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
278 * The following only work if pte_present() is true.
279 * Undefined behaviour if not..
281 static inline int pte_write(pte_t pte
) { return pte_val(pte
) & _PAGE_RW
; }
282 static inline int pte_dirty(pte_t pte
) { return pte_val(pte
) & _PAGE_DIRTY
; }
283 static inline int pte_young(pte_t pte
) { return pte_val(pte
) & _PAGE_ACCESSED
; }
284 static inline int pte_file(pte_t pte
) { return pte_val(pte
) & _PAGE_FILE
; }
285 static inline int pte_special(pte_t pte
) { return pte_val(pte
) & _PAGE_SPECIAL
; }
287 static inline pte_t
pte_wrprotect(pte_t pte
) {
288 pte_val(pte
) &= ~(_PAGE_RW
| _PAGE_HWWRITE
); return pte
; }
289 static inline pte_t
pte_mkclean(pte_t pte
) {
290 pte_val(pte
) &= ~(_PAGE_DIRTY
| _PAGE_HWWRITE
); return pte
; }
291 static inline pte_t
pte_mkold(pte_t pte
) {
292 pte_val(pte
) &= ~_PAGE_ACCESSED
; return pte
; }
294 static inline pte_t
pte_mkwrite(pte_t pte
) {
295 pte_val(pte
) |= _PAGE_RW
; return pte
; }
296 static inline pte_t
pte_mkdirty(pte_t pte
) {
297 pte_val(pte
) |= _PAGE_DIRTY
; return pte
; }
298 static inline pte_t
pte_mkyoung(pte_t pte
) {
299 pte_val(pte
) |= _PAGE_ACCESSED
; return pte
; }
300 static inline pte_t
pte_mkspecial(pte_t pte
) {
301 pte_val(pte
) |= _PAGE_SPECIAL
; return pte
; }
302 static inline pgprot_t
pte_pgprot(pte_t pte
)
304 return __pgprot(pte_val(pte
) & PAGE_PROT_BITS
);
307 static inline pte_t
pte_modify(pte_t pte
, pgprot_t newprot
)
309 pte_val(pte
) = (pte_val(pte
) & _PAGE_CHG_MASK
) | pgprot_val(newprot
);
314 * When flushing the tlb entry for a page, we also need to flush the hash
315 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
317 extern int flush_hash_pages(unsigned context
, unsigned long va
,
318 unsigned long pmdval
, int count
);
320 /* Add an HPTE to the hash table */
321 extern void add_hash_page(unsigned context
, unsigned long va
,
322 unsigned long pmdval
);
324 /* Flush an entry from the TLB/hash table */
325 extern void flush_hash_entry(struct mm_struct
*mm
, pte_t
*ptep
,
326 unsigned long address
);
329 * PTE updates. This function is called whenever an existing
330 * valid PTE is updated. This does -not- include set_pte_at()
331 * which nowadays only sets a new PTE.
333 * Depending on the type of MMU, we may need to use atomic updates
334 * and the PTE may be either 32 or 64 bit wide. In the later case,
335 * when using atomic updates, only the low part of the PTE is
336 * accessed atomically.
338 * In addition, on 44x, we also maintain a global flag indicating
339 * that an executable user mapping was modified, which is needed
340 * to properly flush the virtually tagged instruction cache of
341 * those implementations.
343 #ifndef CONFIG_PTE_64BIT
344 static inline unsigned long pte_update(pte_t
*p
,
348 #ifdef PTE_ATOMIC_UPDATES
349 unsigned long old
, tmp
;
351 __asm__
__volatile__("\
358 : "=&r" (old
), "=&r" (tmp
), "=m" (*p
)
359 : "r" (p
), "r" (clr
), "r" (set
), "m" (*p
)
361 #else /* PTE_ATOMIC_UPDATES */
362 unsigned long old
= pte_val(*p
);
363 *p
= __pte((old
& ~clr
) | set
);
364 #endif /* !PTE_ATOMIC_UPDATES */
367 if ((old
& _PAGE_USER
) && (old
& _PAGE_HWEXEC
))
368 icache_44x_need_flush
= 1;
372 #else /* CONFIG_PTE_64BIT */
373 static inline unsigned long long pte_update(pte_t
*p
,
377 #ifdef PTE_ATOMIC_UPDATES
378 unsigned long long old
;
381 __asm__
__volatile__("\
389 : "=&r" (old
), "=&r" (tmp
), "=m" (*p
)
390 : "r" (p
), "r" ((unsigned long)(p
) + 4), "r" (clr
), "r" (set
), "m" (*p
)
392 #else /* PTE_ATOMIC_UPDATES */
393 unsigned long long old
= pte_val(*p
);
394 *p
= __pte((old
& ~(unsigned long long)clr
) | set
);
395 #endif /* !PTE_ATOMIC_UPDATES */
398 if ((old
& _PAGE_USER
) && (old
& _PAGE_HWEXEC
))
399 icache_44x_need_flush
= 1;
403 #endif /* CONFIG_PTE_64BIT */
406 * 2.6 calls this without flushing the TLB entry; this is wrong
407 * for our hash-based implementation, we fix that up here.
409 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
410 static inline int __ptep_test_and_clear_young(unsigned int context
, unsigned long addr
, pte_t
*ptep
)
413 old
= pte_update(ptep
, _PAGE_ACCESSED
, 0);
414 #if _PAGE_HASHPTE != 0
415 if (old
& _PAGE_HASHPTE
) {
416 unsigned long ptephys
= __pa(ptep
) & PAGE_MASK
;
417 flush_hash_pages(context
, addr
, ptephys
, 1);
420 return (old
& _PAGE_ACCESSED
) != 0;
422 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
423 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
425 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
426 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
, unsigned long addr
,
429 return __pte(pte_update(ptep
, ~_PAGE_HASHPTE
, 0));
432 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
433 static inline void ptep_set_wrprotect(struct mm_struct
*mm
, unsigned long addr
,
436 pte_update(ptep
, (_PAGE_RW
| _PAGE_HWWRITE
), 0);
438 static inline void huge_ptep_set_wrprotect(struct mm_struct
*mm
,
439 unsigned long addr
, pte_t
*ptep
)
441 ptep_set_wrprotect(mm
, addr
, ptep
);
445 static inline void __ptep_set_access_flags(pte_t
*ptep
, pte_t entry
)
447 unsigned long bits
= pte_val(entry
) &
448 (_PAGE_DIRTY
| _PAGE_ACCESSED
| _PAGE_RW
|
449 _PAGE_HWEXEC
| _PAGE_EXEC
);
450 pte_update(ptep
, 0, bits
);
453 #define __HAVE_ARCH_PTE_SAME
454 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
457 * Note that on Book E processors, the pmd contains the kernel virtual
458 * (lowmem) address of the pte page. The physical address is less useful
459 * because everything runs with translation enabled (even the TLB miss
460 * handler). On everything else the pmd contains the physical address
461 * of the pte page. -- paulus
464 #define pmd_page_vaddr(pmd) \
465 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
466 #define pmd_page(pmd) \
467 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
469 #define pmd_page_vaddr(pmd) \
470 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
471 #define pmd_page(pmd) \
472 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
475 /* to find an entry in a kernel page-table-directory */
476 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
478 /* to find an entry in a page-table-directory */
479 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
480 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
482 /* Find an entry in the third-level page table.. */
483 #define pte_index(address) \
484 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
485 #define pte_offset_kernel(dir, addr) \
486 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
487 #define pte_offset_map(dir, addr) \
488 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
489 #define pte_offset_map_nested(dir, addr) \
490 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
492 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
493 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
496 * Encode and decode a swap entry.
497 * Note that the bits we use in a PTE for representing a swap entry
498 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
499 *_PAGE_HASHPTE bit (if used). -- paulus
501 #define __swp_type(entry) ((entry).val & 0x1f)
502 #define __swp_offset(entry) ((entry).val >> 5)
503 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
504 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
505 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
507 /* Encode and decode a nonlinear file mapping entry */
508 #define PTE_FILE_MAX_BITS 29
509 #define pte_to_pgoff(pte) (pte_val(pte) >> 3)
510 #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
513 * No page table caches to initialise
515 #define pgtable_cache_init() do { } while (0)
517 extern int get_pteptr(struct mm_struct
*mm
, unsigned long addr
, pte_t
**ptep
,
520 #endif /* !__ASSEMBLY__ */
522 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
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