arch/powerpc/include/asm/pgtable-ppc32.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
   2 #define _ASM_POWERPC_PGTABLE_PPC32_H
   3
   4 #include <asm-generic/pgtable-nopmd.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  10
  11 extern unsigned long va_to_phys(unsigned long address);
  12 extern pte_t *va_to_pte(unsigned long address);
  13 extern unsigned long ioremap_bot, ioremap_base;
  14
  15 #ifdef CONFIG_44x
  16 extern int icache_44x_need_flush;
  17 #endif
  18
  19 #endif /* __ASSEMBLY__ */
  20
  21 /*
  22  * The PowerPC MMU uses a hash table containing PTEs, together with
  23  * a set of 16 segment registers (on 32-bit implementations), to define
  24  * the virtual to physical address mapping.
  25  *
  26  * We use the hash table as an extended TLB, i.e. a cache of currently
  27  * active mappings.  We maintain a two-level page table tree, much
  28  * like that used by the i386, for the sake of the Linux memory
  29  * management code.  Low-level assembler code in hashtable.S
  30  * (procedure hash_page) is responsible for extracting ptes from the
  31  * tree and putting them into the hash table when necessary, and
  32  * updating the accessed and modified bits in the page table tree.
  33  */
  34
  35 /*
  36  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  37  * We also use the two level tables, but we can put the real bits in them
  38  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  39  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  40  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  41  * based upon user/super access.  The TLB does not have accessed nor write
  42  * protect.  We assume that if the TLB get loaded with an entry it is
  43  * accessed, and overload the changed bit for write protect.  We use
  44  * two bits in the software pte that are supposed to be set to zero in
  45  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  46  * descriptor contains the guarded and writethrough/copyback bits, we can
  47  * set these at the page level since they get copied from the Mx_TWC
  48  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  49  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  50  * These will get masked from the level 2 descriptor at TLB load time, and
  51  * copied to the MD_TWC before it gets loaded.
  52  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  53  * This also allows a TLB hander optimization because we can directly
  54  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  55  * mapping of well known areas.  The PMD (PGD) entries contain control
  56  * flags in addition to the address, so care must be taken that the
  57  * software no longer assumes these are only pointers.
  58  */
  59
  60 /*
  61  * At present, all PowerPC 400-class processors share a similar TLB
  62  * architecture. The instruction and data sides share a unified,
  63  * 64-entry, fully-associative TLB which is maintained totally under
  64  * software control. In addition, the instruction side has a
  65  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  66  * first level to the shared TLB. These two TLBs are known as the UTLB
  67  * and ITLB, respectively (see "mmu.h" for definitions).
  68  */
  69
  70 /*
  71  * The normal case is that PTEs are 32-bits and we have a 1-page
  72  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  73  *
  74  * For any >32-bit physical address platform, we can use the following
  75  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  76  * are an index to the second level table.  The combined pgdir/pmd first
  77  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  78  * -Matt
  79  */
  80 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  81 #define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
  82 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  83 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  84
  85 /*
  86  * entries per page directory level: our page-table tree is two-level, so
  87  * we don't really have any PMD directory.
  88  */
  89 #ifndef __ASSEMBLY__
  90 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_SHIFT)
  91 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
  92 #endif  /* __ASSEMBLY__ */
  93
  94 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  95 #define PTRS_PER_PMD    1
  96 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  97
  98 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  99 #define FIRST_USER_ADDRESS      0
 100
 101 #define pte_ERROR(e) \
 102         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
 103                 (unsigned long long)pte_val(e))
 104 #define pgd_ERROR(e) \
 105         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 106
 107 /*
 108  * Just any arbitrary offset to the start of the vmalloc VM area: the
 109  * current 64MB value just means that there will be a 64MB "hole" after the
 110  * physical memory until the kernel virtual memory starts.  That means that
 111  * any out-of-bounds memory accesses will hopefully be caught.
 112  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 113  * area for the same reason. ;)
 114  *
 115  * We no longer map larger than phys RAM with the BATs so we don't have
 116  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 117  * about clashes between our early calls to ioremap() that start growing down
 118  * from ioremap_base being run into the VM area allocations (growing upwards
 119  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 120  * we actually run into our mappings setup in the early boot with the VM
 121  * system.  This really does become a problem for machines with good amounts
 122  * of RAM.  -- Cort
 123  */
 124 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 125 #ifdef PPC_PIN_SIZE
 126 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 127 #else
 128 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 129 #endif
 130 #define VMALLOC_END     ioremap_bot
 131
 132 /*
 133  * Bits in a linux-style PTE.  These match the bits in the
 134  * (hardware-defined) PowerPC PTE as closely as possible.
 135  */
 136
 137 #if defined(CONFIG_40x)
 138
 139 /* There are several potential gotchas here.  The 40x hardware TLBLO
 140    field looks like this:
 141
 142    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 143    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 144
 145    Where possible we make the Linux PTE bits match up with this
 146
 147    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 148      support down to 1k pages), this is done in the TLBMiss exception
 149      handler.
 150    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 151      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 152      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 153      zone.
 154    - PRESENT *must* be in the bottom two bits because swap cache
 155      entries use the top 30 bits.  Because 40x doesn't support SMP
 156      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 157      is cleared in the TLB miss handler before the TLB entry is loaded.
 158    - All other bits of the PTE are loaded into TLBLO without
 159      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 160      software PTE bits.  We actually use use bits 21, 24, 25, and
 161      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 162      PRESENT.
 163 */
 164
 165 /* Definitions for 40x embedded chips. */
 166 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 167 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 168 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 169 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 170 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 171 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 172 #define _PAGE_RW        0x040   /* software: Writes permitted */
 173 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 174 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 175 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 176 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 177
 178 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 179 #define _PMD_BAD        0x802
 180 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 181 #define _PMD_SIZE_4M    0x0c0
 182 #define _PMD_SIZE_16M   0x0e0
 183 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 184
 185 /* Until my rework is finished, 40x still needs atomic PTE updates */
 186 #define PTE_ATOMIC_UPDATES      1
 187
 188 #elif defined(CONFIG_44x)
 189 /*
 190  * Definitions for PPC440
 191  *
 192  * Because of the 3 word TLB entries to support 36-bit addressing,
 193  * the attribute are difficult to map in such a fashion that they
 194  * are easily loaded during exception processing.  I decided to
 195  * organize the entry so the ERPN is the only portion in the
 196  * upper word of the PTE and the attribute bits below are packed
 197  * in as sensibly as they can be in the area below a 4KB page size
 198  * oriented RPN.  This at least makes it easy to load the RPN and
 199  * ERPN fields in the TLB. -Matt
 200  *
 201  * Note that these bits preclude future use of a page size
 202  * less than 4KB.
 203  *
 204  *
 205  * PPC 440 core has following TLB attribute fields;
 206  *
 207  *   TLB1:
 208  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 209  *   RPN.................................  -  -  -  -  -  - ERPN.......
 210  *
 211  *   TLB2:
 212  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 213  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 214  *
 215  * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
 216  * TLB2 storage attibute fields. Those are:
 217  *
 218  *   TLB2:
 219  *   0...10    11   12   13   14   15   16...31
 220  *   no change WL1  IL1I IL1D IL2I IL2D no change
 221  *
 222  * There are some constrains and options, to decide mapping software bits
 223  * into TLB entry.
 224  *
 225  *   - PRESENT *must* be in the bottom three bits because swap cache
 226  *     entries use the top 29 bits for TLB2.
 227  *
 228  *   - FILE *must* be in the bottom three bits because swap cache
 229  *     entries use the top 29 bits for TLB2.
 230  *
 231  *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
 232  *     because it doesn't support SMP. However, some later 460 variants
 233  *     have -some- form of SMP support and so I keep the bit there for
 234  *     future use
 235  *
 236  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
 237  * for memory protection related functions (see PTE structure in
 238  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
 239  * above bits.  Note that the bit values are CPU specific, not architecture
 240  * specific.
 241  *
 242  * The kernel PTE entry holds an arch-dependent swp_entry structure under
 243  * certain situations. In other words, in such situations some portion of
 244  * the PTE bits are used as a swp_entry. In the PPC implementation, the
 245  * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
 246  * hold protection values. That means the three protection bits are
 247  * reserved for both PTE and SWAP entry at the most significant three
 248  * LSBs.
 249  *
 250  * There are three protection bits available for SWAP entry:
 251  *      _PAGE_PRESENT
 252  *      _PAGE_FILE
 253  *      _PAGE_HASHPTE (if HW has)
 254  *
 255  * So those three bits have to be inside of 0-2nd LSB of PTE.
 256  *
 257  */
 258
 259 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 260 #define _PAGE_RW        0x00000002              /* S: Write permission */
 261 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 262 #define _PAGE_HWEXEC    0x00000004              /* H: Execute permission */
 263 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 264 #define _PAGE_DIRTY     0x00000010              /* S: Page dirty */
 265 #define _PAGE_SPECIAL   0x00000020              /* S: Special page */
 266 #define _PAGE_USER      0x00000040              /* S: User page */
 267 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 268 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 269 #define _PAGE_COHERENT  0x00000200              /* H: M bit */
 270 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 271 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 272
 273 /* TODO: Add large page lowmem mapping support */
 274 #define _PMD_PRESENT    0
 275 #define _PMD_PRESENT_MASK (PAGE_MASK)
 276 #define _PMD_BAD        (~PAGE_MASK)
 277
 278 /* ERPN in a PTE never gets cleared, ignore it */
 279 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 280
 281 #define __HAVE_ARCH_PTE_SPECIAL
 282
 283 #elif defined(CONFIG_FSL_BOOKE)
 284 /*
 285    MMU Assist Register 3:
 286
 287    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
 288    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
 289
 290    - PRESENT *must* be in the bottom three bits because swap cache
 291      entries use the top 29 bits.
 292
 293    - FILE *must* be in the bottom three bits because swap cache
 294      entries use the top 29 bits.
 295 */
 296
 297 /* Definitions for FSL Book-E Cores */
 298 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
 299 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
 300 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
 301 #define _PAGE_RW        0x00004 /* S: Write permission (SW) */
 302 #define _PAGE_DIRTY     0x00008 /* S: Page dirty */
 303 #define _PAGE_HWEXEC    0x00010 /* H: SX permission */
 304 #define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
 305
 306 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
 307 #define _PAGE_GUARDED   0x00080 /* H: G bit */
 308 #define _PAGE_COHERENT  0x00100 /* H: M bit */
 309 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
 310 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 311 #define _PAGE_SPECIAL   0x00800 /* S: Special page */
 312
 313 #ifdef CONFIG_PTE_64BIT
 314 /* ERPN in a PTE never gets cleared, ignore it */
 315 #define _PTE_NONE_MASK  0xffffffffffff0000ULL
 316 #endif
 317
 318 #define _PMD_PRESENT    0
 319 #define _PMD_PRESENT_MASK (PAGE_MASK)
 320 #define _PMD_BAD        (~PAGE_MASK)
 321
 322 #define __HAVE_ARCH_PTE_SPECIAL
 323
 324 #elif defined(CONFIG_8xx)
 325 /* Definitions for 8xx embedded chips. */
 326 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 327 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 328 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 329 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 330
 331 /* These five software bits must be masked out when the entry is loaded
 332  * into the TLB.
 333  */
 334 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 335 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 336 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 337 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 338 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 339
 340 /* Setting any bits in the nibble with the follow two controls will
 341  * require a TLB exception handler change.  It is assumed unused bits
 342  * are always zero.
 343  */
 344 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 345 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 346
 347 #define _PMD_PRESENT    0x0001
 348 #define _PMD_BAD        0x0ff0
 349 #define _PMD_PAGE_MASK  0x000c
 350 #define _PMD_PAGE_8M    0x000c
 351
 352 #define _PTE_NONE_MASK _PAGE_ACCESSED
 353
 354 /* Until my rework is finished, 8xx still needs atomic PTE updates */
 355 #define PTE_ATOMIC_UPDATES      1
 356
 357 #else /* CONFIG_6xx */
 358 /* Definitions for 60x, 740/750, etc. */
 359 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 360 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 361 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 362 #define _PAGE_USER      0x004   /* usermode access allowed */
 363 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 364 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 365 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 366 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 367 #define _PAGE_DIRTY     0x080   /* C: page changed */
 368 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 369 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 370 #define _PAGE_RW        0x400   /* software: user write access allowed */
 371 #define _PAGE_SPECIAL   0x800   /* software: Special page */
 372
 373 #ifdef CONFIG_PTE_64BIT
 374 /* We never clear the high word of the pte */
 375 #define _PTE_NONE_MASK  (0xffffffff00000000ULL | _PAGE_HASHPTE)
 376 #else
 377 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 378 #endif
 379
 380 #define _PMD_PRESENT    0
 381 #define _PMD_PRESENT_MASK (PAGE_MASK)
 382 #define _PMD_BAD        (~PAGE_MASK)
 383
 384 /* Hash table based platforms need atomic updates of the linux PTE */
 385 #define PTE_ATOMIC_UPDATES      1
 386
 387 #define __HAVE_ARCH_PTE_SPECIAL
 388
 389 #endif
 390
 391 /*
 392  * Some bits are only used on some cpu families...
 393  */
 394 #ifndef _PAGE_HASHPTE
 395 #define _PAGE_HASHPTE   0
 396 #endif
 397 #ifndef _PTE_NONE_MASK
 398 #define _PTE_NONE_MASK 0
 399 #endif
 400 #ifndef _PAGE_SHARED
 401 #define _PAGE_SHARED    0
 402 #endif
 403 #ifndef _PAGE_HWWRITE
 404 #define _PAGE_HWWRITE   0
 405 #endif
 406 #ifndef _PAGE_HWEXEC
 407 #define _PAGE_HWEXEC    0
 408 #endif
 409 #ifndef _PAGE_EXEC
 410 #define _PAGE_EXEC      0
 411 #endif
 412 #ifndef _PAGE_ENDIAN
 413 #define _PAGE_ENDIAN    0
 414 #endif
 415 #ifndef _PAGE_COHERENT
 416 #define _PAGE_COHERENT  0
 417 #endif
 418 #ifndef _PAGE_WRITETHRU
 419 #define _PAGE_WRITETHRU 0
 420 #endif
 421 #ifndef _PAGE_SPECIAL
 422 #define _PAGE_SPECIAL   0
 423 #endif
 424 #ifndef _PMD_PRESENT_MASK
 425 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 426 #endif
 427 #ifndef _PMD_SIZE
 428 #define _PMD_SIZE       0
 429 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 430 #endif
 431
 432 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
 433                          _PAGE_SPECIAL)
 434
 435
 436 #define PAGE_PROT_BITS  (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
 437                          _PAGE_WRITETHRU | _PAGE_ENDIAN | \
 438                          _PAGE_USER | _PAGE_ACCESSED | \
 439                          _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
 440                          _PAGE_EXEC | _PAGE_HWEXEC)
 441
 442 /*
 443  * We define 2 sets of base prot bits, one for basic pages (ie,
 444  * cacheable kernel and user pages) and one for non cacheable
 445  * pages. We always set _PAGE_COHERENT when SMP is enabled or
 446  * the processor might need it for DMA coherency.
 447  */
 448 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
 449 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
 450 #else
 451 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 452 #endif
 453 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_NO_CACHE)
 454
 455 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 456 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 457 #define _PAGE_KERNEL_NC (_PAGE_BASE_NC | _PAGE_SHARED | _PAGE_WRENABLE)
 458
 459 #ifdef CONFIG_PPC_STD_MMU
 460 /* On standard PPC MMU, no user access implies kernel read/write access,
 461  * so to write-protect kernel memory we must turn on user access */
 462 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 463 #else
 464 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 465 #endif
 466
 467 #define _PAGE_IO        (_PAGE_KERNEL_NC | _PAGE_GUARDED)
 468 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 469
 470 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
 471         defined(CONFIG_KPROBES)
 472 /* We want the debuggers to be able to set breakpoints anywhere, so
 473  * don't write protect the kernel text */
 474 #define _PAGE_RAM_TEXT  _PAGE_RAM
 475 #else
 476 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 477 #endif
 478
 479 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 480 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 481 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 482 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 483 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 484 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 485 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 486
 487 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 488 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 489
 490 /*
 491  * The PowerPC can only do execute protection on a segment (256MB) basis,
 492  * not on a page basis.  So we consider execute permission the same as read.
 493  * Also, write permissions imply read permissions.
 494  * This is the closest we can get..
 495  */
 496 #define __P000  PAGE_NONE
 497 #define __P001  PAGE_READONLY_X
 498 #define __P010  PAGE_COPY
 499 #define __P011  PAGE_COPY_X
 500 #define __P100  PAGE_READONLY
 501 #define __P101  PAGE_READONLY_X
 502 #define __P110  PAGE_COPY
 503 #define __P111  PAGE_COPY_X
 504
 505 #define __S000  PAGE_NONE
 506 #define __S001  PAGE_READONLY_X
 507 #define __S010  PAGE_SHARED
 508 #define __S011  PAGE_SHARED_X
 509 #define __S100  PAGE_READONLY
 510 #define __S101  PAGE_READONLY_X
 511 #define __S110  PAGE_SHARED
 512 #define __S111  PAGE_SHARED_X
 513
 514 #ifndef __ASSEMBLY__
 515 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 516  * kernel without large page PMD support */
 517 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 518
 519 /*
 520  * Conversions between PTE values and page frame numbers.
 521  */
 522
 523 /* in some case we want to additionaly adjust where the pfn is in the pte to
 524  * allow room for more flags */
 525 #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
 526 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
 527 #else
 528 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
 529 #endif
 530
 531 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
 532 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 533
 534 #define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
 535                                         pgprot_val(prot))
 536 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 537 #endif /* __ASSEMBLY__ */
 538
 539 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 540 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 541 #define pte_clear(mm, addr, ptep) \
 542         do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
 543
 544 #define pmd_none(pmd)           (!pmd_val(pmd))
 545 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 546 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 547 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 548
 549 #ifndef __ASSEMBLY__
 550 /*
 551  * The following only work if pte_present() is true.
 552  * Undefined behaviour if not..
 553  */
 554 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 555 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 556 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 557 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 558 static inline int pte_special(pte_t pte)        { return pte_val(pte) & _PAGE_SPECIAL; }
 559
 560 static inline pte_t pte_wrprotect(pte_t pte) {
 561         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 562 static inline pte_t pte_mkclean(pte_t pte) {
 563         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 564 static inline pte_t pte_mkold(pte_t pte) {
 565         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 566
 567 static inline pte_t pte_mkwrite(pte_t pte) {
 568         pte_val(pte) |= _PAGE_RW; return pte; }
 569 static inline pte_t pte_mkdirty(pte_t pte) {
 570         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 571 static inline pte_t pte_mkyoung(pte_t pte) {
 572         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 573 static inline pte_t pte_mkspecial(pte_t pte) {
 574         pte_val(pte) |= _PAGE_SPECIAL; return pte; }
 575 static inline pgprot_t pte_pgprot(pte_t pte)
 576 {
 577         return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
 578 }
 579
 580 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 581 {
 582         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 583         return pte;
 584 }
 585
 586 /*
 587  * When flushing the tlb entry for a page, we also need to flush the hash
 588  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 589  */
 590 extern int flush_hash_pages(unsigned context, unsigned long va,
 591                             unsigned long pmdval, int count);
 592
 593 /* Add an HPTE to the hash table */
 594 extern void add_hash_page(unsigned context, unsigned long va,
 595                           unsigned long pmdval);
 596
 597 /* Flush an entry from the TLB/hash table */
 598 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
 599                              unsigned long address);
 600
 601 /*
 602  * Atomic PTE updates.
 603  *
 604  * pte_update clears and sets bit atomically, and returns
 605  * the old pte value.  In the 64-bit PTE case we lock around the
 606  * low PTE word since we expect ALL flag bits to be there
 607  */
 608 #ifndef CONFIG_PTE_64BIT
 609 static inline unsigned long pte_update(pte_t *p,
 610                                        unsigned long clr,
 611                                        unsigned long set)
 612 {
 613 #ifdef PTE_ATOMIC_UPDATES
 614         unsigned long old, tmp;
 615
 616         __asm__ __volatile__("\
 617 1:      lwarx   %0,0,%3\n\
 618         andc    %1,%0,%4\n\
 619         or      %1,%1,%5\n"
 620         PPC405_ERR77(0,%3)
 621 "       stwcx.  %1,0,%3\n\
 622         bne-    1b"
 623         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 624         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 625         : "cc" );
 626 #else /* PTE_ATOMIC_UPDATES */
 627         unsigned long old = pte_val(*p);
 628         *p = __pte((old & ~clr) | set);
 629 #endif /* !PTE_ATOMIC_UPDATES */
 630
 631 #ifdef CONFIG_44x
 632         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 633                 icache_44x_need_flush = 1;
 634 #endif
 635         return old;
 636 }
 637 #else /* CONFIG_PTE_64BIT */
 638 static inline unsigned long long pte_update(pte_t *p,
 639                                             unsigned long clr,
 640                                             unsigned long set)
 641 {
 642 #ifdef PTE_ATOMIC_UPDATES
 643         unsigned long long old;
 644         unsigned long tmp;
 645
 646         __asm__ __volatile__("\
 647 1:      lwarx   %L0,0,%4\n\
 648         lwzx    %0,0,%3\n\
 649         andc    %1,%L0,%5\n\
 650         or      %1,%1,%6\n"
 651         PPC405_ERR77(0,%3)
 652 "       stwcx.  %1,0,%4\n\
 653         bne-    1b"
 654         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 655         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 656         : "cc" );
 657 #else /* PTE_ATOMIC_UPDATES */
 658         unsigned long long old = pte_val(*p);
 659         *p = __pte((old & ~(unsigned long long)clr) | set);
 660 #endif /* !PTE_ATOMIC_UPDATES */
 661
 662 #ifdef CONFIG_44x
 663         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 664                 icache_44x_need_flush = 1;
 665 #endif
 666         return old;
 667 }
 668 #endif /* CONFIG_PTE_64BIT */
 669
 670 /*
 671  * set_pte stores a linux PTE into the linux page table.
 672  * On machines which use an MMU hash table we avoid changing the
 673  * _PAGE_HASHPTE bit.
 674  */
 675
 676 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 677                               pte_t *ptep, pte_t pte)
 678 {
 679 #if (_PAGE_HASHPTE != 0) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
 680         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 681 #elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
 682 #if _PAGE_HASHPTE != 0
 683         if (pte_val(*ptep) & _PAGE_HASHPTE)
 684                 flush_hash_entry(mm, ptep, addr);
 685 #endif
 686         __asm__ __volatile__("\
 687                 stw%U0%X0 %2,%0\n\
 688                 eieio\n\
 689                 stw%U0%X0 %L2,%1"
 690         : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
 691         : "r" (pte) : "memory");
 692 #else
 693         *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
 694                       | (pte_val(pte) & ~_PAGE_HASHPTE));
 695 #endif
 696 }
 697
 698
 699 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 700                               pte_t *ptep, pte_t pte)
 701 {
 702 #if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP) && defined(CONFIG_DEBUG_VM)
 703         WARN_ON(pte_present(*ptep));
 704 #endif
 705         __set_pte_at(mm, addr, ptep, pte);
 706 }
 707
 708 /*
 709  * 2.6 calls this without flushing the TLB entry; this is wrong
 710  * for our hash-based implementation, we fix that up here.
 711  */
 712 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 713 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 714 {
 715         unsigned long old;
 716         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 717 #if _PAGE_HASHPTE != 0
 718         if (old & _PAGE_HASHPTE) {
 719                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 720                 flush_hash_pages(context, addr, ptephys, 1);
 721         }
 722 #endif
 723         return (old & _PAGE_ACCESSED) != 0;
 724 }
 725 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 726         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 727
 728 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 729 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 730                                        pte_t *ptep)
 731 {
 732         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 733 }
 734
 735 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 736 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 737                                       pte_t *ptep)
 738 {
 739         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 740 }
 741 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 742                                            unsigned long addr, pte_t *ptep)
 743 {
 744         ptep_set_wrprotect(mm, addr, ptep);
 745 }
 746
 747
 748 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 749 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 750 {
 751         unsigned long bits = pte_val(entry) &
 752                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 753         pte_update(ptep, 0, bits);
 754 }
 755
 756 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 757 ({                                                                         \
 758         int __changed = !pte_same(*(__ptep), __entry);                     \
 759         if (__changed) {                                                   \
 760                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 761                 flush_tlb_page_nohash(__vma, __address);                   \
 762         }                                                                  \
 763         __changed;                                                         \
 764 })
 765
 766 #define __HAVE_ARCH_PTE_SAME
 767 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 768
 769 /*
 770  * Note that on Book E processors, the pmd contains the kernel virtual
 771  * (lowmem) address of the pte page.  The physical address is less useful
 772  * because everything runs with translation enabled (even the TLB miss
 773  * handler).  On everything else the pmd contains the physical address
 774  * of the pte page.  -- paulus
 775  */
 776 #ifndef CONFIG_BOOKE
 777 #define pmd_page_vaddr(pmd)     \
 778         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 779 #define pmd_page(pmd)           \
 780         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 781 #else
 782 #define pmd_page_vaddr(pmd)     \
 783         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 784 #define pmd_page(pmd)           \
 785         pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 786 #endif
 787
 788 /* to find an entry in a kernel page-table-directory */
 789 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 790
 791 /* to find an entry in a page-table-directory */
 792 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 793 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 794
 795 /* Find an entry in the third-level page table.. */
 796 #define pte_index(address)              \
 797         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 798 #define pte_offset_kernel(dir, addr)    \
 799         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 800 #define pte_offset_map(dir, addr)               \
 801         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 802 #define pte_offset_map_nested(dir, addr)        \
 803         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 804
 805 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 806 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 807
 808 /*
 809  * Encode and decode a swap entry.
 810  * Note that the bits we use in a PTE for representing a swap entry
 811  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 812  *_PAGE_HASHPTE bit (if used).  -- paulus
 813  */
 814 #define __swp_type(entry)               ((entry).val & 0x1f)
 815 #define __swp_offset(entry)             ((entry).val >> 5)
 816 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 817 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 818 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 819
 820 /* Encode and decode a nonlinear file mapping entry */
 821 #define PTE_FILE_MAX_BITS       29
 822 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 823 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 824
 825 /*
 826  * No page table caches to initialise
 827  */
 828 #define pgtable_cache_init()    do { } while (0)
 829
 830 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 831                       pmd_t **pmdp);
 832
 833 #endif /* !__ASSEMBLY__ */
 834
 835 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */