arch/powerpc/include/asm/pgtable-ppc64.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
   2 #define _ASM_POWERPC_PGTABLE_PPC64_H_
   3 /*
   4  * This file contains the functions and defines necessary to modify and use
   5  * the ppc64 hashed page table.
   6  */
   7
   8 #ifndef __ASSEMBLY__
   9 #include <linux/stddef.h>
  10 #include <asm/tlbflush.h>
  11 #endif /* __ASSEMBLY__ */
  12
  13 #ifdef CONFIG_PPC_64K_PAGES
  14 #include <asm/pgtable-ppc64-64k.h>
  15 #else
  16 #include <asm/pgtable-ppc64-4k.h>
  17 #endif
  18
  19 #define FIRST_USER_ADDRESS      0
  20
  21 /*
  22  * Size of EA range mapped by our pagetables.
  23  */
  24 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
  25                             PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
  26 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
  27
  28
  29 /* Some sanity checking */
  30 #if TASK_SIZE_USER64 > PGTABLE_RANGE
  31 #error TASK_SIZE_USER64 exceeds pagetable range
  32 #endif
  33
  34 #ifdef CONFIG_PPC_STD_MMU_64
  35 #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
  36 #error TASK_SIZE_USER64 exceeds user VSID range
  37 #endif
  38 #endif
  39
  40 /*
  41  * Define the address range of the vmalloc VM area.
  42  */
  43 #define VMALLOC_START ASM_CONST(0xD000000000000000)
  44 #define VMALLOC_SIZE  (PGTABLE_RANGE >> 1)
  45 #define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
  46
  47 /*
  48  * Define the address ranges for MMIO and IO space :
  49  *
  50  *  ISA_IO_BASE = VMALLOC_END, 64K reserved area
  51  *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
  52  * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
  53  */
  54 #define FULL_IO_SIZE    0x80000000ul
  55 #define  ISA_IO_BASE    (VMALLOC_END)
  56 #define  ISA_IO_END     (VMALLOC_END + 0x10000ul)
  57 #define  PHB_IO_BASE    (ISA_IO_END)
  58 #define  PHB_IO_END     (VMALLOC_END + FULL_IO_SIZE)
  59 #define IOREMAP_BASE    (PHB_IO_END)
  60 #define IOREMAP_END     (VMALLOC_START + PGTABLE_RANGE)
  61
  62 /*
  63  * Region IDs
  64  */
  65 #define REGION_SHIFT            60UL
  66 #define REGION_MASK             (0xfUL << REGION_SHIFT)
  67 #define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
  68
  69 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
  70 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
  71 #define VMEMMAP_REGION_ID       (0xfUL)
  72 #define USER_REGION_ID          (0UL)
  73
  74 /*
  75  * Defines the address of the vmemap area, in its own region
  76  */
  77 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
  78 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
  79
  80
  81 /*
  82  * Include the PTE bits definitions
  83  */
  84 #include <asm/pte-hash64.h>
  85 #include <asm/pte-common.h>
  86
  87
  88 #ifdef CONFIG_PPC_MM_SLICES
  89 #define HAVE_ARCH_UNMAPPED_AREA
  90 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
  91 #endif /* CONFIG_PPC_MM_SLICES */
  92
  93 #ifndef __ASSEMBLY__
  94
  95 /*
  96  * This is the default implementation of various PTE accessors, it's
  97  * used in all cases except Book3S with 64K pages where we have a
  98  * concept of sub-pages
  99  */
 100 #ifndef __real_pte
 101
 102 #ifdef STRICT_MM_TYPECHECKS
 103 #define __real_pte(e,p)         ((real_pte_t){(e)})
 104 #define __rpte_to_pte(r)        ((r).pte)
 105 #else
 106 #define __real_pte(e,p)         (e)
 107 #define __rpte_to_pte(r)        (__pte(r))
 108 #endif
 109 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
 110
 111 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
 112         do {                                                             \
 113                 index = 0;                                               \
 114                 shift = mmu_psize_defs[psize].shift;                     \
 115
 116 #define pte_iterate_hashed_end() } while(0)
 117
 118 #ifdef CONFIG_PPC_HAS_HASH_64K
 119 #define pte_pagesize_index(mm, addr, pte)       get_slice_psize(mm, addr)
 120 #else
 121 #define pte_pagesize_index(mm, addr, pte)       MMU_PAGE_4K
 122 #endif
 123
 124 #endif /* __real_pte */
 125
 126
 127 /* pte_clear moved to later in this file */
 128
 129 #define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
 130 #define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
 131
 132 #define pmd_set(pmdp, pmdval)   (pmd_val(*(pmdp)) = (pmdval))
 133 #define pmd_none(pmd)           (!pmd_val(pmd))
 134 #define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
 135                                  || (pmd_val(pmd) & PMD_BAD_BITS))
 136 #define pmd_present(pmd)        (pmd_val(pmd) != 0)
 137 #define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
 138 #define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
 139 #define pmd_page(pmd)           virt_to_page(pmd_page_vaddr(pmd))
 140
 141 #define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
 142 #define pud_none(pud)           (!pud_val(pud))
 143 #define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
 144                                  || (pud_val(pud) & PUD_BAD_BITS))
 145 #define pud_present(pud)        (pud_val(pud) != 0)
 146 #define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
 147 #define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
 148 #define pud_page(pud)           virt_to_page(pud_page_vaddr(pud))
 149
 150 #define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
 151
 152 /*
 153  * Find an entry in a page-table-directory.  We combine the address region
 154  * (the high order N bits) and the pgd portion of the address.
 155  */
 156 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
 157 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
 158
 159 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 160
 161 #define pmd_offset(pudp,addr) \
 162   (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 163
 164 #define pte_offset_kernel(dir,addr) \
 165   (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 166
 167 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 168 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
 169 #define pte_unmap(pte)                  do { } while(0)
 170 #define pte_unmap_nested(pte)           do { } while(0)
 171
 172 /* to find an entry in a kernel page-table-directory */
 173 /* This now only contains the vmalloc pages */
 174 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 175
 176
 177 /* Atomic PTE updates */
 178 static inline unsigned long pte_update(struct mm_struct *mm,
 179                                        unsigned long addr,
 180                                        pte_t *ptep, unsigned long clr,
 181                                        int huge)
 182 {
 183 #ifdef PTE_ATOMIC_UPDATES
 184         unsigned long old, tmp;
 185
 186         __asm__ __volatile__(
 187         "1:     ldarx   %0,0,%3         # pte_update\n\
 188         andi.   %1,%0,%6\n\
 189         bne-    1b \n\
 190         andc    %1,%0,%4 \n\
 191         stdcx.  %1,0,%3 \n\
 192         bne-    1b"
 193         : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
 194         : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
 195         : "cc" );
 196 #else
 197         unsigned long old = pte_val(*ptep);
 198         *ptep = __pte(old & ~clr);
 199 #endif
 200         /* huge pages use the old page table lock */
 201         if (!huge)
 202                 assert_pte_locked(mm, addr);
 203
 204 #ifdef CONFIG_PPC_STD_MMU_64
 205         if (old & _PAGE_HASHPTE)
 206                 hpte_need_flush(mm, addr, ptep, old, huge);
 207 #endif
 208
 209         return old;
 210 }
 211
 212 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 213                                               unsigned long addr, pte_t *ptep)
 214 {
 215         unsigned long old;
 216
 217         if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
 218                 return 0;
 219         old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
 220         return (old & _PAGE_ACCESSED) != 0;
 221 }
 222 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 223 #define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
 224 ({                                                                         \
 225         int __r;                                                           \
 226         __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 227         __r;                                                               \
 228 })
 229
 230 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 231 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 232                                       pte_t *ptep)
 233 {
 234         unsigned long old;
 235
 236         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 237                 return;
 238         old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
 239 }
 240
 241 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 242                                            unsigned long addr, pte_t *ptep)
 243 {
 244         unsigned long old;
 245
 246         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 247                 return;
 248         old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
 249 }
 250
 251 /*
 252  * We currently remove entries from the hashtable regardless of whether
 253  * the entry was young or dirty. The generic routines only flush if the
 254  * entry was young or dirty which is not good enough.
 255  *
 256  * We should be more intelligent about this but for the moment we override
 257  * these functions and force a tlb flush unconditionally
 258  */
 259 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 260 #define ptep_clear_flush_young(__vma, __address, __ptep)                \
 261 ({                                                                      \
 262         int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
 263                                                   __ptep);              \
 264         __young;                                                        \
 265 })
 266
 267 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 268 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 269                                        unsigned long addr, pte_t *ptep)
 270 {
 271         unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
 272         return __pte(old);
 273 }
 274
 275 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 276                              pte_t * ptep)
 277 {
 278         pte_update(mm, addr, ptep, ~0UL, 0);
 279 }
 280
 281
 282 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
 283  * function doesn't need to flush the hash entry
 284  */
 285 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 286 {
 287         unsigned long bits = pte_val(entry) &
 288                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
 289                  _PAGE_EXEC | _PAGE_HWEXEC);
 290
 291 #ifdef PTE_ATOMIC_UPDATES
 292         unsigned long old, tmp;
 293
 294         __asm__ __volatile__(
 295         "1:     ldarx   %0,0,%4\n\
 296                 andi.   %1,%0,%6\n\
 297                 bne-    1b \n\
 298                 or      %0,%3,%0\n\
 299                 stdcx.  %0,0,%4\n\
 300                 bne-    1b"
 301         :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
 302         :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
 303         :"cc");
 304 #else
 305         unsigned long old = pte_val(*ptep);
 306         *ptep = __pte(old | bits);
 307 #endif
 308 }
 309
 310 #define __HAVE_ARCH_PTE_SAME
 311 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 312
 313 #define pte_ERROR(e) \
 314         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 315 #define pmd_ERROR(e) \
 316         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 317 #define pgd_ERROR(e) \
 318         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 319
 320 /* Encode and de-code a swap entry */
 321 #define __swp_type(entry)       (((entry).val >> 1) & 0x3f)
 322 #define __swp_offset(entry)     ((entry).val >> 8)
 323 #define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
 324 #define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
 325 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val << PTE_RPN_SHIFT })
 326 #define pte_to_pgoff(pte)       (pte_val(pte) >> PTE_RPN_SHIFT)
 327 #define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
 328 #define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
 329
 330 void pgtable_cache_init(void);
 331
 332 /*
 333  * find_linux_pte returns the address of a linux pte for a given
 334  * effective address and directory.  If not found, it returns zero.
 335  */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
 336 {
 337         pgd_t *pg;
 338         pud_t *pu;
 339         pmd_t *pm;
 340         pte_t *pt = NULL;
 341
 342         pg = pgdir + pgd_index(ea);
 343         if (!pgd_none(*pg)) {
 344                 pu = pud_offset(pg, ea);
 345                 if (!pud_none(*pu)) {
 346                         pm = pmd_offset(pu, ea);
 347                         if (pmd_present(*pm))
 348                                 pt = pte_offset_kernel(pm, ea);
 349                 }
 350         }
 351         return pt;
 352 }
 353
 354 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);
 355
 356 #endif /* __ASSEMBLY__ */
 357
 358 #endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */