arch/powerpc/include/asm/pgtable-types.h

   1 #ifndef _ASM_POWERPC_PGTABLE_TYPES_H
   2 #define _ASM_POWERPC_PGTABLE_TYPES_H
   3
   4 /* PTE level */
   5 typedef struct { pte_basic_t pte; } pte_t;
   6 #define __pte(x)        ((pte_t) { (x) })
   7 static inline pte_basic_t pte_val(pte_t x)
   8 {
   9         return x.pte;
  10 }
  11
  12 /* PMD level */
  13 #ifdef CONFIG_PPC64
  14 typedef struct { unsigned long pmd; } pmd_t;
  15 #define __pmd(x)        ((pmd_t) { (x) })
  16 static inline unsigned long pmd_val(pmd_t x)
  17 {
  18         return x.pmd;
  19 }
  20
  21 /*
  22  * 64 bit hash always use 4 level table. Everybody else use 4 level
  23  * only for 4K page size.
  24  */
  25 #if defined(CONFIG_PPC_BOOK3S_64) || !defined(CONFIG_PPC_64K_PAGES)
  26 typedef struct { unsigned long pud; } pud_t;
  27 #define __pud(x)        ((pud_t) { (x) })
  28 static inline unsigned long pud_val(pud_t x)
  29 {
  30         return x.pud;
  31 }
  32 #endif /* CONFIG_PPC_BOOK3S_64 || !CONFIG_PPC_64K_PAGES */
  33 #endif /* CONFIG_PPC64 */
  34
  35 /* PGD level */
  36 typedef struct { unsigned long pgd; } pgd_t;
  37 #define __pgd(x)        ((pgd_t) { (x) })
  38 static inline unsigned long pgd_val(pgd_t x)
  39 {
  40         return x.pgd;
  41 }
  42
  43 /* Page protection bits */
  44 typedef struct { unsigned long pgprot; } pgprot_t;
  45 #define pgprot_val(x)   ((x).pgprot)
  46 #define __pgprot(x)     ((pgprot_t) { (x) })
  47
  48 /*
  49  * With hash config 64k pages additionally define a bigger "real PTE" type that
  50  * gathers the "second half" part of the PTE for pseudo 64k pages
  51  */
  52 #if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
  53 typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
  54 #else
  55 typedef struct { pte_t pte; } real_pte_t;
  56 #endif
  57 #endif /* _ASM_POWERPC_PGTABLE_TYPES_H */