arch/powerpc/include/asm/ppc-opcode.h

   1 /*
   2  * Copyright 2009 Freescale Semicondutor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  *
   9  * provides masks and opcode images for use by code generation, emulation
  10  * and for instructions that older assemblers might not know about
  11  */
  12 #ifndef _ASM_POWERPC_PPC_OPCODE_H
  13 #define _ASM_POWERPC_PPC_OPCODE_H
  14
  15 #include <linux/stringify.h>
  16 #include <asm/asm-compat.h>
  17
  18 /* sorted alphabetically */
  19 #define PPC_INST_DCBA                   0x7c0005ec
  20 #define PPC_INST_DCBA_MASK              0xfc0007fe
  21 #define PPC_INST_DCBAL                  0x7c2005ec
  22 #define PPC_INST_DCBZL                  0x7c2007ec
  23 #define PPC_INST_ISEL                   0x7c00001e
  24 #define PPC_INST_ISEL_MASK              0xfc00003e
  25 #define PPC_INST_LDARX                  0x7c0000a8
  26 #define PPC_INST_LSWI                   0x7c0004aa
  27 #define PPC_INST_LSWX                   0x7c00042a
  28 #define PPC_INST_LWARX                  0x7c000028
  29 #define PPC_INST_LWSYNC                 0x7c2004ac
  30 #define PPC_INST_LXVD2X                 0x7c000698
  31 #define PPC_INST_MCRXR                  0x7c000400
  32 #define PPC_INST_MCRXR_MASK             0xfc0007fe
  33 #define PPC_INST_MFSPR_PVR              0x7c1f42a6
  34 #define PPC_INST_MFSPR_PVR_MASK         0xfc1fffff
  35 #define PPC_INST_MSGSND                 0x7c00019c
  36 #define PPC_INST_NOP                    0x60000000
  37 #define PPC_INST_POPCNTB                0x7c0000f4
  38 #define PPC_INST_POPCNTB_MASK           0xfc0007fe
  39 #define PPC_INST_POPCNTD                0x7c0003f4
  40 #define PPC_INST_POPCNTW                0x7c0002f4
  41 #define PPC_INST_RFCI                   0x4c000066
  42 #define PPC_INST_RFDI                   0x4c00004e
  43 #define PPC_INST_RFMCI                  0x4c00004c
  44 #define PPC_INST_MFSPR_DSCR             0x7c1102a6
  45 #define PPC_INST_MFSPR_DSCR_MASK        0xfc1fffff
  46 #define PPC_INST_MTSPR_DSCR             0x7c1103a6
  47 #define PPC_INST_MTSPR_DSCR_MASK        0xfc1fffff
  48
  49 #define PPC_INST_STRING                 0x7c00042a
  50 #define PPC_INST_STRING_MASK            0xfc0007fe
  51 #define PPC_INST_STRING_GEN_MASK        0xfc00067e
  52
  53 #define PPC_INST_STSWI                  0x7c0005aa
  54 #define PPC_INST_STSWX                  0x7c00052a
  55 #define PPC_INST_STXVD2X                0x7c000798
  56 #define PPC_INST_TLBIE                  0x7c000264
  57 #define PPC_INST_TLBILX                 0x7c000024
  58 #define PPC_INST_WAIT                   0x7c00007c
  59 #define PPC_INST_TLBIVAX                0x7c000624
  60 #define PPC_INST_TLBSRX_DOT             0x7c0006a5
  61 #define PPC_INST_XXLOR                  0xf0000510
  62
  63 #define PPC_INST_NAP                    0x4c000364
  64 #define PPC_INST_SLEEP                  0x4c0003a4
  65
  66 /* A2 specific instructions */
  67 #define PPC_INST_ERATWE                 0x7c0001a6
  68 #define PPC_INST_ERATRE                 0x7c000166
  69 #define PPC_INST_ERATILX                0x7c000066
  70 #define PPC_INST_ERATIVAX               0x7c000666
  71 #define PPC_INST_ERATSX                 0x7c000126
  72 #define PPC_INST_ERATSX_DOT             0x7c000127
  73
  74 /* macros to insert fields into opcodes */
  75 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
  76 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
  77 #define __PPC_RS(s)     (((s) & 0x1f) << 21)
  78 #define __PPC_RT(s)     __PPC_RS(s)
  79 #define __PPC_XA(a)     ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
  80 #define __PPC_XB(b)     ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
  81 #define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
  82 #define __PPC_XT(s)     __PPC_XS(s)
  83 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
  84 #define __PPC_WC(w)     (((w) & 0x3) << 21)
  85 #define __PPC_WS(w)     (((w) & 0x1f) << 11)
  86
  87 /*
  88  * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
  89  * larx with EH set as an illegal instruction.
  90  */
  91 #ifdef CONFIG_PPC64
  92 #define __PPC_EH(eh)    (((eh) & 0x1) << 0)
  93 #else
  94 #define __PPC_EH(eh)    0
  95 #endif
  96
  97 /* Deal with instructions that older assemblers aren't aware of */
  98 #define PPC_DCBAL(a, b)         stringify_in_c(.long PPC_INST_DCBAL | \
  99                                         __PPC_RA(a) | __PPC_RB(b))
 100 #define PPC_DCBZL(a, b)         stringify_in_c(.long PPC_INST_DCBZL | \
 101                                         __PPC_RA(a) | __PPC_RB(b))
 102 #define PPC_LDARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LDARX | \
 103                                         __PPC_RT(t) | __PPC_RA(a) | \
 104                                         __PPC_RB(b) | __PPC_EH(eh))
 105 #define PPC_LWARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LWARX | \
 106                                         __PPC_RT(t) | __PPC_RA(a) | \
 107                                         __PPC_RB(b) | __PPC_EH(eh))
 108 #define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
 109                                         __PPC_RB(b))
 110 #define PPC_POPCNTB(a, s)       stringify_in_c(.long PPC_INST_POPCNTB | \
 111                                         __PPC_RA(a) | __PPC_RS(s))
 112 #define PPC_POPCNTD(a, s)       stringify_in_c(.long PPC_INST_POPCNTD | \
 113                                         __PPC_RA(a) | __PPC_RS(s))
 114 #define PPC_POPCNTW(a, s)       stringify_in_c(.long PPC_INST_POPCNTW | \
 115                                         __PPC_RA(a) | __PPC_RS(s))
 116 #define PPC_RFCI                stringify_in_c(.long PPC_INST_RFCI)
 117 #define PPC_RFDI                stringify_in_c(.long PPC_INST_RFDI)
 118 #define PPC_RFMCI               stringify_in_c(.long PPC_INST_RFMCI)
 119 #define PPC_TLBILX(t, a, b)     stringify_in_c(.long PPC_INST_TLBILX | \
 120                                         __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
 121 #define PPC_TLBILX_ALL(a, b)    PPC_TLBILX(0, a, b)
 122 #define PPC_TLBILX_PID(a, b)    PPC_TLBILX(1, a, b)
 123 #define PPC_TLBILX_VA(a, b)     PPC_TLBILX(3, a, b)
 124 #define PPC_WAIT(w)             stringify_in_c(.long PPC_INST_WAIT | \
 125                                         __PPC_WC(w))
 126 #define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
 127                                                __PPC_RB(a) | __PPC_RS(lp))
 128 #define PPC_TLBSRX_DOT(a,b)     stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
 129                                         __PPC_RA(a) | __PPC_RB(b))
 130 #define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
 131                                         __PPC_RA(a) | __PPC_RB(b))
 132
 133 #define PPC_ERATWE(s, a, w)     stringify_in_c(.long PPC_INST_ERATWE | \
 134                                         __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 135 #define PPC_ERATRE(s, a, w)     stringify_in_c(.long PPC_INST_ERATRE | \
 136                                         __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 137 #define PPC_ERATILX(t, a, b)    stringify_in_c(.long PPC_INST_ERATILX | \
 138                                         __PPC_T_TLB(t) | __PPC_RA(a) | \
 139                                         __PPC_RB(b))
 140 #define PPC_ERATIVAX(s, a, b)   stringify_in_c(.long PPC_INST_ERATIVAX | \
 141                                         __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
 142 #define PPC_ERATSX(t, a, w)     stringify_in_c(.long PPC_INST_ERATSX | \
 143                                         __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
 144 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
 145                                         __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
 146
 147
 148 /*
 149  * Define what the VSX XX1 form instructions will look like, then add
 150  * the 128 bit load store instructions based on that.
 151  */
 152 #define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
 153 #define VSX_XX3(t, a, b)        (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 154 #define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
 155                                                VSX_XX1((s), (a), (b)))
 156 #define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
 157                                                VSX_XX1((s), (a), (b)))
 158 #define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
 159                                                VSX_XX3((t), (a), (b)))
 160
 161 #define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
 162 #define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
 163
 164 #endif /* _ASM_POWERPC_PPC_OPCODE_H */