arch/powerpc/include/asm/tlbflush.h

   1 #ifndef _ASM_POWERPC_TLBFLUSH_H
   2 #define _ASM_POWERPC_TLBFLUSH_H
   3
   4 /*
   5  * TLB flushing:
   6  *
   7  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
   8  *  - flush_tlb_page(vma, vmaddr) flushes one page
   9  *  - local_flush_tlb_page(vmaddr) flushes one page on the local processor
  10  *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
  11  *  - flush_tlb_range(vma, start, end) flushes a range of pages
  12  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
  13  *
  14  *  This program is free software; you can redistribute it and/or
  15  *  modify it under the terms of the GNU General Public License
  16  *  as published by the Free Software Foundation; either version
  17  *  2 of the License, or (at your option) any later version.
  18  */
  19 #ifdef __KERNEL__
  20
  21 #if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
  22 /*
  23  * TLB flushing for software loaded TLB chips
  24  *
  25  * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
  26  * flush_tlb_kernel_range are best implemented as tlbia vs
  27  * specific tlbie's
  28  */
  29
  30 #include <linux/mm.h>
  31
  32 extern void _tlbie(unsigned long address, unsigned int pid);
  33 extern void _tlbil_all(void);
  34 extern void _tlbil_pid(unsigned int pid);
  35 extern void _tlbil_va(unsigned long address, unsigned int pid);
  36
  37 #if defined(CONFIG_40x) || defined(CONFIG_8xx)
  38 #define _tlbia()        asm volatile ("tlbia; sync" : : : "memory")
  39 #else /* CONFIG_44x || CONFIG_FSL_BOOKE */
  40 extern void _tlbia(void);
  41 #endif
  42
  43 static inline void local_flush_tlb_mm(struct mm_struct *mm)
  44 {
  45         _tlbil_pid(mm->context.id);
  46 }
  47
  48 static inline void flush_tlb_mm(struct mm_struct *mm)
  49 {
  50         _tlbil_pid(mm->context.id);
  51 }
  52
  53 static inline void local_flush_tlb_page(unsigned long vmaddr)
  54 {
  55         _tlbil_va(vmaddr, 0);
  56 }
  57
  58 static inline void flush_tlb_page(struct vm_area_struct *vma,
  59                                   unsigned long vmaddr)
  60 {
  61         _tlbil_va(vmaddr, vma ? vma->vm_mm->context.id : 0);
  62 }
  63
  64 static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
  65                                          unsigned long vmaddr)
  66 {
  67         flush_tlb_page(vma, vmaddr);
  68 }
  69
  70 static inline void flush_tlb_range(struct vm_area_struct *vma,
  71                                    unsigned long start, unsigned long end)
  72 {
  73         _tlbil_pid(vma->vm_mm->context.id);
  74 }
  75
  76 static inline void flush_tlb_kernel_range(unsigned long start,
  77                                           unsigned long end)
  78 {
  79         _tlbil_pid(0);
  80 }
  81
  82 #elif defined(CONFIG_PPC32)
  83 /*
  84  * TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
  85  */
  86 extern void _tlbie(unsigned long address);
  87 extern void _tlbia(void);
  88
  89 extern void flush_tlb_mm(struct mm_struct *mm);
  90 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
  91 extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
  92 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  93                             unsigned long end);
  94 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
  95 static inline void local_flush_tlb_page(unsigned long vmaddr)
  96 {
  97         flush_tlb_page(NULL, vmaddr);
  98 }
  99
 100 #else
 101 /*
 102  * TLB flushing for 64-bit has-MMU CPUs
 103  */
 104
 105 #include <linux/percpu.h>
 106 #include <asm/page.h>
 107
 108 #define PPC64_TLB_BATCH_NR 192
 109
 110 struct ppc64_tlb_batch {
 111         int                     active;
 112         unsigned long           index;
 113         struct mm_struct        *mm;
 114         real_pte_t              pte[PPC64_TLB_BATCH_NR];
 115         unsigned long           vaddr[PPC64_TLB_BATCH_NR];
 116         unsigned int            psize;
 117         int                     ssize;
 118 };
 119 DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 120
 121 extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
 122
 123 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 124                             pte_t *ptep, unsigned long pte, int huge);
 125
 126 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
 127
 128 static inline void arch_enter_lazy_mmu_mode(void)
 129 {
 130         struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
 131
 132         batch->active = 1;
 133 }
 134
 135 static inline void arch_leave_lazy_mmu_mode(void)
 136 {
 137         struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
 138
 139         if (batch->index)
 140                 __flush_tlb_pending(batch);
 141         batch->active = 0;
 142 }
 143
 144 #define arch_flush_lazy_mmu_mode()      do {} while (0)
 145
 146
 147 extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
 148                             int ssize, int local);
 149 extern void flush_hash_range(unsigned long number, int local);
 150
 151
 152 static inline void flush_tlb_mm(struct mm_struct *mm)
 153 {
 154 }
 155
 156 static inline void local_flush_tlb_page(unsigned long vmaddr)
 157 {
 158 }
 159
 160 static inline void flush_tlb_page(struct vm_area_struct *vma,
 161                                   unsigned long vmaddr)
 162 {
 163 }
 164
 165 static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
 166                                          unsigned long vmaddr)
 167 {
 168 }
 169
 170 static inline void flush_tlb_range(struct vm_area_struct *vma,
 171                                    unsigned long start, unsigned long end)
 172 {
 173 }
 174
 175 static inline void flush_tlb_kernel_range(unsigned long start,
 176                                           unsigned long end)
 177 {
 178 }
 179
 180 /* Private function for use by PCI IO mapping code */
 181 extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
 182                                      unsigned long end);
 183
 184
 185 #endif
 186
 187 #endif /*__KERNEL__ */
 188 #endif /* _ASM_POWERPC_TLBFLUSH_H */