arch/powerpc/kernel/cpu_setup_power.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18
  19 /* Entry: r3 = crap, r4 = ptr to cputable entry
  20  *
  21  * Note that we can be called twice for pseudo-PVRs
  22  */
  23 _GLOBAL(__setup_cpu_power7)
  24         mflr    r11
  25         bl      __init_hvmode_206
  26         mtlr    r11
  27         beqlr
  28         li      r0,0
  29         mtspr   SPRN_LPID,r0
  30         mfspr   r3,SPRN_LPCR
  31         bl      __init_LPCR
  32         bl      __init_TLB
  33         mtlr    r11
  34         blr
  35
  36 _GLOBAL(__restore_cpu_power7)
  37         mflr    r11
  38         mfmsr   r3
  39         rldicl. r0,r3,4,63
  40         beqlr
  41         li      r0,0
  42         mtspr   SPRN_LPID,r0
  43         mfspr   r3,SPRN_LPCR
  44         bl      __init_LPCR
  45         bl      __init_TLB
  46         mtlr    r11
  47         blr
  48
  49 _GLOBAL(__setup_cpu_power8)
  50         mflr    r11
  51         bl      __init_FSCR
  52         bl      __init_hvmode_206
  53         mtlr    r11
  54         beqlr
  55         li      r0,0
  56         mtspr   SPRN_LPID,r0
  57         mfspr   r3,SPRN_LPCR
  58         oris    r3, r3, LPCR_AIL_3@h
  59         bl      __init_LPCR
  60         bl      __init_HFSCR
  61         bl      __init_TLB
  62         mtlr    r11
  63         blr
  64
  65 _GLOBAL(__restore_cpu_power8)
  66         mflr    r11
  67         bl      __init_FSCR
  68         mfmsr   r3
  69         rldicl. r0,r3,4,63
  70         beqlr
  71         li      r0,0
  72         mtspr   SPRN_LPID,r0
  73         mfspr   r3,SPRN_LPCR
  74         oris    r3, r3, LPCR_AIL_3@h
  75         bl      __init_LPCR
  76         bl      __init_HFSCR
  77         bl      __init_TLB
  78         mtlr    r11
  79         blr
  80
  81 __init_hvmode_206:
  82         /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  83         mfmsr   r3
  84         rldicl. r0,r3,4,63
  85         bnelr
  86         ld      r5,CPU_SPEC_FEATURES(r4)
  87         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  88         xor     r5,r5,r6
  89         std     r5,CPU_SPEC_FEATURES(r4)
  90         blr
  91
  92 __init_LPCR:
  93         /* Setup a sane LPCR:
  94          *   Called with initial LPCR in R3
  95          *
  96          *   LPES = 0b01 (HSRR0/1 used for 0x500)
  97          *   PECE = 0b111
  98          *   DPFD = 4
  99          *   HDICE = 0
 100          *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
 101          *   VRMASD = 0b10000 (L=1, LP=00)
 102          *
 103          * Other bits untouched for now
 104          */
 105         li      r5,1
 106         rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
 107         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
 108         li      r5,4
 109         rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
 110         clrrdi  r3,r3,1         /* clear HDICE */
 111         li      r5,4
 112         rldimi  r3,r5, LPCR_VC_SH, 0
 113         li      r5,0x10
 114         rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
 115         mtspr   SPRN_LPCR,r3
 116         isync
 117         blr
 118
 119 __init_FSCR:
 120         mfspr   r3,SPRN_FSCR
 121         ori     r3,r3,FSCR_TAR|FSCR_DSCR
 122         mtspr   SPRN_FSCR,r3
 123         blr
 124
 125 __init_HFSCR:
 126         mfspr   r3,SPRN_HFSCR
 127         ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP
 128         mtspr   SPRN_HFSCR,r3
 129         blr
 130
 131 __init_TLB:
 132         /* Clear the TLB */
 133         li      r6,128
 134         mtctr   r6
 135         li      r7,0xc00        /* IS field = 0b11 */
 136         ptesync
 137 2:      tlbiel  r7
 138         addi    r7,r7,0x1000
 139         bdnz    2b
 140         ptesync
 141 1:      blr