arch/powerpc/kernel/cpu_setup_power.S

   1 /*
   2  * This file contains low level CPU setup functions.
   3  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  *
  10  */
  11
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/ppc_asm.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/cache.h>
  18
  19 /* Entry: r3 = crap, r4 = ptr to cputable entry
  20  *
  21  * Note that we can be called twice for pseudo-PVRs
  22  */
  23 _GLOBAL(__setup_cpu_power7)
  24         mflr    r11
  25         bl      __init_hvmode_206
  26         mtlr    r11
  27         beqlr
  28         li      r0,0
  29         mtspr   SPRN_LPID,r0
  30         mfspr   r3,SPRN_LPCR
  31         bl      __init_LPCR
  32         bl      __init_TLB
  33         mtlr    r11
  34         blr
  35
  36 _GLOBAL(__restore_cpu_power7)
  37         mflr    r11
  38         mfmsr   r3
  39         rldicl. r0,r3,4,63
  40         beqlr
  41         li      r0,0
  42         mtspr   SPRN_LPID,r0
  43         mfspr   r3,SPRN_LPCR
  44         bl      __init_LPCR
  45         bl      __init_TLB
  46         mtlr    r11
  47         blr
  48
  49 _GLOBAL(__setup_cpu_power8)
  50         mflr    r11
  51         bl      __init_FSCR
  52         bl      __init_hvmode_206
  53         mtlr    r11
  54         beqlr
  55         li      r0,0
  56         mtspr   SPRN_LPID,r0
  57         mfspr   r3,SPRN_LPCR
  58         oris    r3, r3, LPCR_AIL_3@h
  59         bl      __init_LPCR
  60         bl      __init_TLB
  61         mtlr    r11
  62         blr
  63
  64 _GLOBAL(__restore_cpu_power8)
  65         mflr    r11
  66         bl      __init_FSCR
  67         mfmsr   r3
  68         rldicl. r0,r3,4,63
  69         beqlr
  70         li      r0,0
  71         mtspr   SPRN_LPID,r0
  72         mfspr   r3,SPRN_LPCR
  73         oris    r3, r3, LPCR_AIL_3@h
  74         bl      __init_LPCR
  75         bl      __init_TLB
  76         mtlr    r11
  77         blr
  78
  79 __init_hvmode_206:
  80         /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  81         mfmsr   r3
  82         rldicl. r0,r3,4,63
  83         bnelr
  84         ld      r5,CPU_SPEC_FEATURES(r4)
  85         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  86         xor     r5,r5,r6
  87         std     r5,CPU_SPEC_FEATURES(r4)
  88         blr
  89
  90 __init_LPCR:
  91         /* Setup a sane LPCR:
  92          *   Called with initial LPCR in R3
  93          *
  94          *   LPES = 0b01 (HSRR0/1 used for 0x500)
  95          *   PECE = 0b111
  96          *   DPFD = 4
  97          *   HDICE = 0
  98          *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  99          *   VRMASD = 0b10000 (L=1, LP=00)
 100          *
 101          * Other bits untouched for now
 102          */
 103         li      r5,1
 104         rldimi  r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
 105         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
 106         li      r5,4
 107         rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
 108         clrrdi  r3,r3,1         /* clear HDICE */
 109         li      r5,4
 110         rldimi  r3,r5, LPCR_VC_SH, 0
 111         li      r5,0x10
 112         rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
 113         mtspr   SPRN_LPCR,r3
 114         isync
 115         blr
 116
 117 __init_FSCR:
 118         mfspr   r3,SPRN_FSCR
 119         ori     r3,r3,FSCR_TAR|FSCR_DSCR
 120         mtspr   SPRN_FSCR,r3
 121         blr
 122
 123 __init_TLB:
 124         /* Clear the TLB */
 125         li      r6,128
 126         mtctr   r6
 127         li      r7,0xc00        /* IS field = 0b11 */
 128         ptesync
 129 2:      tlbiel  r7
 130         addi    r7,r7,0x1000
 131         bdnz    2b
 132         ptesync
 133 1:      blr