arch/powerpc/kernel/entry_64.S

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   5  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   6  *  Adapted for Power Macintosh by Paul Mackerras.
   7  *  Low-level exception handlers and MMU support
   8  *  rewritten by Paul Mackerras.
   9  *    Copyright (C) 1996 Paul Mackerras.
  10  *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  11  *
  12  *  This file contains the system call entry code, context switch
  13  *  code, and exception/interrupt return code for PowerPC.
  14  *
  15  *  This program is free software; you can redistribute it and/or
  16  *  modify it under the terms of the GNU General Public License
  17  *  as published by the Free Software Foundation; either version
  18  *  2 of the License, or (at your option) any later version.
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <asm/unistd.h>
  23 #include <asm/processor.h>
  24 #include <asm/page.h>
  25 #include <asm/mmu.h>
  26 #include <asm/thread_info.h>
  27 #include <asm/ppc_asm.h>
  28 #include <asm/asm-offsets.h>
  29 #include <asm/cputable.h>
  30 #include <asm/firmware.h>
  31 #include <asm/bug.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/irqflags.h>
  34 #include <asm/ftrace.h>
  35 #include <asm/hw_irq.h>
  36 #include <asm/context_tracking.h>
  37 #include <asm/tm.h>
  38
  39 /*
  40  * System calls.
  41  */
  42         .section        ".toc","aw"
  43 SYS_CALL_TABLE:
  44         .tc sys_call_table[TC],sys_call_table
  45
  46 /* This value is used to mark exception frames on the stack. */
  47 exception_marker:
  48         .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
  49
  50         .section        ".text"
  51         .align 7
  52
  53         .globl system_call_common
  54 system_call_common:
  55 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  56 BEGIN_FTR_SECTION
  57         extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
  58         bne     tabort_syscall
  59 END_FTR_SECTION_IFSET(CPU_FTR_TM)
  60 #endif
  61         andi.   r10,r12,MSR_PR
  62         mr      r10,r1
  63         addi    r1,r1,-INT_FRAME_SIZE
  64         beq-    1f
  65         ld      r1,PACAKSAVE(r13)
  66 1:      std     r10,0(r1)
  67         std     r11,_NIP(r1)
  68         std     r12,_MSR(r1)
  69         std     r0,GPR0(r1)
  70         std     r10,GPR1(r1)
  71         beq     2f                      /* if from kernel mode */
  72         ACCOUNT_CPU_USER_ENTRY(r10, r11)
  73 2:      std     r2,GPR2(r1)
  74         std     r3,GPR3(r1)
  75         mfcr    r2
  76         std     r4,GPR4(r1)
  77         std     r5,GPR5(r1)
  78         std     r6,GPR6(r1)
  79         std     r7,GPR7(r1)
  80         std     r8,GPR8(r1)
  81         li      r11,0
  82         std     r11,GPR9(r1)
  83         std     r11,GPR10(r1)
  84         std     r11,GPR11(r1)
  85         std     r11,GPR12(r1)
  86         std     r11,_XER(r1)
  87         std     r11,_CTR(r1)
  88         std     r9,GPR13(r1)
  89         mflr    r10
  90         /*
  91          * This clears CR0.SO (bit 28), which is the error indication on
  92          * return from this system call.
  93          */
  94         rldimi  r2,r11,28,(63-28)
  95         li      r11,0xc01
  96         std     r10,_LINK(r1)
  97         std     r11,_TRAP(r1)
  98         std     r3,ORIG_GPR3(r1)
  99         std     r2,_CCR(r1)
 100         ld      r2,PACATOC(r13)
 101         addi    r9,r1,STACK_FRAME_OVERHEAD
 102         ld      r11,exception_marker@toc(r2)
 103         std     r11,-16(r9)             /* "regshere" marker */
 104 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
 105 BEGIN_FW_FTR_SECTION
 106         beq     33f
 107         /* if from user, see if there are any DTL entries to process */
 108         ld      r10,PACALPPACAPTR(r13)  /* get ptr to VPA */
 109         ld      r11,PACA_DTL_RIDX(r13)  /* get log read index */
 110         addi    r10,r10,LPPACA_DTLIDX
 111         LDX_BE  r10,0,r10               /* get log write index */
 112         cmpd    cr1,r11,r10
 113         beq+    cr1,33f
 114         bl      accumulate_stolen_time
 115         REST_GPR(0,r1)
 116         REST_4GPRS(3,r1)
 117         REST_2GPRS(7,r1)
 118         addi    r9,r1,STACK_FRAME_OVERHEAD
 119 33:
 120 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 121 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
 122
 123         /*
 124          * A syscall should always be called with interrupts enabled
 125          * so we just unconditionally hard-enable here. When some kind
 126          * of irq tracing is used, we additionally check that condition
 127          * is correct
 128          */
 129 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
 130         lbz     r10,PACASOFTIRQEN(r13)
 131         xori    r10,r10,1
 132 1:      tdnei   r10,0
 133         EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
 134 #endif
 135
 136 #ifdef CONFIG_PPC_BOOK3E
 137         wrteei  1
 138 #else
 139         ld      r11,PACAKMSR(r13)
 140         ori     r11,r11,MSR_EE
 141         mtmsrd  r11,1
 142 #endif /* CONFIG_PPC_BOOK3E */
 143
 144         /* We do need to set SOFTE in the stack frame or the return
 145          * from interrupt will be painful
 146          */
 147         li      r10,1
 148         std     r10,SOFTE(r1)
 149
 150         CURRENT_THREAD_INFO(r11, r1)
 151         ld      r10,TI_FLAGS(r11)
 152         andi.   r11,r10,_TIF_SYSCALL_DOTRACE
 153         bne     syscall_dotrace
 154 .Lsyscall_dotrace_cont:
 155         cmpldi  0,r0,NR_syscalls
 156         bge-    syscall_enosys
 157
 158 system_call:                    /* label this so stack traces look sane */
 159 /*
 160  * Need to vector to 32 Bit or default sys_call_table here,
 161  * based on caller's run-mode / personality.
 162  */
 163         ld      r11,SYS_CALL_TABLE@toc(2)
 164         andi.   r10,r10,_TIF_32BIT
 165         beq     15f
 166         addi    r11,r11,8       /* use 32-bit syscall entries */
 167         clrldi  r3,r3,32
 168         clrldi  r4,r4,32
 169         clrldi  r5,r5,32
 170         clrldi  r6,r6,32
 171         clrldi  r7,r7,32
 172         clrldi  r8,r8,32
 173 15:
 174         slwi    r0,r0,4
 175         ldx     r12,r11,r0      /* Fetch system call handler [ptr] */
 176         mtctr   r12
 177         bctrl                   /* Call handler */
 178
 179 .Lsyscall_exit:
 180         std     r3,RESULT(r1)
 181         CURRENT_THREAD_INFO(r12, r1)
 182
 183         ld      r8,_MSR(r1)
 184 #ifdef CONFIG_PPC_BOOK3S
 185         /* No MSR:RI on BookE */
 186         andi.   r10,r8,MSR_RI
 187         beq-    unrecov_restore
 188 #endif
 189         /*
 190          * Disable interrupts so current_thread_info()->flags can't change,
 191          * and so that we don't get interrupted after loading SRR0/1.
 192          */
 193 #ifdef CONFIG_PPC_BOOK3E
 194         wrteei  0
 195 #else
 196         ld      r10,PACAKMSR(r13)
 197         /*
 198          * For performance reasons we clear RI the same time that we
 199          * clear EE. We only need to clear RI just before we restore r13
 200          * below, but batching it with EE saves us one expensive mtmsrd call.
 201          * We have to be careful to restore RI if we branch anywhere from
 202          * here (eg syscall_exit_work).
 203          */
 204         li      r9,MSR_RI
 205         andc    r11,r10,r9
 206         mtmsrd  r11,1
 207 #endif /* CONFIG_PPC_BOOK3E */
 208
 209         ld      r9,TI_FLAGS(r12)
 210         li      r11,-_LAST_ERRNO
 211         andi.   r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
 212         bne-    syscall_exit_work
 213         cmpld   r3,r11
 214         ld      r5,_CCR(r1)
 215         bge-    syscall_error
 216 .Lsyscall_error_cont:
 217         ld      r7,_NIP(r1)
 218 BEGIN_FTR_SECTION
 219         stdcx.  r0,0,r1                 /* to clear the reservation */
 220 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
 221         andi.   r6,r8,MSR_PR
 222         ld      r4,_LINK(r1)
 223
 224         beq-    1f
 225         ACCOUNT_CPU_USER_EXIT(r11, r12)
 226         HMT_MEDIUM_LOW_HAS_PPR
 227         ld      r13,GPR13(r1)   /* only restore r13 if returning to usermode */
 228 1:      ld      r2,GPR2(r1)
 229         ld      r1,GPR1(r1)
 230         mtlr    r4
 231         mtcr    r5
 232         mtspr   SPRN_SRR0,r7
 233         mtspr   SPRN_SRR1,r8
 234         RFI
 235         b       .       /* prevent speculative execution */
 236
 237 syscall_error:
 238         oris    r5,r5,0x1000    /* Set SO bit in CR */
 239         neg     r3,r3
 240         std     r5,_CCR(r1)
 241         b       .Lsyscall_error_cont
 242
 243 /* Traced system call support */
 244 syscall_dotrace:
 245         bl      save_nvgprs
 246         addi    r3,r1,STACK_FRAME_OVERHEAD
 247         bl      do_syscall_trace_enter
 248         /*
 249          * Restore argument registers possibly just changed.
 250          * We use the return value of do_syscall_trace_enter
 251          * for the call number to look up in the table (r0).
 252          */
 253         mr      r0,r3
 254         ld      r3,GPR3(r1)
 255         ld      r4,GPR4(r1)
 256         ld      r5,GPR5(r1)
 257         ld      r6,GPR6(r1)
 258         ld      r7,GPR7(r1)
 259         ld      r8,GPR8(r1)
 260         addi    r9,r1,STACK_FRAME_OVERHEAD
 261         CURRENT_THREAD_INFO(r10, r1)
 262         ld      r10,TI_FLAGS(r10)
 263         b       .Lsyscall_dotrace_cont
 264
 265 syscall_enosys:
 266         li      r3,-ENOSYS
 267         b       .Lsyscall_exit
 268
 269 syscall_exit_work:
 270 #ifdef CONFIG_PPC_BOOK3S
 271         mtmsrd  r10,1           /* Restore RI */
 272 #endif
 273         /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
 274          If TIF_NOERROR is set, just save r3 as it is. */
 275
 276         andi.   r0,r9,_TIF_RESTOREALL
 277         beq+    0f
 278         REST_NVGPRS(r1)
 279         b       2f
 280 0:      cmpld   r3,r11          /* r10 is -LAST_ERRNO */
 281         blt+    1f
 282         andi.   r0,r9,_TIF_NOERROR
 283         bne-    1f
 284         ld      r5,_CCR(r1)
 285         neg     r3,r3
 286         oris    r5,r5,0x1000    /* Set SO bit in CR */
 287         std     r5,_CCR(r1)
 288 1:      std     r3,GPR3(r1)
 289 2:      andi.   r0,r9,(_TIF_PERSYSCALL_MASK)
 290         beq     4f
 291
 292         /* Clear per-syscall TIF flags if any are set.  */
 293
 294         li      r11,_TIF_PERSYSCALL_MASK
 295         addi    r12,r12,TI_FLAGS
 296 3:      ldarx   r10,0,r12
 297         andc    r10,r10,r11
 298         stdcx.  r10,0,r12
 299         bne-    3b
 300         subi    r12,r12,TI_FLAGS
 301
 302 4:      /* Anything else left to do? */
 303         SET_DEFAULT_THREAD_PPR(r3, r10)         /* Set thread.ppr = 3 */
 304         andi.   r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
 305         beq     ret_from_except_lite
 306
 307         /* Re-enable interrupts */
 308 #ifdef CONFIG_PPC_BOOK3E
 309         wrteei  1
 310 #else
 311         ld      r10,PACAKMSR(r13)
 312         ori     r10,r10,MSR_EE
 313         mtmsrd  r10,1
 314 #endif /* CONFIG_PPC_BOOK3E */
 315
 316         bl      save_nvgprs
 317         addi    r3,r1,STACK_FRAME_OVERHEAD
 318         bl      do_syscall_trace_leave
 319         b       ret_from_except
 320
 321 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 322 tabort_syscall:
 323         /* Firstly we need to enable TM in the kernel */
 324         mfmsr   r10
 325         li      r13, 1
 326         rldimi  r10, r13, MSR_TM_LG, 63-MSR_TM_LG
 327         mtmsrd  r10, 0
 328
 329         /* tabort, this dooms the transaction, nothing else */
 330         li      r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
 331         TABORT(R13)
 332
 333         /*
 334          * Return directly to userspace. We have corrupted user register state,
 335          * but userspace will never see that register state. Execution will
 336          * resume after the tbegin of the aborted transaction with the
 337          * checkpointed register state.
 338          */
 339         li      r13, MSR_RI
 340         andc    r10, r10, r13
 341         mtmsrd  r10, 1
 342         mtspr   SPRN_SRR0, r11
 343         mtspr   SPRN_SRR1, r12
 344
 345         rfid
 346         b       .       /* prevent speculative execution */
 347 #endif
 348
 349 /* Save non-volatile GPRs, if not already saved. */
 350 _GLOBAL(save_nvgprs)
 351         ld      r11,_TRAP(r1)
 352         andi.   r0,r11,1
 353         beqlr-
 354         SAVE_NVGPRS(r1)
 355         clrrdi  r0,r11,1
 356         std     r0,_TRAP(r1)
 357         blr
 358
 359
 360 /*
 361  * The sigsuspend and rt_sigsuspend system calls can call do_signal
 362  * and thus put the process into the stopped state where we might
 363  * want to examine its user state with ptrace.  Therefore we need
 364  * to save all the nonvolatile registers (r14 - r31) before calling
 365  * the C code.  Similarly, fork, vfork and clone need the full
 366  * register state on the stack so that it can be copied to the child.
 367  */
 368
 369 _GLOBAL(ppc_fork)
 370         bl      save_nvgprs
 371         bl      sys_fork
 372         b       .Lsyscall_exit
 373
 374 _GLOBAL(ppc_vfork)
 375         bl      save_nvgprs
 376         bl      sys_vfork
 377         b       .Lsyscall_exit
 378
 379 _GLOBAL(ppc_clone)
 380         bl      save_nvgprs
 381         bl      sys_clone
 382         b       .Lsyscall_exit
 383
 384 _GLOBAL(ppc32_swapcontext)
 385         bl      save_nvgprs
 386         bl      compat_sys_swapcontext
 387         b       .Lsyscall_exit
 388
 389 _GLOBAL(ppc64_swapcontext)
 390         bl      save_nvgprs
 391         bl      sys_swapcontext
 392         b       .Lsyscall_exit
 393
 394 _GLOBAL(ppc_switch_endian)
 395         bl      save_nvgprs
 396         bl      sys_switch_endian
 397         b       .Lsyscall_exit
 398
 399 _GLOBAL(ret_from_fork)
 400         bl      schedule_tail
 401         REST_NVGPRS(r1)
 402         li      r3,0
 403         b       .Lsyscall_exit
 404
 405 _GLOBAL(ret_from_kernel_thread)
 406         bl      schedule_tail
 407         REST_NVGPRS(r1)
 408         mtlr    r14
 409         mr      r3,r15
 410 #if defined(_CALL_ELF) && _CALL_ELF == 2
 411         mr      r12,r14
 412 #endif
 413         blrl
 414         li      r3,0
 415         b       .Lsyscall_exit
 416
 417 /*
 418  * This routine switches between two different tasks.  The process
 419  * state of one is saved on its kernel stack.  Then the state
 420  * of the other is restored from its kernel stack.  The memory
 421  * management hardware is updated to the second process's state.
 422  * Finally, we can return to the second process, via ret_from_except.
 423  * On entry, r3 points to the THREAD for the current task, r4
 424  * points to the THREAD for the new task.
 425  *
 426  * Note: there are two ways to get to the "going out" portion
 427  * of this code; either by coming in via the entry (_switch)
 428  * or via "fork" which must set up an environment equivalent
 429  * to the "_switch" path.  If you change this you'll have to change
 430  * the fork code also.
 431  *
 432  * The code which creates the new task context is in 'copy_thread'
 433  * in arch/powerpc/kernel/process.c
 434  */
 435         .align  7
 436 _GLOBAL(_switch)
 437         mflr    r0
 438         std     r0,16(r1)
 439         stdu    r1,-SWITCH_FRAME_SIZE(r1)
 440         /* r3-r13 are caller saved -- Cort */
 441         SAVE_8GPRS(14, r1)
 442         SAVE_10GPRS(22, r1)
 443         mflr    r20             /* Return to switch caller */
 444         mfmsr   r22
 445         li      r0, MSR_FP
 446 #ifdef CONFIG_VSX
 447 BEGIN_FTR_SECTION
 448         oris    r0,r0,MSR_VSX@h /* Disable VSX */
 449 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 450 #endif /* CONFIG_VSX */
 451 #ifdef CONFIG_ALTIVEC
 452 BEGIN_FTR_SECTION
 453         oris    r0,r0,MSR_VEC@h /* Disable altivec */
 454         mfspr   r24,SPRN_VRSAVE /* save vrsave register value */
 455         std     r24,THREAD_VRSAVE(r3)
 456 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 457 #endif /* CONFIG_ALTIVEC */
 458         and.    r0,r0,r22
 459         beq+    1f
 460         andc    r22,r22,r0
 461         MTMSRD(r22)
 462         isync
 463 1:      std     r20,_NIP(r1)
 464         mfcr    r23
 465         std     r23,_CCR(r1)
 466         std     r1,KSP(r3)      /* Set old stack pointer */
 467
 468 #ifdef CONFIG_PPC_BOOK3S_64
 469 BEGIN_FTR_SECTION
 470         /* Event based branch registers */
 471         mfspr   r0, SPRN_BESCR
 472         std     r0, THREAD_BESCR(r3)
 473         mfspr   r0, SPRN_EBBHR
 474         std     r0, THREAD_EBBHR(r3)
 475         mfspr   r0, SPRN_EBBRR
 476         std     r0, THREAD_EBBRR(r3)
 477 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 478 #endif
 479
 480 #ifdef CONFIG_SMP
 481         /* We need a sync somewhere here to make sure that if the
 482          * previous task gets rescheduled on another CPU, it sees all
 483          * stores it has performed on this one.
 484          */
 485         sync
 486 #endif /* CONFIG_SMP */
 487
 488         /*
 489          * If we optimise away the clear of the reservation in system
 490          * calls because we know the CPU tracks the address of the
 491          * reservation, then we need to clear it here to cover the
 492          * case that the kernel context switch path has no larx
 493          * instructions.
 494          */
 495 BEGIN_FTR_SECTION
 496         ldarx   r6,0,r1
 497 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
 498
 499 #ifdef CONFIG_PPC_BOOK3S
 500 /* Cancel all explict user streams as they will have no use after context
 501  * switch and will stop the HW from creating streams itself
 502  */
 503         DCBT_STOP_ALL_STREAM_IDS(r6)
 504 #endif
 505
 506         addi    r6,r4,-THREAD   /* Convert THREAD to 'current' */
 507         std     r6,PACACURRENT(r13)     /* Set new 'current' */
 508
 509         ld      r8,KSP(r4)      /* new stack pointer */
 510 #ifdef CONFIG_PPC_BOOK3S
 511 BEGIN_FTR_SECTION
 512         clrrdi  r6,r8,28        /* get its ESID */
 513         clrrdi  r9,r1,28        /* get current sp ESID */
 514 FTR_SECTION_ELSE
 515         clrrdi  r6,r8,40        /* get its 1T ESID */
 516         clrrdi  r9,r1,40        /* get current sp 1T ESID */
 517 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
 518         clrldi. r0,r6,2         /* is new ESID c00000000? */
 519         cmpd    cr1,r6,r9       /* or is new ESID the same as current ESID? */
 520         cror    eq,4*cr1+eq,eq
 521         beq     2f              /* if yes, don't slbie it */
 522
 523         /* Bolt in the new stack SLB entry */
 524         ld      r7,KSP_VSID(r4) /* Get new stack's VSID */
 525         oris    r0,r6,(SLB_ESID_V)@h
 526         ori     r0,r0,(SLB_NUM_BOLTED-1)@l
 527 BEGIN_FTR_SECTION
 528         li      r9,MMU_SEGSIZE_1T       /* insert B field */
 529         oris    r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
 530         rldimi  r7,r9,SLB_VSID_SSIZE_SHIFT,0
 531 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 532
 533         /* Update the last bolted SLB.  No write barriers are needed
 534          * here, provided we only update the current CPU's SLB shadow
 535          * buffer.
 536          */
 537         ld      r9,PACA_SLBSHADOWPTR(r13)
 538         li      r12,0
 539         std     r12,SLBSHADOW_STACKESID(r9)     /* Clear ESID */
 540         li      r12,SLBSHADOW_STACKVSID
 541         STDX_BE r7,r12,r9                       /* Save VSID */
 542         li      r12,SLBSHADOW_STACKESID
 543         STDX_BE r0,r12,r9                       /* Save ESID */
 544
 545         /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
 546          * we have 1TB segments, the only CPUs known to have the errata
 547          * only support less than 1TB of system memory and we'll never
 548          * actually hit this code path.
 549          */
 550
 551         slbie   r6
 552         slbie   r6              /* Workaround POWER5 < DD2.1 issue */
 553         slbmte  r7,r0
 554         isync
 555 2:
 556 #endif /* !CONFIG_PPC_BOOK3S */
 557
 558         CURRENT_THREAD_INFO(r7, r8)  /* base of new stack */
 559         /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
 560            because we don't need to leave the 288-byte ABI gap at the
 561            top of the kernel stack. */
 562         addi    r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
 563
 564         mr      r1,r8           /* start using new stack pointer */
 565         std     r7,PACAKSAVE(r13)
 566
 567 #ifdef CONFIG_PPC_BOOK3S_64
 568 BEGIN_FTR_SECTION
 569         /* Event based branch registers */
 570         ld      r0, THREAD_BESCR(r4)
 571         mtspr   SPRN_BESCR, r0
 572         ld      r0, THREAD_EBBHR(r4)
 573         mtspr   SPRN_EBBHR, r0
 574         ld      r0, THREAD_EBBRR(r4)
 575         mtspr   SPRN_EBBRR, r0
 576
 577         ld      r0,THREAD_TAR(r4)
 578         mtspr   SPRN_TAR,r0
 579 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 580 #endif
 581
 582 #ifdef CONFIG_ALTIVEC
 583 BEGIN_FTR_SECTION
 584         ld      r0,THREAD_VRSAVE(r4)
 585         mtspr   SPRN_VRSAVE,r0          /* if G4, restore VRSAVE reg */
 586 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 587 #endif /* CONFIG_ALTIVEC */
 588 #ifdef CONFIG_PPC64
 589 BEGIN_FTR_SECTION
 590         lwz     r6,THREAD_DSCR_INHERIT(r4)
 591         ld      r0,THREAD_DSCR(r4)
 592         cmpwi   r6,0
 593         bne     1f
 594         ld      r0,PACA_DSCR_DEFAULT(r13)
 595 1:
 596 BEGIN_FTR_SECTION_NESTED(70)
 597         mfspr   r8, SPRN_FSCR
 598         rldimi  r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
 599         mtspr   SPRN_FSCR, r8
 600 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
 601         cmpd    r0,r25
 602         beq     2f
 603         mtspr   SPRN_DSCR,r0
 604 2:
 605 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 606 #endif
 607
 608         ld      r6,_CCR(r1)
 609         mtcrf   0xFF,r6
 610
 611         /* r3-r13 are destroyed -- Cort */
 612         REST_8GPRS(14, r1)
 613         REST_10GPRS(22, r1)
 614
 615         /* convert old thread to its task_struct for return value */
 616         addi    r3,r3,-THREAD
 617         ld      r7,_NIP(r1)     /* Return to _switch caller in new task */
 618         mtlr    r7
 619         addi    r1,r1,SWITCH_FRAME_SIZE
 620         blr
 621
 622         .align  7
 623 _GLOBAL(ret_from_except)
 624         ld      r11,_TRAP(r1)
 625         andi.   r0,r11,1
 626         bne     ret_from_except_lite
 627         REST_NVGPRS(r1)
 628
 629 _GLOBAL(ret_from_except_lite)
 630         /*
 631          * Disable interrupts so that current_thread_info()->flags
 632          * can't change between when we test it and when we return
 633          * from the interrupt.
 634          */
 635 #ifdef CONFIG_PPC_BOOK3E
 636         wrteei  0
 637 #else
 638         ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
 639         mtmsrd  r10,1             /* Update machine state */
 640 #endif /* CONFIG_PPC_BOOK3E */
 641
 642         CURRENT_THREAD_INFO(r9, r1)
 643         ld      r3,_MSR(r1)
 644 #ifdef CONFIG_PPC_BOOK3E
 645         ld      r10,PACACURRENT(r13)
 646 #endif /* CONFIG_PPC_BOOK3E */
 647         ld      r4,TI_FLAGS(r9)
 648         andi.   r3,r3,MSR_PR
 649         beq     resume_kernel
 650 #ifdef CONFIG_PPC_BOOK3E
 651         lwz     r3,(THREAD+THREAD_DBCR0)(r10)
 652 #endif /* CONFIG_PPC_BOOK3E */
 653
 654         /* Check current_thread_info()->flags */
 655         andi.   r0,r4,_TIF_USER_WORK_MASK
 656 #ifdef CONFIG_PPC_BOOK3E
 657         bne     1f
 658         /*
 659          * Check to see if the dbcr0 register is set up to debug.
 660          * Use the internal debug mode bit to do this.
 661          */
 662         andis.  r0,r3,DBCR0_IDM@h
 663         beq     restore
 664         mfmsr   r0
 665         rlwinm  r0,r0,0,~MSR_DE /* Clear MSR.DE */
 666         mtmsr   r0
 667         mtspr   SPRN_DBCR0,r3
 668         li      r10, -1
 669         mtspr   SPRN_DBSR,r10
 670         b       restore
 671 #else
 672         beq     restore
 673 #endif
 674 1:      andi.   r0,r4,_TIF_NEED_RESCHED
 675         beq     2f
 676         bl      restore_interrupts
 677         SCHEDULE_USER
 678         b       ret_from_except_lite
 679 2:
 680 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 681         andi.   r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
 682         bne     3f              /* only restore TM if nothing else to do */
 683         addi    r3,r1,STACK_FRAME_OVERHEAD
 684         bl      restore_tm_state
 685         b       restore
 686 3:
 687 #endif
 688         bl      save_nvgprs
 689         /*
 690          * Use a non volatile GPR to save and restore our thread_info flags
 691          * across the call to restore_interrupts.
 692          */
 693         mr      r30,r4
 694         bl      restore_interrupts
 695         mr      r4,r30
 696         addi    r3,r1,STACK_FRAME_OVERHEAD
 697         bl      do_notify_resume
 698         b       ret_from_except
 699
 700 resume_kernel:
 701         /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
 702         andis.  r8,r4,_TIF_EMULATE_STACK_STORE@h
 703         beq+    1f
 704
 705         addi    r8,r1,INT_FRAME_SIZE    /* Get the kprobed function entry */
 706
 707         lwz     r3,GPR1(r1)
 708         subi    r3,r3,INT_FRAME_SIZE    /* dst: Allocate a trampoline exception frame */
 709         mr      r4,r1                   /* src:  current exception frame */
 710         mr      r1,r3                   /* Reroute the trampoline frame to r1 */
 711
 712         /* Copy from the original to the trampoline. */
 713         li      r5,INT_FRAME_SIZE/8     /* size: INT_FRAME_SIZE */
 714         li      r6,0                    /* start offset: 0 */
 715         mtctr   r5
 716 2:      ldx     r0,r6,r4
 717         stdx    r0,r6,r3
 718         addi    r6,r6,8
 719         bdnz    2b
 720
 721         /* Do real store operation to complete stwu */
 722         lwz     r5,GPR1(r1)
 723         std     r8,0(r5)
 724
 725         /* Clear _TIF_EMULATE_STACK_STORE flag */
 726         lis     r11,_TIF_EMULATE_STACK_STORE@h
 727         addi    r5,r9,TI_FLAGS
 728 0:      ldarx   r4,0,r5
 729         andc    r4,r4,r11
 730         stdcx.  r4,0,r5
 731         bne-    0b
 732 1:
 733
 734 #ifdef CONFIG_PREEMPT
 735         /* Check if we need to preempt */
 736         andi.   r0,r4,_TIF_NEED_RESCHED
 737         beq+    restore
 738         /* Check that preempt_count() == 0 and interrupts are enabled */
 739         lwz     r8,TI_PREEMPT(r9)
 740         cmpwi   cr1,r8,0
 741         ld      r0,SOFTE(r1)
 742         cmpdi   r0,0
 743         crandc  eq,cr1*4+eq,eq
 744         bne     restore
 745
 746         /*
 747          * Here we are preempting the current task. We want to make
 748          * sure we are soft-disabled first and reconcile irq state.
 749          */
 750         RECONCILE_IRQ_STATE(r3,r4)
 751 1:      bl      preempt_schedule_irq
 752
 753         /* Re-test flags and eventually loop */
 754         CURRENT_THREAD_INFO(r9, r1)
 755         ld      r4,TI_FLAGS(r9)
 756         andi.   r0,r4,_TIF_NEED_RESCHED
 757         bne     1b
 758
 759         /*
 760          * arch_local_irq_restore() from preempt_schedule_irq above may
 761          * enable hard interrupt but we really should disable interrupts
 762          * when we return from the interrupt, and so that we don't get
 763          * interrupted after loading SRR0/1.
 764          */
 765 #ifdef CONFIG_PPC_BOOK3E
 766         wrteei  0
 767 #else
 768         ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
 769         mtmsrd  r10,1             /* Update machine state */
 770 #endif /* CONFIG_PPC_BOOK3E */
 771 #endif /* CONFIG_PREEMPT */
 772
 773         .globl  fast_exc_return_irq
 774 fast_exc_return_irq:
 775 restore:
 776         /*
 777          * This is the main kernel exit path. First we check if we
 778          * are about to re-enable interrupts
 779          */
 780         ld      r5,SOFTE(r1)
 781         lbz     r6,PACASOFTIRQEN(r13)
 782         cmpwi   cr0,r5,0
 783         beq     restore_irq_off
 784
 785         /* We are enabling, were we already enabled ? Yes, just return */
 786         cmpwi   cr0,r6,1
 787         beq     cr0,do_restore
 788
 789         /*
 790          * We are about to soft-enable interrupts (we are hard disabled
 791          * at this point). We check if there's anything that needs to
 792          * be replayed first.
 793          */
 794         lbz     r0,PACAIRQHAPPENED(r13)
 795         cmpwi   cr0,r0,0
 796         bne-    restore_check_irq_replay
 797
 798         /*
 799          * Get here when nothing happened while soft-disabled, just
 800          * soft-enable and move-on. We will hard-enable as a side
 801          * effect of rfi
 802          */
 803 restore_no_replay:
 804         TRACE_ENABLE_INTS
 805         li      r0,1
 806         stb     r0,PACASOFTIRQEN(r13);
 807
 808         /*
 809          * Final return path. BookE is handled in a different file
 810          */
 811 do_restore:
 812 #ifdef CONFIG_PPC_BOOK3E
 813         b       exception_return_book3e
 814 #else
 815         /*
 816          * Clear the reservation. If we know the CPU tracks the address of
 817          * the reservation then we can potentially save some cycles and use
 818          * a larx. On POWER6 and POWER7 this is significantly faster.
 819          */
 820 BEGIN_FTR_SECTION
 821         stdcx.  r0,0,r1         /* to clear the reservation */
 822 FTR_SECTION_ELSE
 823         ldarx   r4,0,r1
 824 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
 825
 826         /*
 827          * Some code path such as load_up_fpu or altivec return directly
 828          * here. They run entirely hard disabled and do not alter the
 829          * interrupt state. They also don't use lwarx/stwcx. and thus
 830          * are known not to leave dangling reservations.
 831          */
 832         .globl  fast_exception_return
 833 fast_exception_return:
 834         ld      r3,_MSR(r1)
 835         ld      r4,_CTR(r1)
 836         ld      r0,_LINK(r1)
 837         mtctr   r4
 838         mtlr    r0
 839         ld      r4,_XER(r1)
 840         mtspr   SPRN_XER,r4
 841
 842         REST_8GPRS(5, r1)
 843
 844         andi.   r0,r3,MSR_RI
 845         beq-    unrecov_restore
 846
 847         /* Load PPR from thread struct before we clear MSR:RI */
 848 BEGIN_FTR_SECTION
 849         ld      r2,PACACURRENT(r13)
 850         ld      r2,TASKTHREADPPR(r2)
 851 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
 852
 853         /*
 854          * Clear RI before restoring r13.  If we are returning to
 855          * userspace and we take an exception after restoring r13,
 856          * we end up corrupting the userspace r13 value.
 857          */
 858         ld      r4,PACAKMSR(r13) /* Get kernel MSR without EE */
 859         andc    r4,r4,r0         /* r0 contains MSR_RI here */
 860         mtmsrd  r4,1
 861
 862 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 863         /* TM debug */
 864         std     r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
 865 #endif
 866         /*
 867          * r13 is our per cpu area, only restore it if we are returning to
 868          * userspace the value stored in the stack frame may belong to
 869          * another CPU.
 870          */
 871         andi.   r0,r3,MSR_PR
 872         beq     1f
 873 BEGIN_FTR_SECTION
 874         mtspr   SPRN_PPR,r2     /* Restore PPR */
 875 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
 876         ACCOUNT_CPU_USER_EXIT(r2, r4)
 877         REST_GPR(13, r1)
 878 1:
 879         mtspr   SPRN_SRR1,r3
 880
 881         ld      r2,_CCR(r1)
 882         mtcrf   0xFF,r2
 883         ld      r2,_NIP(r1)
 884         mtspr   SPRN_SRR0,r2
 885
 886         ld      r0,GPR0(r1)
 887         ld      r2,GPR2(r1)
 888         ld      r3,GPR3(r1)
 889         ld      r4,GPR4(r1)
 890         ld      r1,GPR1(r1)
 891
 892         rfid
 893         b       .       /* prevent speculative execution */
 894
 895 #endif /* CONFIG_PPC_BOOK3E */
 896
 897         /*
 898          * We are returning to a context with interrupts soft disabled.
 899          *
 900          * However, we may also about to hard enable, so we need to
 901          * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
 902          * or that bit can get out of sync and bad things will happen
 903          */
 904 restore_irq_off:
 905         ld      r3,_MSR(r1)
 906         lbz     r7,PACAIRQHAPPENED(r13)
 907         andi.   r0,r3,MSR_EE
 908         beq     1f
 909         rlwinm  r7,r7,0,~PACA_IRQ_HARD_DIS
 910         stb     r7,PACAIRQHAPPENED(r13)
 911 1:      li      r0,0
 912         stb     r0,PACASOFTIRQEN(r13);
 913         TRACE_DISABLE_INTS
 914         b       do_restore
 915
 916         /*
 917          * Something did happen, check if a re-emit is needed
 918          * (this also clears paca->irq_happened)
 919          */
 920 restore_check_irq_replay:
 921         /* XXX: We could implement a fast path here where we check
 922          * for irq_happened being just 0x01, in which case we can
 923          * clear it and return. That means that we would potentially
 924          * miss a decrementer having wrapped all the way around.
 925          *
 926          * Still, this might be useful for things like hash_page
 927          */
 928         bl      __check_irq_replay
 929         cmpwi   cr0,r3,0
 930         beq     restore_no_replay
 931
 932         /*
 933          * We need to re-emit an interrupt. We do so by re-using our
 934          * existing exception frame. We first change the trap value,
 935          * but we need to ensure we preserve the low nibble of it
 936          */
 937         ld      r4,_TRAP(r1)
 938         clrldi  r4,r4,60
 939         or      r4,r4,r3
 940         std     r4,_TRAP(r1)
 941
 942         /*
 943          * Then find the right handler and call it. Interrupts are
 944          * still soft-disabled and we keep them that way.
 945         */
 946         cmpwi   cr0,r3,0x500
 947         bne     1f
 948         addi    r3,r1,STACK_FRAME_OVERHEAD;
 949         bl      do_IRQ
 950         b       ret_from_except
 951 1:      cmpwi   cr0,r3,0xe60
 952         bne     1f
 953         addi    r3,r1,STACK_FRAME_OVERHEAD;
 954         bl      handle_hmi_exception
 955         b       ret_from_except
 956 1:      cmpwi   cr0,r3,0x900
 957         bne     1f
 958         addi    r3,r1,STACK_FRAME_OVERHEAD;
 959         bl      timer_interrupt
 960         b       ret_from_except
 961 #ifdef CONFIG_PPC_DOORBELL
 962 1:
 963 #ifdef CONFIG_PPC_BOOK3E
 964         cmpwi   cr0,r3,0x280
 965 #else
 966         BEGIN_FTR_SECTION
 967                 cmpwi   cr0,r3,0xe80
 968         FTR_SECTION_ELSE
 969                 cmpwi   cr0,r3,0xa00
 970         ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
 971 #endif /* CONFIG_PPC_BOOK3E */
 972         bne     1f
 973         addi    r3,r1,STACK_FRAME_OVERHEAD;
 974         bl      doorbell_exception
 975         b       ret_from_except
 976 #endif /* CONFIG_PPC_DOORBELL */
 977 1:      b       ret_from_except /* What else to do here ? */
 978
 979 unrecov_restore:
 980         addi    r3,r1,STACK_FRAME_OVERHEAD
 981         bl      unrecoverable_exception
 982         b       unrecov_restore
 983
 984 #ifdef CONFIG_PPC_RTAS
 985 /*
 986  * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
 987  * called with the MMU off.
 988  *
 989  * In addition, we need to be in 32b mode, at least for now.
 990  *
 991  * Note: r3 is an input parameter to rtas, so don't trash it...
 992  */
 993 _GLOBAL(enter_rtas)
 994         mflr    r0
 995         std     r0,16(r1)
 996         stdu    r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
 997
 998         /* Because RTAS is running in 32b mode, it clobbers the high order half
 999          * of all registers that it saves.  We therefore save those registers
1000          * RTAS might touch to the stack.  (r0, r3-r13 are caller saved)
1001          */
1002         SAVE_GPR(2, r1)                 /* Save the TOC */
1003         SAVE_GPR(13, r1)                /* Save paca */
1004         SAVE_8GPRS(14, r1)              /* Save the non-volatiles */
1005         SAVE_10GPRS(22, r1)             /* ditto */
1006
1007         mfcr    r4
1008         std     r4,_CCR(r1)
1009         mfctr   r5
1010         std     r5,_CTR(r1)
1011         mfspr   r6,SPRN_XER
1012         std     r6,_XER(r1)
1013         mfdar   r7
1014         std     r7,_DAR(r1)
1015         mfdsisr r8
1016         std     r8,_DSISR(r1)
1017
1018         /* Temporary workaround to clear CR until RTAS can be modified to
1019          * ignore all bits.
1020          */
1021         li      r0,0
1022         mtcr    r0
1023
1024 #ifdef CONFIG_BUG
1025         /* There is no way it is acceptable to get here with interrupts enabled,
1026          * check it with the asm equivalent of WARN_ON
1027          */
1028         lbz     r0,PACASOFTIRQEN(r13)
1029 1:      tdnei   r0,0
1030         EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1031 #endif
1032
1033         /* Hard-disable interrupts */
1034         mfmsr   r6
1035         rldicl  r7,r6,48,1
1036         rotldi  r7,r7,16
1037         mtmsrd  r7,1
1038
1039         /* Unfortunately, the stack pointer and the MSR are also clobbered,
1040          * so they are saved in the PACA which allows us to restore
1041          * our original state after RTAS returns.
1042          */
1043         std     r1,PACAR1(r13)
1044         std     r6,PACASAVEDMSR(r13)
1045
1046         /* Setup our real return addr */
1047         LOAD_REG_ADDR(r4,rtas_return_loc)
1048         clrldi  r4,r4,2                 /* convert to realmode address */
1049         mtlr    r4
1050
1051         li      r0,0
1052         ori     r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1053         andc    r0,r6,r0
1054
1055         li      r9,1
1056         rldicr  r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1057         ori     r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1058         andc    r6,r0,r9
1059         sync                            /* disable interrupts so SRR0/1 */
1060         mtmsrd  r0                      /* don't get trashed */
1061
1062         LOAD_REG_ADDR(r4, rtas)
1063         ld      r5,RTASENTRY(r4)        /* get the rtas->entry value */
1064         ld      r4,RTASBASE(r4)         /* get the rtas->base value */
1065
1066         mtspr   SPRN_SRR0,r5
1067         mtspr   SPRN_SRR1,r6
1068         rfid
1069         b       .       /* prevent speculative execution */
1070
1071 rtas_return_loc:
1072         FIXUP_ENDIAN
1073
1074         /* relocation is off at this point */
1075         GET_PACA(r4)
1076         clrldi  r4,r4,2                 /* convert to realmode address */
1077
1078         bcl     20,31,$+4
1079 0:      mflr    r3
1080         ld      r3,(1f-0b)(r3)          /* get &rtas_restore_regs */
1081
1082         mfmsr   r6
1083         li      r0,MSR_RI
1084         andc    r6,r6,r0
1085         sync
1086         mtmsrd  r6
1087
1088         ld      r1,PACAR1(r4)           /* Restore our SP */
1089         ld      r4,PACASAVEDMSR(r4)     /* Restore our MSR */
1090
1091         mtspr   SPRN_SRR0,r3
1092         mtspr   SPRN_SRR1,r4
1093         rfid
1094         b       .       /* prevent speculative execution */
1095
1096         .align  3
1097 1:      .llong  rtas_restore_regs
1098
1099 rtas_restore_regs:
1100         /* relocation is on at this point */
1101         REST_GPR(2, r1)                 /* Restore the TOC */
1102         REST_GPR(13, r1)                /* Restore paca */
1103         REST_8GPRS(14, r1)              /* Restore the non-volatiles */
1104         REST_10GPRS(22, r1)             /* ditto */
1105
1106         GET_PACA(r13)
1107
1108         ld      r4,_CCR(r1)
1109         mtcr    r4
1110         ld      r5,_CTR(r1)
1111         mtctr   r5
1112         ld      r6,_XER(r1)
1113         mtspr   SPRN_XER,r6
1114         ld      r7,_DAR(r1)
1115         mtdar   r7
1116         ld      r8,_DSISR(r1)
1117         mtdsisr r8
1118
1119         addi    r1,r1,RTAS_FRAME_SIZE   /* Unstack our frame */
1120         ld      r0,16(r1)               /* get return address */
1121
1122         mtlr    r0
1123         blr                             /* return to caller */
1124
1125 #endif /* CONFIG_PPC_RTAS */
1126
1127 _GLOBAL(enter_prom)
1128         mflr    r0
1129         std     r0,16(r1)
1130         stdu    r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1131
1132         /* Because PROM is running in 32b mode, it clobbers the high order half
1133          * of all registers that it saves.  We therefore save those registers
1134          * PROM might touch to the stack.  (r0, r3-r13 are caller saved)
1135          */
1136         SAVE_GPR(2, r1)
1137         SAVE_GPR(13, r1)
1138         SAVE_8GPRS(14, r1)
1139         SAVE_10GPRS(22, r1)
1140         mfcr    r10
1141         mfmsr   r11
1142         std     r10,_CCR(r1)
1143         std     r11,_MSR(r1)
1144
1145         /* Put PROM address in SRR0 */
1146         mtsrr0  r4
1147
1148         /* Setup our trampoline return addr in LR */
1149         bcl     20,31,$+4
1150 0:      mflr    r4
1151         addi    r4,r4,(1f - 0b)
1152         mtlr    r4
1153
1154         /* Prepare a 32-bit mode big endian MSR
1155          */
1156 #ifdef CONFIG_PPC_BOOK3E
1157         rlwinm  r11,r11,0,1,31
1158         mtsrr1  r11
1159         rfi
1160 #else /* CONFIG_PPC_BOOK3E */
1161         LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1162         andc    r11,r11,r12
1163         mtsrr1  r11
1164         rfid
1165 #endif /* CONFIG_PPC_BOOK3E */
1166
1167 1:      /* Return from OF */
1168         FIXUP_ENDIAN
1169
1170         /* Just make sure that r1 top 32 bits didn't get
1171          * corrupt by OF
1172          */
1173         rldicl  r1,r1,0,32
1174
1175         /* Restore the MSR (back to 64 bits) */
1176         ld      r0,_MSR(r1)
1177         MTMSRD(r0)
1178         isync
1179
1180         /* Restore other registers */
1181         REST_GPR(2, r1)
1182         REST_GPR(13, r1)
1183         REST_8GPRS(14, r1)
1184         REST_10GPRS(22, r1)
1185         ld      r4,_CCR(r1)
1186         mtcr    r4
1187
1188         addi    r1,r1,PROM_FRAME_SIZE
1189         ld      r0,16(r1)
1190         mtlr    r0
1191         blr
1192
1193 #ifdef CONFIG_FUNCTION_TRACER
1194 #ifdef CONFIG_DYNAMIC_FTRACE
1195 _GLOBAL(mcount)
1196 _GLOBAL(_mcount)
1197         blr
1198
1199 _GLOBAL_TOC(ftrace_caller)
1200         /* Taken from output of objdump from lib64/glibc */
1201         mflr    r3
1202         ld      r11, 0(r1)
1203         stdu    r1, -112(r1)
1204         std     r3, 128(r1)
1205         ld      r4, 16(r11)
1206         subi    r3, r3, MCOUNT_INSN_SIZE
1207 .globl ftrace_call
1208 ftrace_call:
1209         bl      ftrace_stub
1210         nop
1211 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1212 .globl ftrace_graph_call
1213 ftrace_graph_call:
1214         b       ftrace_graph_stub
1215 _GLOBAL(ftrace_graph_stub)
1216 #endif
1217         ld      r0, 128(r1)
1218         mtlr    r0
1219         addi    r1, r1, 112
1220 _GLOBAL(ftrace_stub)
1221         blr
1222 #else
1223 _GLOBAL_TOC(_mcount)
1224         /* Taken from output of objdump from lib64/glibc */
1225         mflr    r3
1226         ld      r11, 0(r1)
1227         stdu    r1, -112(r1)
1228         std     r3, 128(r1)
1229         ld      r4, 16(r11)
1230
1231         subi    r3, r3, MCOUNT_INSN_SIZE
1232         LOAD_REG_ADDR(r5,ftrace_trace_function)
1233         ld      r5,0(r5)
1234         ld      r5,0(r5)
1235         mtctr   r5
1236         bctrl
1237         nop
1238
1239
1240 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1241         b       ftrace_graph_caller
1242 #endif
1243         ld      r0, 128(r1)
1244         mtlr    r0
1245         addi    r1, r1, 112
1246 _GLOBAL(ftrace_stub)
1247         blr
1248
1249 #endif /* CONFIG_DYNAMIC_FTRACE */
1250
1251 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1252 _GLOBAL(ftrace_graph_caller)
1253         /* load r4 with local address */
1254         ld      r4, 128(r1)
1255         subi    r4, r4, MCOUNT_INSN_SIZE
1256
1257         /* Grab the LR out of the caller stack frame */
1258         ld      r11, 112(r1)
1259         ld      r3, 16(r11)
1260
1261         bl      prepare_ftrace_return
1262         nop
1263
1264         /*
1265          * prepare_ftrace_return gives us the address we divert to.
1266          * Change the LR in the callers stack frame to this.
1267          */
1268         ld      r11, 112(r1)
1269         std     r3, 16(r11)
1270
1271         ld      r0, 128(r1)
1272         mtlr    r0
1273         addi    r1, r1, 112
1274         blr
1275
1276 _GLOBAL(return_to_handler)
1277         /* need to save return values */
1278         std     r4,  -32(r1)
1279         std     r3,  -24(r1)
1280         /* save TOC */
1281         std     r2,  -16(r1)
1282         std     r31, -8(r1)
1283         mr      r31, r1
1284         stdu    r1, -112(r1)
1285
1286         /*
1287          * We might be called from a module.
1288          * Switch to our TOC to run inside the core kernel.
1289          */
1290         ld      r2, PACATOC(r13)
1291
1292         bl      ftrace_return_to_handler
1293         nop
1294
1295         /* return value has real return address */
1296         mtlr    r3
1297
1298         ld      r1, 0(r1)
1299         ld      r4,  -32(r1)
1300         ld      r3,  -24(r1)
1301         ld      r2,  -16(r1)
1302         ld      r31, -8(r1)
1303
1304         /* Jump back to real return address */
1305         blr
1306 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1307 #endif /* CONFIG_FUNCTION_TRACER */