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Merge tag 'dlm-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm
[deliverable/linux.git] / arch / powerpc / kernel / exceptions-64e.S
1 /*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/threads.h>
13 #include <asm/reg.h>
14 #include <asm/page.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
22 #include <asm/bug.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
26 #include <asm/mmu.h>
27 #include <asm/hw_irq.h>
28 #include <asm/kvm_asm.h>
29 #include <asm/kvm_booke_hv_asm.h>
30
31 /* XXX This will ultimately add space for a special exception save
32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
33 * when taking special interrupts. For now we don't support that,
34 * special interrupts from within a non-standard level will probably
35 * blow you up
36 */
37 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
38
39 /* Exception prolog code for all exceptions */
40 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
41 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
42 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
43 std r10,PACA_EX##type+EX_R10(r13); \
44 std r11,PACA_EX##type+EX_R11(r13); \
45 PROLOG_STORE_RESTORE_SCRATCH_##type; \
46 mfcr r10; /* save CR */ \
47 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
48 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
49 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
50 addition; /* additional code for that exc. */ \
51 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
52 type##_SET_KSTACK; /* get special stack if necessary */\
53 andi. r10,r11,MSR_PR; /* save stack pointer */ \
54 beq 1f; /* branch around if supervisor */ \
55 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
56 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
57 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
58 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
59
60 /* Exception type-specific macros */
61 #define GEN_SET_KSTACK \
62 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
63 #define SPRN_GEN_SRR0 SPRN_SRR0
64 #define SPRN_GEN_SRR1 SPRN_SRR1
65
66 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
67 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
68 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
69
70 #define CRIT_SET_KSTACK \
71 ld r1,PACA_CRIT_STACK(r13); \
72 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
73 #define SPRN_CRIT_SRR0 SPRN_CSRR0
74 #define SPRN_CRIT_SRR1 SPRN_CSRR1
75
76 #define DBG_SET_KSTACK \
77 ld r1,PACA_DBG_STACK(r13); \
78 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
79 #define SPRN_DBG_SRR0 SPRN_DSRR0
80 #define SPRN_DBG_SRR1 SPRN_DSRR1
81
82 #define MC_SET_KSTACK \
83 ld r1,PACA_MC_STACK(r13); \
84 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
85 #define SPRN_MC_SRR0 SPRN_MCSRR0
86 #define SPRN_MC_SRR1 SPRN_MCSRR1
87
88 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
89 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
90
91 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
92 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
93
94 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
95 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
96
97 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
98 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
99
100 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
101 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
102
103 /*
104 * Store user-visible scratch in PACA exception slots and restore proper value
105 */
106 #define PROLOG_STORE_RESTORE_SCRATCH_GEN
107 #define PROLOG_STORE_RESTORE_SCRATCH_GDBELL
108 #define PROLOG_STORE_RESTORE_SCRATCH_DBG
109 #define PROLOG_STORE_RESTORE_SCRATCH_MC
110
111 #define PROLOG_STORE_RESTORE_SCRATCH_CRIT \
112 mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \
113 std r10,PACA_EXCRIT+EX_R13(r13); \
114 ld r11,PACA_SPRG3(r13); \
115 mtspr SPRN_SPRG_CRIT_SCRATCH,r11;
116
117 /* Variants of the "addition" argument for the prolog
118 */
119 #define PROLOG_ADDITION_NONE_GEN(n)
120 #define PROLOG_ADDITION_NONE_GDBELL(n)
121 #define PROLOG_ADDITION_NONE_CRIT(n)
122 #define PROLOG_ADDITION_NONE_DBG(n)
123 #define PROLOG_ADDITION_NONE_MC(n)
124
125 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
126 lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
127 cmpwi cr0,r10,0; /* yes -> go out of line */ \
128 beq masked_interrupt_book3e_##n
129
130 #define PROLOG_ADDITION_2REGS_GEN(n) \
131 std r14,PACA_EXGEN+EX_R14(r13); \
132 std r15,PACA_EXGEN+EX_R15(r13)
133
134 #define PROLOG_ADDITION_1REG_GEN(n) \
135 std r14,PACA_EXGEN+EX_R14(r13);
136
137 #define PROLOG_ADDITION_2REGS_CRIT(n) \
138 std r14,PACA_EXCRIT+EX_R14(r13); \
139 std r15,PACA_EXCRIT+EX_R15(r13)
140
141 #define PROLOG_ADDITION_2REGS_DBG(n) \
142 std r14,PACA_EXDBG+EX_R14(r13); \
143 std r15,PACA_EXDBG+EX_R15(r13)
144
145 #define PROLOG_ADDITION_2REGS_MC(n) \
146 std r14,PACA_EXMC+EX_R14(r13); \
147 std r15,PACA_EXMC+EX_R15(r13)
148
149
150 /* Core exception code for all exceptions except TLB misses.
151 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
152 */
153 #define EXCEPTION_COMMON(n, excf, ints) \
154 exc_##n##_common: \
155 std r0,GPR0(r1); /* save r0 in stackframe */ \
156 std r2,GPR2(r1); /* save r2 in stackframe */ \
157 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
158 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
159 std r9,GPR9(r1); /* save r9 in stackframe */ \
160 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
161 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
162 beq 2f; /* if from kernel mode */ \
163 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
164 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
165 ld r4,excf+EX_R11(r13); /* get back r11 */ \
166 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
167 std r12,GPR12(r1); /* save r12 in stackframe */ \
168 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
169 mflr r6; /* save LR in stackframe */ \
170 mfctr r7; /* save CTR in stackframe */ \
171 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
172 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
173 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
174 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
175 ld r12,exception_marker@toc(r2); \
176 li r0,0; \
177 std r3,GPR10(r1); /* save r10 to stackframe */ \
178 std r4,GPR11(r1); /* save r11 to stackframe */ \
179 std r5,GPR13(r1); /* save it to stackframe */ \
180 std r6,_LINK(r1); \
181 std r7,_CTR(r1); \
182 std r8,_XER(r1); \
183 li r3,(n)+1; /* indicate partial regs in trap */ \
184 std r9,0(r1); /* store stack frame back link */ \
185 std r10,_CCR(r1); /* store orig CR in stackframe */ \
186 std r9,GPR1(r1); /* store stack frame back link */ \
187 std r11,SOFTE(r1); /* and save it to stackframe */ \
188 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
189 std r3,_TRAP(r1); /* set trap number */ \
190 std r0,RESULT(r1); /* clear regs->result */ \
191 ints;
192
193 /* Variants for the "ints" argument. This one does nothing when we want
194 * to keep interrupts in their original state
195 */
196 #define INTS_KEEP
197
198 /* This second version is meant for exceptions that don't immediately
199 * hard-enable. We set a bit in paca->irq_happened to ensure that
200 * a subsequent call to arch_local_irq_restore() will properly
201 * hard-enable and avoid the fast-path, and then reconcile irq state.
202 */
203 #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4)
204
205 /* This is called by exceptions that used INTS_KEEP (that did not touch
206 * irq indicators in the PACA). This will restore MSR:EE to it's previous
207 * value
208 *
209 * XXX In the long run, we may want to open-code it in order to separate the
210 * load from the wrtee, thus limiting the latency caused by the dependency
211 * but at this point, I'll favor code clarity until we have a near to final
212 * implementation
213 */
214 #define INTS_RESTORE_HARD \
215 ld r11,_MSR(r1); \
216 wrtee r11;
217
218 /* XXX FIXME: Restore r14/r15 when necessary */
219 #define BAD_STACK_TRAMPOLINE(n) \
220 exc_##n##_bad_stack: \
221 li r1,(n); /* get exception number */ \
222 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
223 b bad_stack_book3e; /* bad stack error */
224
225 /* WARNING: If you change the layout of this stub, make sure you chcek
226 * the debug exception handler which handles single stepping
227 * into exceptions from userspace, and the MM code in
228 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
229 * and would need to be updated if that branch is moved
230 */
231 #define EXCEPTION_STUB(loc, label) \
232 . = interrupt_base_book3e + loc; \
233 nop; /* To make debug interrupts happy */ \
234 b exc_##label##_book3e;
235
236 #define ACK_NONE(r)
237 #define ACK_DEC(r) \
238 lis r,TSR_DIS@h; \
239 mtspr SPRN_TSR,r
240 #define ACK_FIT(r) \
241 lis r,TSR_FIS@h; \
242 mtspr SPRN_TSR,r
243
244 /* Used by asynchronous interrupt that may happen in the idle loop.
245 *
246 * This check if the thread was in the idle loop, and if yes, returns
247 * to the caller rather than the PC. This is to avoid a race if
248 * interrupts happen before the wait instruction.
249 */
250 #define CHECK_NAPPING() \
251 CURRENT_THREAD_INFO(r11, r1); \
252 ld r10,TI_LOCAL_FLAGS(r11); \
253 andi. r9,r10,_TLF_NAPPING; \
254 beq+ 1f; \
255 ld r8,_LINK(r1); \
256 rlwinm r7,r10,0,~_TLF_NAPPING; \
257 std r8,_NIP(r1); \
258 std r7,TI_LOCAL_FLAGS(r11); \
259 1:
260
261
262 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
263 START_EXCEPTION(label); \
264 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
265 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \
266 ack(r8); \
267 CHECK_NAPPING(); \
268 addi r3,r1,STACK_FRAME_OVERHEAD; \
269 bl hdlr; \
270 b .ret_from_except_lite;
271
272 /* This value is used to mark exception frames on the stack. */
273 .section ".toc","aw"
274 exception_marker:
275 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
276
277
278 /*
279 * And here we have the exception vectors !
280 */
281
282 .text
283 .balign 0x1000
284 .globl interrupt_base_book3e
285 interrupt_base_book3e: /* fake trap */
286 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
287 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
288 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
289 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
290 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
291 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
292 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
293 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
294 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
295 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
296 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
297 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
298 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
299 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
300 EXCEPTION_STUB(0x1c0, data_tlb_miss)
301 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
302 EXCEPTION_STUB(0x200, altivec_unavailable) /* 0x0f20 */
303 EXCEPTION_STUB(0x220, altivec_assist) /* 0x1700 */
304 EXCEPTION_STUB(0x260, perfmon)
305 EXCEPTION_STUB(0x280, doorbell)
306 EXCEPTION_STUB(0x2a0, doorbell_crit)
307 EXCEPTION_STUB(0x2c0, guest_doorbell)
308 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
309 EXCEPTION_STUB(0x300, hypercall)
310 EXCEPTION_STUB(0x320, ehpriv)
311
312 .globl interrupt_end_book3e
313 interrupt_end_book3e:
314
315 /* Critical Input Interrupt */
316 START_EXCEPTION(critical_input);
317 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
318 PROLOG_ADDITION_NONE)
319 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
320 // bl special_reg_save_crit
321 // CHECK_NAPPING();
322 // addi r3,r1,STACK_FRAME_OVERHEAD
323 // bl .critical_exception
324 // b ret_from_crit_except
325 b .
326
327 /* Machine Check Interrupt */
328 START_EXCEPTION(machine_check);
329 MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
330 PROLOG_ADDITION_NONE)
331 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
332 // bl special_reg_save_mc
333 // addi r3,r1,STACK_FRAME_OVERHEAD
334 // CHECK_NAPPING();
335 // bl .machine_check_exception
336 // b ret_from_mc_except
337 b .
338
339 /* Data Storage Interrupt */
340 START_EXCEPTION(data_storage)
341 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
342 PROLOG_ADDITION_2REGS)
343 mfspr r14,SPRN_DEAR
344 mfspr r15,SPRN_ESR
345 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
346 b storage_fault_common
347
348 /* Instruction Storage Interrupt */
349 START_EXCEPTION(instruction_storage);
350 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
351 PROLOG_ADDITION_2REGS)
352 li r15,0
353 mr r14,r10
354 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
355 b storage_fault_common
356
357 /* External Input Interrupt */
358 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
359 external_input, .do_IRQ, ACK_NONE)
360
361 /* Alignment */
362 START_EXCEPTION(alignment);
363 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
364 PROLOG_ADDITION_2REGS)
365 mfspr r14,SPRN_DEAR
366 mfspr r15,SPRN_ESR
367 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
368 b alignment_more /* no room, go out of line */
369
370 /* Program Interrupt */
371 START_EXCEPTION(program);
372 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
373 PROLOG_ADDITION_1REG)
374 mfspr r14,SPRN_ESR
375 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
376 std r14,_DSISR(r1)
377 addi r3,r1,STACK_FRAME_OVERHEAD
378 ld r14,PACA_EXGEN+EX_R14(r13)
379 bl .save_nvgprs
380 bl .program_check_exception
381 b .ret_from_except
382
383 /* Floating Point Unavailable Interrupt */
384 START_EXCEPTION(fp_unavailable);
385 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
386 PROLOG_ADDITION_NONE)
387 /* we can probably do a shorter exception entry for that one... */
388 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
389 ld r12,_MSR(r1)
390 andi. r0,r12,MSR_PR;
391 beq- 1f
392 bl .load_up_fpu
393 b fast_exception_return
394 1: INTS_DISABLE
395 bl .save_nvgprs
396 addi r3,r1,STACK_FRAME_OVERHEAD
397 bl .kernel_fp_unavailable_exception
398 b .ret_from_except
399
400 /* Altivec Unavailable Interrupt */
401 START_EXCEPTION(altivec_unavailable);
402 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL,
403 PROLOG_ADDITION_NONE)
404 /* we can probably do a shorter exception entry for that one... */
405 EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
406 #ifdef CONFIG_ALTIVEC
407 BEGIN_FTR_SECTION
408 ld r12,_MSR(r1)
409 andi. r0,r12,MSR_PR;
410 beq- 1f
411 bl .load_up_altivec
412 b fast_exception_return
413 1:
414 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
415 #endif
416 INTS_DISABLE
417 bl .save_nvgprs
418 addi r3,r1,STACK_FRAME_OVERHEAD
419 bl .altivec_unavailable_exception
420 b .ret_from_except
421
422 /* AltiVec Assist */
423 START_EXCEPTION(altivec_assist);
424 NORMAL_EXCEPTION_PROLOG(0x220,
425 BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST,
426 PROLOG_ADDITION_NONE)
427 EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
428 bl .save_nvgprs
429 addi r3,r1,STACK_FRAME_OVERHEAD
430 #ifdef CONFIG_ALTIVEC
431 BEGIN_FTR_SECTION
432 bl .altivec_assist_exception
433 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
434 #else
435 bl .unknown_exception
436 #endif
437 b .ret_from_except
438
439
440 /* Decrementer Interrupt */
441 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
442 decrementer, .timer_interrupt, ACK_DEC)
443
444 /* Fixed Interval Timer Interrupt */
445 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
446 fixed_interval, .unknown_exception, ACK_FIT)
447
448 /* Watchdog Timer Interrupt */
449 START_EXCEPTION(watchdog);
450 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
451 PROLOG_ADDITION_NONE)
452 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
453 // bl special_reg_save_crit
454 // CHECK_NAPPING();
455 // addi r3,r1,STACK_FRAME_OVERHEAD
456 // bl .unknown_exception
457 // b ret_from_crit_except
458 b .
459
460 /* System Call Interrupt */
461 START_EXCEPTION(system_call)
462 mr r9,r13 /* keep a copy of userland r13 */
463 mfspr r11,SPRN_SRR0 /* get return address */
464 mfspr r12,SPRN_SRR1 /* get previous MSR */
465 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
466 b system_call_common
467
468 /* Auxiliary Processor Unavailable Interrupt */
469 START_EXCEPTION(ap_unavailable);
470 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
471 PROLOG_ADDITION_NONE)
472 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
473 bl .save_nvgprs
474 addi r3,r1,STACK_FRAME_OVERHEAD
475 bl .unknown_exception
476 b .ret_from_except
477
478 /* Debug exception as a critical interrupt*/
479 START_EXCEPTION(debug_crit);
480 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
481 PROLOG_ADDITION_2REGS)
482
483 /*
484 * If there is a single step or branch-taken exception in an
485 * exception entry sequence, it was probably meant to apply to
486 * the code where the exception occurred (since exception entry
487 * doesn't turn off DE automatically). We simulate the effect
488 * of turning off DE on entry to an exception handler by turning
489 * off DE in the CSRR1 value and clearing the debug status.
490 */
491
492 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
493 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
494 beq+ 1f
495
496 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
497 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
498 cmpld cr0,r10,r14
499 cmpld cr1,r10,r15
500 blt+ cr0,1f
501 bge+ cr1,1f
502
503 /* here it looks like we got an inappropriate debug exception. */
504 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
505 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
506 mtspr SPRN_DBSR,r14
507 mtspr SPRN_CSRR1,r11
508 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
509 ld r1,PACA_EXCRIT+EX_R1(r13)
510 ld r14,PACA_EXCRIT+EX_R14(r13)
511 ld r15,PACA_EXCRIT+EX_R15(r13)
512 mtcr r10
513 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
514 ld r11,PACA_EXCRIT+EX_R11(r13)
515 ld r13,PACA_EXCRIT+EX_R13(r13)
516 rfci
517
518 /* Normal debug exception */
519 /* XXX We only handle coming from userspace for now since we can't
520 * quite save properly an interrupted kernel state yet
521 */
522 1: andi. r14,r11,MSR_PR; /* check for userspace again */
523 beq kernel_dbg_exc; /* if from kernel mode */
524
525 /* Now we mash up things to make it look like we are coming on a
526 * normal exception
527 */
528 ld r15,PACA_EXCRIT+EX_R13(r13)
529 mtspr SPRN_SPRG_GEN_SCRATCH,r15
530 mfspr r14,SPRN_DBSR
531 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
532 std r14,_DSISR(r1)
533 addi r3,r1,STACK_FRAME_OVERHEAD
534 mr r4,r14
535 ld r14,PACA_EXCRIT+EX_R14(r13)
536 ld r15,PACA_EXCRIT+EX_R15(r13)
537 bl .save_nvgprs
538 bl .DebugException
539 b .ret_from_except
540
541 kernel_dbg_exc:
542 b . /* NYI */
543
544 /* Debug exception as a debug interrupt*/
545 START_EXCEPTION(debug_debug);
546 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
547 PROLOG_ADDITION_2REGS)
548
549 /*
550 * If there is a single step or branch-taken exception in an
551 * exception entry sequence, it was probably meant to apply to
552 * the code where the exception occurred (since exception entry
553 * doesn't turn off DE automatically). We simulate the effect
554 * of turning off DE on entry to an exception handler by turning
555 * off DE in the DSRR1 value and clearing the debug status.
556 */
557
558 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
559 andis. r15,r14,(DBSR_IC|DBSR_BT)@h
560 beq+ 1f
561
562 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
563 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
564 cmpld cr0,r10,r14
565 cmpld cr1,r10,r15
566 blt+ cr0,1f
567 bge+ cr1,1f
568
569 /* here it looks like we got an inappropriate debug exception. */
570 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
571 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
572 mtspr SPRN_DBSR,r14
573 mtspr SPRN_DSRR1,r11
574 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
575 ld r1,PACA_EXDBG+EX_R1(r13)
576 ld r14,PACA_EXDBG+EX_R14(r13)
577 ld r15,PACA_EXDBG+EX_R15(r13)
578 mtcr r10
579 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
580 ld r11,PACA_EXDBG+EX_R11(r13)
581 mfspr r13,SPRN_SPRG_DBG_SCRATCH
582 rfdi
583
584 /* Normal debug exception */
585 /* XXX We only handle coming from userspace for now since we can't
586 * quite save properly an interrupted kernel state yet
587 */
588 1: andi. r14,r11,MSR_PR; /* check for userspace again */
589 beq kernel_dbg_exc; /* if from kernel mode */
590
591 /* Now we mash up things to make it look like we are coming on a
592 * normal exception
593 */
594 mfspr r15,SPRN_SPRG_DBG_SCRATCH
595 mtspr SPRN_SPRG_GEN_SCRATCH,r15
596 mfspr r14,SPRN_DBSR
597 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
598 std r14,_DSISR(r1)
599 addi r3,r1,STACK_FRAME_OVERHEAD
600 mr r4,r14
601 ld r14,PACA_EXDBG+EX_R14(r13)
602 ld r15,PACA_EXDBG+EX_R15(r13)
603 bl .save_nvgprs
604 bl .DebugException
605 b .ret_from_except
606
607 START_EXCEPTION(perfmon);
608 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
609 PROLOG_ADDITION_NONE)
610 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
611 CHECK_NAPPING()
612 addi r3,r1,STACK_FRAME_OVERHEAD
613 bl .performance_monitor_exception
614 b .ret_from_except_lite
615
616 /* Doorbell interrupt */
617 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
618 doorbell, .doorbell_exception, ACK_NONE)
619
620 /* Doorbell critical Interrupt */
621 START_EXCEPTION(doorbell_crit);
622 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
623 PROLOG_ADDITION_NONE)
624 // EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
625 // bl special_reg_save_crit
626 // CHECK_NAPPING();
627 // addi r3,r1,STACK_FRAME_OVERHEAD
628 // bl .doorbell_critical_exception
629 // b ret_from_crit_except
630 b .
631
632 /*
633 * Guest doorbell interrupt
634 * This general exception use GSRRx save/restore registers
635 */
636 START_EXCEPTION(guest_doorbell);
637 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
638 PROLOG_ADDITION_NONE)
639 EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
640 addi r3,r1,STACK_FRAME_OVERHEAD
641 bl .save_nvgprs
642 INTS_RESTORE_HARD
643 bl .unknown_exception
644 b .ret_from_except
645
646 /* Guest Doorbell critical Interrupt */
647 START_EXCEPTION(guest_doorbell_crit);
648 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
649 PROLOG_ADDITION_NONE)
650 // EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
651 // bl special_reg_save_crit
652 // CHECK_NAPPING();
653 // addi r3,r1,STACK_FRAME_OVERHEAD
654 // bl .guest_doorbell_critical_exception
655 // b ret_from_crit_except
656 b .
657
658 /* Hypervisor call */
659 START_EXCEPTION(hypercall);
660 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
661 PROLOG_ADDITION_NONE)
662 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
663 addi r3,r1,STACK_FRAME_OVERHEAD
664 bl .save_nvgprs
665 INTS_RESTORE_HARD
666 bl .unknown_exception
667 b .ret_from_except
668
669 /* Embedded Hypervisor priviledged */
670 START_EXCEPTION(ehpriv);
671 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
672 PROLOG_ADDITION_NONE)
673 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
674 addi r3,r1,STACK_FRAME_OVERHEAD
675 bl .save_nvgprs
676 INTS_RESTORE_HARD
677 bl .unknown_exception
678 b .ret_from_except
679
680 /*
681 * An interrupt came in while soft-disabled; We mark paca->irq_happened
682 * accordingly and if the interrupt is level sensitive, we hard disable
683 */
684
685 .macro masked_interrupt_book3e paca_irq full_mask
686 lbz r10,PACAIRQHAPPENED(r13)
687 ori r10,r10,\paca_irq
688 stb r10,PACAIRQHAPPENED(r13)
689
690 .if \full_mask == 1
691 rldicl r10,r11,48,1 /* clear MSR_EE */
692 rotldi r11,r10,16
693 mtspr SPRN_SRR1,r11
694 .endif
695
696 lwz r11,PACA_EXGEN+EX_CR(r13)
697 mtcr r11
698 ld r10,PACA_EXGEN+EX_R10(r13)
699 ld r11,PACA_EXGEN+EX_R11(r13)
700 mfspr r13,SPRN_SPRG_GEN_SCRATCH
701 rfi
702 b .
703 .endm
704
705 masked_interrupt_book3e_0x500:
706 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
707 masked_interrupt_book3e PACA_IRQ_EE 1
708
709 masked_interrupt_book3e_0x900:
710 ACK_DEC(r10);
711 masked_interrupt_book3e PACA_IRQ_DEC 0
712
713 masked_interrupt_book3e_0x980:
714 ACK_FIT(r10);
715 masked_interrupt_book3e PACA_IRQ_DEC 0
716
717 masked_interrupt_book3e_0x280:
718 masked_interrupt_book3e_0x2c0:
719 masked_interrupt_book3e PACA_IRQ_DBELL 0
720
721 /*
722 * Called from arch_local_irq_enable when an interrupt needs
723 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
724 * to indicate the kind of interrupt. MSR:EE is already off.
725 * We generate a stackframe like if a real interrupt had happened.
726 *
727 * Note: While MSR:EE is off, we need to make sure that _MSR
728 * in the generated frame has EE set to 1 or the exception
729 * handler will not properly re-enable them.
730 */
731 _GLOBAL(__replay_interrupt)
732 /* We are going to jump to the exception common code which
733 * will retrieve various register values from the PACA which
734 * we don't give a damn about.
735 */
736 mflr r10
737 mfmsr r11
738 mfcr r4
739 mtspr SPRN_SPRG_GEN_SCRATCH,r13;
740 std r1,PACA_EXGEN+EX_R1(r13);
741 stw r4,PACA_EXGEN+EX_CR(r13);
742 ori r11,r11,MSR_EE
743 subi r1,r1,INT_FRAME_SIZE;
744 cmpwi cr0,r3,0x500
745 beq exc_0x500_common
746 cmpwi cr0,r3,0x900
747 beq exc_0x900_common
748 cmpwi cr0,r3,0x280
749 beq exc_0x280_common
750 blr
751
752
753 /*
754 * This is called from 0x300 and 0x400 handlers after the prologs with
755 * r14 and r15 containing the fault address and error code, with the
756 * original values stashed away in the PACA
757 */
758 storage_fault_common:
759 std r14,_DAR(r1)
760 std r15,_DSISR(r1)
761 addi r3,r1,STACK_FRAME_OVERHEAD
762 mr r4,r14
763 mr r5,r15
764 ld r14,PACA_EXGEN+EX_R14(r13)
765 ld r15,PACA_EXGEN+EX_R15(r13)
766 bl .do_page_fault
767 cmpdi r3,0
768 bne- 1f
769 b .ret_from_except_lite
770 1: bl .save_nvgprs
771 mr r5,r3
772 addi r3,r1,STACK_FRAME_OVERHEAD
773 ld r4,_DAR(r1)
774 bl .bad_page_fault
775 b .ret_from_except
776
777 /*
778 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
779 * continues here.
780 */
781 alignment_more:
782 std r14,_DAR(r1)
783 std r15,_DSISR(r1)
784 addi r3,r1,STACK_FRAME_OVERHEAD
785 ld r14,PACA_EXGEN+EX_R14(r13)
786 ld r15,PACA_EXGEN+EX_R15(r13)
787 bl .save_nvgprs
788 INTS_RESTORE_HARD
789 bl .alignment_exception
790 b .ret_from_except
791
792 /*
793 * We branch here from entry_64.S for the last stage of the exception
794 * return code path. MSR:EE is expected to be off at that point
795 */
796 _GLOBAL(exception_return_book3e)
797 b 1f
798
799 /* This is the return from load_up_fpu fast path which could do with
800 * less GPR restores in fact, but for now we have a single return path
801 */
802 .globl fast_exception_return
803 fast_exception_return:
804 wrteei 0
805 1: mr r0,r13
806 ld r10,_MSR(r1)
807 REST_4GPRS(2, r1)
808 andi. r6,r10,MSR_PR
809 REST_2GPRS(6, r1)
810 beq 1f
811 ACCOUNT_CPU_USER_EXIT(r10, r11)
812 ld r0,GPR13(r1)
813
814 1: stdcx. r0,0,r1 /* to clear the reservation */
815
816 ld r8,_CCR(r1)
817 ld r9,_LINK(r1)
818 ld r10,_CTR(r1)
819 ld r11,_XER(r1)
820 mtcr r8
821 mtlr r9
822 mtctr r10
823 mtxer r11
824 REST_2GPRS(8, r1)
825 ld r10,GPR10(r1)
826 ld r11,GPR11(r1)
827 ld r12,GPR12(r1)
828 mtspr SPRN_SPRG_GEN_SCRATCH,r0
829
830 std r10,PACA_EXGEN+EX_R10(r13);
831 std r11,PACA_EXGEN+EX_R11(r13);
832 ld r10,_NIP(r1)
833 ld r11,_MSR(r1)
834 ld r0,GPR0(r1)
835 ld r1,GPR1(r1)
836 mtspr SPRN_SRR0,r10
837 mtspr SPRN_SRR1,r11
838 ld r10,PACA_EXGEN+EX_R10(r13)
839 ld r11,PACA_EXGEN+EX_R11(r13)
840 mfspr r13,SPRN_SPRG_GEN_SCRATCH
841 rfi
842
843 /*
844 * Trampolines used when spotting a bad kernel stack pointer in
845 * the exception entry code.
846 *
847 * TODO: move some bits like SRR0 read to trampoline, pass PACA
848 * index around, etc... to handle crit & mcheck
849 */
850 BAD_STACK_TRAMPOLINE(0x000)
851 BAD_STACK_TRAMPOLINE(0x100)
852 BAD_STACK_TRAMPOLINE(0x200)
853 BAD_STACK_TRAMPOLINE(0x220)
854 BAD_STACK_TRAMPOLINE(0x260)
855 BAD_STACK_TRAMPOLINE(0x280)
856 BAD_STACK_TRAMPOLINE(0x2a0)
857 BAD_STACK_TRAMPOLINE(0x2c0)
858 BAD_STACK_TRAMPOLINE(0x2e0)
859 BAD_STACK_TRAMPOLINE(0x300)
860 BAD_STACK_TRAMPOLINE(0x310)
861 BAD_STACK_TRAMPOLINE(0x320)
862 BAD_STACK_TRAMPOLINE(0x400)
863 BAD_STACK_TRAMPOLINE(0x500)
864 BAD_STACK_TRAMPOLINE(0x600)
865 BAD_STACK_TRAMPOLINE(0x700)
866 BAD_STACK_TRAMPOLINE(0x800)
867 BAD_STACK_TRAMPOLINE(0x900)
868 BAD_STACK_TRAMPOLINE(0x980)
869 BAD_STACK_TRAMPOLINE(0x9f0)
870 BAD_STACK_TRAMPOLINE(0xa00)
871 BAD_STACK_TRAMPOLINE(0xb00)
872 BAD_STACK_TRAMPOLINE(0xc00)
873 BAD_STACK_TRAMPOLINE(0xd00)
874 BAD_STACK_TRAMPOLINE(0xd08)
875 BAD_STACK_TRAMPOLINE(0xe00)
876 BAD_STACK_TRAMPOLINE(0xf00)
877 BAD_STACK_TRAMPOLINE(0xf20)
878
879 .globl bad_stack_book3e
880 bad_stack_book3e:
881 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
882 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
883 ld r1,PACAEMERGSP(r13)
884 subi r1,r1,64+INT_FRAME_SIZE
885 std r10,_NIP(r1)
886 std r11,_MSR(r1)
887 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
888 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
889 std r10,GPR1(r1)
890 std r11,_CCR(r1)
891 mfspr r10,SPRN_DEAR
892 mfspr r11,SPRN_ESR
893 std r10,_DAR(r1)
894 std r11,_DSISR(r1)
895 std r0,GPR0(r1); /* save r0 in stackframe */ \
896 std r2,GPR2(r1); /* save r2 in stackframe */ \
897 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
898 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
899 std r9,GPR9(r1); /* save r9 in stackframe */ \
900 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
901 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
902 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
903 std r3,GPR10(r1); /* save r10 to stackframe */ \
904 std r4,GPR11(r1); /* save r11 to stackframe */ \
905 std r12,GPR12(r1); /* save r12 in stackframe */ \
906 std r5,GPR13(r1); /* save it to stackframe */ \
907 mflr r10
908 mfctr r11
909 mfxer r12
910 std r10,_LINK(r1)
911 std r11,_CTR(r1)
912 std r12,_XER(r1)
913 SAVE_10GPRS(14,r1)
914 SAVE_8GPRS(24,r1)
915 lhz r12,PACA_TRAP_SAVE(r13)
916 std r12,_TRAP(r1)
917 addi r11,r1,INT_FRAME_SIZE
918 std r11,0(r1)
919 li r12,0
920 std r12,0(r11)
921 ld r2,PACATOC(r13)
922 1: addi r3,r1,STACK_FRAME_OVERHEAD
923 bl .kernel_bad_stack
924 b 1b
925
926 /*
927 * Setup the initial TLB for a core. This current implementation
928 * assume that whatever we are running off will not conflict with
929 * the new mapping at PAGE_OFFSET.
930 */
931 _GLOBAL(initial_tlb_book3e)
932
933 /* Look for the first TLB with IPROT set */
934 mfspr r4,SPRN_TLB0CFG
935 andi. r3,r4,TLBnCFG_IPROT
936 lis r3,MAS0_TLBSEL(0)@h
937 bne found_iprot
938
939 mfspr r4,SPRN_TLB1CFG
940 andi. r3,r4,TLBnCFG_IPROT
941 lis r3,MAS0_TLBSEL(1)@h
942 bne found_iprot
943
944 mfspr r4,SPRN_TLB2CFG
945 andi. r3,r4,TLBnCFG_IPROT
946 lis r3,MAS0_TLBSEL(2)@h
947 bne found_iprot
948
949 lis r3,MAS0_TLBSEL(3)@h
950 mfspr r4,SPRN_TLB3CFG
951 /* fall through */
952
953 found_iprot:
954 andi. r5,r4,TLBnCFG_HES
955 bne have_hes
956
957 mflr r8 /* save LR */
958 /* 1. Find the index of the entry we're executing in
959 *
960 * r3 = MAS0_TLBSEL (for the iprot array)
961 * r4 = SPRN_TLBnCFG
962 */
963 bl invstr /* Find our address */
964 invstr: mflr r6 /* Make it accessible */
965 mfmsr r7
966 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
967 mfspr r7,SPRN_PID
968 slwi r7,r7,16
969 or r7,r7,r5
970 mtspr SPRN_MAS6,r7
971 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
972
973 mfspr r3,SPRN_MAS0
974 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
975
976 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
977 oris r7,r7,MAS1_IPROT@h
978 mtspr SPRN_MAS1,r7
979 tlbwe
980
981 /* 2. Invalidate all entries except the entry we're executing in
982 *
983 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
984 * r4 = SPRN_TLBnCFG
985 * r5 = ESEL of entry we are running in
986 */
987 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
988 li r6,0 /* Set Entry counter to 0 */
989 1: mr r7,r3 /* Set MAS0(TLBSEL) */
990 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
991 mtspr SPRN_MAS0,r7
992 tlbre
993 mfspr r7,SPRN_MAS1
994 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
995 cmpw r5,r6
996 beq skpinv /* Dont update the current execution TLB */
997 mtspr SPRN_MAS1,r7
998 tlbwe
999 isync
1000 skpinv: addi r6,r6,1 /* Increment */
1001 cmpw r6,r4 /* Are we done? */
1002 bne 1b /* If not, repeat */
1003
1004 /* Invalidate all TLBs */
1005 PPC_TLBILX_ALL(0,R0)
1006 sync
1007 isync
1008
1009 /* 3. Setup a temp mapping and jump to it
1010 *
1011 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1012 * r5 = ESEL of entry we are running in
1013 */
1014 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
1015 addi r7,r7,0x1
1016 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
1017 mtspr SPRN_MAS0,r4
1018 tlbre
1019
1020 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
1021 mtspr SPRN_MAS0,r4
1022
1023 mfspr r7,SPRN_MAS1
1024 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
1025 mtspr SPRN_MAS1,r6
1026
1027 tlbwe
1028
1029 mfmsr r6
1030 xori r6,r6,MSR_IS
1031 mtspr SPRN_SRR1,r6
1032 bl 1f /* Find our address */
1033 1: mflr r6
1034 addi r6,r6,(2f - 1b)
1035 mtspr SPRN_SRR0,r6
1036 rfi
1037 2:
1038
1039 /* 4. Clear out PIDs & Search info
1040 *
1041 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1042 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1043 * r5 = MAS3
1044 */
1045 li r6,0
1046 mtspr SPRN_MAS6,r6
1047 mtspr SPRN_PID,r6
1048
1049 /* 5. Invalidate mapping we started in
1050 *
1051 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1052 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1053 * r5 = MAS3
1054 */
1055 mtspr SPRN_MAS0,r3
1056 tlbre
1057 mfspr r6,SPRN_MAS1
1058 rlwinm r6,r6,0,2,0 /* clear IPROT */
1059 mtspr SPRN_MAS1,r6
1060 tlbwe
1061
1062 /* Invalidate TLB1 */
1063 PPC_TLBILX_ALL(0,R0)
1064 sync
1065 isync
1066
1067 /* The mapping only needs to be cache-coherent on SMP */
1068 #ifdef CONFIG_SMP
1069 #define M_IF_SMP MAS2_M
1070 #else
1071 #define M_IF_SMP 0
1072 #endif
1073
1074 /* 6. Setup KERNELBASE mapping in TLB[0]
1075 *
1076 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1077 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1078 * r5 = MAS3
1079 */
1080 rlwinm r3,r3,0,16,3 /* clear ESEL */
1081 mtspr SPRN_MAS0,r3
1082 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1083 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1084 mtspr SPRN_MAS1,r6
1085
1086 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
1087 mtspr SPRN_MAS2,r6
1088
1089 rlwinm r5,r5,0,0,25
1090 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1091 mtspr SPRN_MAS3,r5
1092 li r5,-1
1093 rlwinm r5,r5,0,0,25
1094
1095 tlbwe
1096
1097 /* 7. Jump to KERNELBASE mapping
1098 *
1099 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1100 */
1101 /* Now we branch the new virtual address mapped by this entry */
1102 LOAD_REG_IMMEDIATE(r6,2f)
1103 lis r7,MSR_KERNEL@h
1104 ori r7,r7,MSR_KERNEL@l
1105 mtspr SPRN_SRR0,r6
1106 mtspr SPRN_SRR1,r7
1107 rfi /* start execution out of TLB1[0] entry */
1108 2:
1109
1110 /* 8. Clear out the temp mapping
1111 *
1112 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1113 */
1114 mtspr SPRN_MAS0,r4
1115 tlbre
1116 mfspr r5,SPRN_MAS1
1117 rlwinm r5,r5,0,2,0 /* clear IPROT */
1118 mtspr SPRN_MAS1,r5
1119 tlbwe
1120
1121 /* Invalidate TLB1 */
1122 PPC_TLBILX_ALL(0,R0)
1123 sync
1124 isync
1125
1126 /* We translate LR and return */
1127 tovirt(r8,r8)
1128 mtlr r8
1129 blr
1130
1131 have_hes:
1132 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1133 * kernel linear mapping. We also set MAS8 once for all here though
1134 * that will have to be made dependent on whether we are running under
1135 * a hypervisor I suppose.
1136 */
1137
1138 /* BEWARE, MAGIC
1139 * This code is called as an ordinary function on the boot CPU. But to
1140 * avoid duplication, this code is also used in SCOM bringup of
1141 * secondary CPUs. We read the code between the initial_tlb_code_start
1142 * and initial_tlb_code_end labels one instruction at a time and RAM it
1143 * into the new core via SCOM. That doesn't process branches, so there
1144 * must be none between those two labels. It also means if this code
1145 * ever takes any parameters, the SCOM code must also be updated to
1146 * provide them.
1147 */
1148 .globl a2_tlbinit_code_start
1149 a2_tlbinit_code_start:
1150
1151 ori r11,r3,MAS0_WQ_ALLWAYS
1152 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1153 mtspr SPRN_MAS0,r11
1154 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1155 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1156 mtspr SPRN_MAS1,r3
1157 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1158 mtspr SPRN_MAS2,r3
1159 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1160 mtspr SPRN_MAS7_MAS3,r3
1161 li r3,0
1162 mtspr SPRN_MAS8,r3
1163
1164 /* Write the TLB entry */
1165 tlbwe
1166
1167 .globl a2_tlbinit_after_linear_map
1168 a2_tlbinit_after_linear_map:
1169
1170 /* Now we branch the new virtual address mapped by this entry */
1171 LOAD_REG_IMMEDIATE(r3,1f)
1172 mtctr r3
1173 bctr
1174
1175 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1176 * else (including IPROTed things left by firmware)
1177 * r4 = TLBnCFG
1178 * r3 = current address (more or less)
1179 */
1180
1181 li r5,0
1182 mtspr SPRN_MAS6,r5
1183 tlbsx 0,r3
1184
1185 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1186 rlwinm r10,r4,8,0xff
1187 addi r10,r10,-1 /* Get inner loop mask */
1188
1189 li r3,1
1190
1191 mfspr r5,SPRN_MAS1
1192 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1193
1194 mfspr r6,SPRN_MAS2
1195 rldicr r6,r6,0,51 /* Extract EPN */
1196
1197 mfspr r7,SPRN_MAS0
1198 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1199
1200 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1201
1202 2: add r4,r3,r8
1203 and r4,r4,r10
1204
1205 rlwimi r7,r4,16,MAS0_ESEL_MASK
1206
1207 mtspr SPRN_MAS0,r7
1208 mtspr SPRN_MAS1,r5
1209 mtspr SPRN_MAS2,r6
1210 tlbwe
1211
1212 addi r3,r3,1
1213 and. r4,r3,r10
1214
1215 bne 3f
1216 addis r6,r6,(1<<30)@h
1217 3:
1218 cmpw r3,r9
1219 blt 2b
1220
1221 .globl a2_tlbinit_after_iprot_flush
1222 a2_tlbinit_after_iprot_flush:
1223
1224 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1225 /* Now establish early debug mappings if applicable */
1226 /* Restore the MAS0 we used for linear mapping load */
1227 mtspr SPRN_MAS0,r11
1228
1229 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1230 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1231 mtspr SPRN_MAS1,r3
1232 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1233 mtspr SPRN_MAS2,r3
1234 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1235 mtspr SPRN_MAS7_MAS3,r3
1236 /* re-use the MAS8 value from the linear mapping */
1237 tlbwe
1238 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1239
1240 PPC_TLBILX(0,0,R0)
1241 sync
1242 isync
1243
1244 .globl a2_tlbinit_code_end
1245 a2_tlbinit_code_end:
1246
1247 /* We translate LR and return */
1248 mflr r3
1249 tovirt(r3,r3)
1250 mtlr r3
1251 blr
1252
1253 /*
1254 * Main entry (boot CPU, thread 0)
1255 *
1256 * We enter here from head_64.S, possibly after the prom_init trampoline
1257 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1258 * mode. Anything else is as it was left by the bootloader
1259 *
1260 * Initial requirements of this port:
1261 *
1262 * - Kernel loaded at 0 physical
1263 * - A good lump of memory mapped 0:0 by UTLB entry 0
1264 * - MSR:IS & MSR:DS set to 0
1265 *
1266 * Note that some of the above requirements will be relaxed in the future
1267 * as the kernel becomes smarter at dealing with different initial conditions
1268 * but for now you have to be careful
1269 */
1270 _GLOBAL(start_initialization_book3e)
1271 mflr r28
1272
1273 /* First, we need to setup some initial TLBs to map the kernel
1274 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1275 * and always use AS 0, so we just set it up to match our link
1276 * address and never use 0 based addresses.
1277 */
1278 bl .initial_tlb_book3e
1279
1280 /* Init global core bits */
1281 bl .init_core_book3e
1282
1283 /* Init per-thread bits */
1284 bl .init_thread_book3e
1285
1286 /* Return to common init code */
1287 tovirt(r28,r28)
1288 mtlr r28
1289 blr
1290
1291
1292 /*
1293 * Secondary core/processor entry
1294 *
1295 * This is entered for thread 0 of a secondary core, all other threads
1296 * are expected to be stopped. It's similar to start_initialization_book3e
1297 * except that it's generally entered from the holding loop in head_64.S
1298 * after CPUs have been gathered by Open Firmware.
1299 *
1300 * We assume we are in 32 bits mode running with whatever TLB entry was
1301 * set for us by the firmware or POR engine.
1302 */
1303 _GLOBAL(book3e_secondary_core_init_tlb_set)
1304 li r4,1
1305 b .generic_secondary_smp_init
1306
1307 _GLOBAL(book3e_secondary_core_init)
1308 mflr r28
1309
1310 /* Do we need to setup initial TLB entry ? */
1311 cmplwi r4,0
1312 bne 2f
1313
1314 /* Setup TLB for this core */
1315 bl .initial_tlb_book3e
1316
1317 /* We can return from the above running at a different
1318 * address, so recalculate r2 (TOC)
1319 */
1320 bl .relative_toc
1321
1322 /* Init global core bits */
1323 2: bl .init_core_book3e
1324
1325 /* Init per-thread bits */
1326 3: bl .init_thread_book3e
1327
1328 /* Return to common init code at proper virtual address.
1329 *
1330 * Due to various previous assumptions, we know we entered this
1331 * function at either the final PAGE_OFFSET mapping or using a
1332 * 1:1 mapping at 0, so we don't bother doing a complicated check
1333 * here, we just ensure the return address has the right top bits.
1334 *
1335 * Note that if we ever want to be smarter about where we can be
1336 * started from, we have to be careful that by the time we reach
1337 * the code below we may already be running at a different location
1338 * than the one we were called from since initial_tlb_book3e can
1339 * have moved us already.
1340 */
1341 cmpdi cr0,r28,0
1342 blt 1f
1343 lis r3,PAGE_OFFSET@highest
1344 sldi r3,r3,32
1345 or r28,r28,r3
1346 1: mtlr r28
1347 blr
1348
1349 _GLOBAL(book3e_secondary_thread_init)
1350 mflr r28
1351 b 3b
1352
1353 _STATIC(init_core_book3e)
1354 /* Establish the interrupt vector base */
1355 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1356 mtspr SPRN_IVPR,r3
1357 sync
1358 blr
1359
1360 _STATIC(init_thread_book3e)
1361 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1362 mtspr SPRN_EPCR,r3
1363
1364 /* Make sure interrupts are off */
1365 wrteei 0
1366
1367 /* disable all timers and clear out status */
1368 li r3,0
1369 mtspr SPRN_TCR,r3
1370 mfspr r3,SPRN_TSR
1371 mtspr SPRN_TSR,r3
1372
1373 blr
1374
1375 _GLOBAL(__setup_base_ivors)
1376 SET_IVOR(0, 0x020) /* Critical Input */
1377 SET_IVOR(1, 0x000) /* Machine Check */
1378 SET_IVOR(2, 0x060) /* Data Storage */
1379 SET_IVOR(3, 0x080) /* Instruction Storage */
1380 SET_IVOR(4, 0x0a0) /* External Input */
1381 SET_IVOR(5, 0x0c0) /* Alignment */
1382 SET_IVOR(6, 0x0e0) /* Program */
1383 SET_IVOR(7, 0x100) /* FP Unavailable */
1384 SET_IVOR(8, 0x120) /* System Call */
1385 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1386 SET_IVOR(10, 0x160) /* Decrementer */
1387 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1388 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1389 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1390 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1391 SET_IVOR(15, 0x040) /* Debug */
1392
1393 sync
1394
1395 blr
1396
1397 _GLOBAL(setup_altivec_ivors)
1398 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1399 SET_IVOR(33, 0x220) /* AltiVec Assist */
1400 blr
1401
1402 _GLOBAL(setup_perfmon_ivor)
1403 SET_IVOR(35, 0x260) /* Performance Monitor */
1404 blr
1405
1406 _GLOBAL(setup_doorbell_ivors)
1407 SET_IVOR(36, 0x280) /* Processor Doorbell */
1408 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1409 blr
1410
1411 _GLOBAL(setup_ehv_ivors)
1412 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1413 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1414 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1415 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1416 blr
Linux kernel - Deliverables
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