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powerpc/mm: Used free register to save a few cycles in SW TLB miss handling
[deliverable/linux.git] / arch / powerpc / kernel / head_32.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/mmu.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/ptrace.h>
34 #include <asm/bug.h>
35
36 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
39 li RA,0; \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 beq 1f; \
47 lwz RA,(n*16)+8(reg); \
48 lwz RB,(n*16)+12(reg); \
49 mtspr SPRN_DBAT##n##U,RA; \
50 mtspr SPRN_DBAT##n##L,RB; \
51 1:
52
53 .section .text.head, "ax"
54 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
55 .stabs "head_32.S",N_SO,0,0,0f
56 0:
57 _ENTRY(_stext);
58
59 /*
60 * _start is defined this way because the XCOFF loader in the OpenFirmware
61 * on the powermac expects the entry point to be a procedure descriptor.
62 */
63 _ENTRY(_start);
64 /*
65 * These are here for legacy reasons, the kernel used to
66 * need to look like a coff function entry for the pmac
67 * but we're always started by some kind of bootloader now.
68 * -- Cort
69 */
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
72 nop
73
74 /* PMAC
75 * Enter here with the kernel text, data and bss loaded starting at
76 * 0, running with virtual == physical mapping.
77 * r5 points to the prom entry point (the client interface handler
78 * address). Address translation is turned on, with the prom
79 * managing the hash table. Interrupts are disabled. The stack
80 * pointer (r1) points to just below the end of the half-meg region
81 * from 0x380000 - 0x400000, which is mapped in already.
82 *
83 * If we are booted from MacOS via BootX, we enter with the kernel
84 * image loaded somewhere, and the following values in registers:
85 * r3: 'BooX' (0x426f6f58)
86 * r4: virtual address of boot_infos_t
87 * r5: 0
88 *
89 * PREP
90 * This is jumped to on prep systems right after the kernel is relocated
91 * to its proper place in memory by the boot loader. The expected layout
92 * of the regs is:
93 * r3: ptr to residual data
94 * r4: initrd_start or if no initrd then 0
95 * r5: initrd_end - unused if r4 is 0
96 * r6: Start of command line string
97 * r7: End of command line string
98 *
99 * This just gets a minimal mmu environment setup so we can call
100 * start_here() to do the real work.
101 * -- Cort
102 */
103
104 .globl __start
105 __start:
106 /*
107 * We have to do any OF calls before we map ourselves to KERNELBASE,
108 * because OF may have I/O devices mapped into that area
109 * (particularly on CHRP).
110 */
111 cmpwi 0,r5,0
112 beq 1f
113
114 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
115 /* find out where we are now */
116 bcl 20,31,$+4
117 0: mflr r8 /* r8 = runtime addr here */
118 addis r8,r8,(_stext - 0b)@ha
119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
120 bl prom_init
121 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
122
123 /* We never return. We also hit that trap if trying to boot
124 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
125 trap
126
127 /*
128 * Check for BootX signature when supporting PowerMac and branch to
129 * appropriate trampoline if it's present
130 */
131 #ifdef CONFIG_PPC_PMAC
132 1: lis r31,0x426f
133 ori r31,r31,0x6f58
134 cmpw 0,r3,r31
135 bne 1f
136 bl bootx_init
137 trap
138 #endif /* CONFIG_PPC_PMAC */
139
140 1: mr r31,r3 /* save parameters */
141 mr r30,r4
142 li r24,0 /* cpu # */
143
144 /*
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
147 * -- Cort <cort@fsmlabs.com>
148 */
149 bl early_init
150
151 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
152 * the physical address we are running at, returned by early_init()
153 */
154 bl mmu_off
155 __after_mmu_off:
156 bl clear_bats
157 bl flush_tlbs
158
159 bl initial_bats
160 #if defined(CONFIG_BOOTX_TEXT)
161 bl setup_disp_bat
162 #endif
163 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
164 bl setup_cpm_bat
165 #endif
166
167 /*
168 * Call setup_cpu for CPU 0 and initialize 6xx Idle
169 */
170 bl reloc_offset
171 li r24,0 /* cpu# */
172 bl call_setup_cpu /* Call setup_cpu for this CPU */
173 #ifdef CONFIG_6xx
174 bl reloc_offset
175 bl init_idle_6xx
176 #endif /* CONFIG_6xx */
177
178
179 /*
180 * We need to run with _start at physical address 0.
181 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
182 * the exception vectors at 0 (and therefore this copy
183 * overwrites OF's exception vectors with our own).
184 * The MMU is off at this point.
185 */
186 bl reloc_offset
187 mr r26,r3
188 addis r4,r3,KERNELBASE@h /* current address of _start */
189 lis r5,PHYSICAL_START@h
190 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
191 bne relocate_kernel
192 /*
193 * we now have the 1st 16M of ram mapped with the bats.
194 * prep needs the mmu to be turned on here, but pmac already has it on.
195 * this shouldn't bother the pmac since it just gets turned on again
196 * as we jump to our code at KERNELBASE. -- Cort
197 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
198 * off, and in other cases, we now turn it off before changing BATs above.
199 */
200 turn_on_mmu:
201 mfmsr r0
202 ori r0,r0,MSR_DR|MSR_IR
203 mtspr SPRN_SRR1,r0
204 lis r0,start_here@h
205 ori r0,r0,start_here@l
206 mtspr SPRN_SRR0,r0
207 SYNC
208 RFI /* enables MMU */
209
210 /*
211 * We need __secondary_hold as a place to hold the other cpus on
212 * an SMP machine, even when we are running a UP kernel.
213 */
214 . = 0xc0 /* for prep bootloader */
215 li r3,1 /* MTX only has 1 cpu */
216 .globl __secondary_hold
217 __secondary_hold:
218 /* tell the master we're here */
219 stw r3,__secondary_hold_acknowledge@l(0)
220 #ifdef CONFIG_SMP
221 100: lwz r4,0(0)
222 /* wait until we're told to start */
223 cmpw 0,r4,r3
224 bne 100b
225 /* our cpu # was at addr 0 - go */
226 mr r24,r3 /* cpu # */
227 b __secondary_start
228 #else
229 b .
230 #endif /* CONFIG_SMP */
231
232 .globl __secondary_hold_spinloop
233 __secondary_hold_spinloop:
234 .long 0
235 .globl __secondary_hold_acknowledge
236 __secondary_hold_acknowledge:
237 .long -1
238
239 /*
240 * Exception entry code. This code runs with address translation
241 * turned off, i.e. using physical addresses.
242 * We assume sprg3 has the physical address of the current
243 * task's thread_struct.
244 */
245 #define EXCEPTION_PROLOG \
246 mtspr SPRN_SPRG0,r10; \
247 mtspr SPRN_SPRG1,r11; \
248 mfcr r10; \
249 EXCEPTION_PROLOG_1; \
250 EXCEPTION_PROLOG_2
251
252 #define EXCEPTION_PROLOG_1 \
253 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
254 andi. r11,r11,MSR_PR; \
255 tophys(r11,r1); /* use tophys(r1) if kernel */ \
256 beq 1f; \
257 mfspr r11,SPRN_SPRG3; \
258 lwz r11,THREAD_INFO-THREAD(r11); \
259 addi r11,r11,THREAD_SIZE; \
260 tophys(r11,r11); \
261 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
262
263
264 #define EXCEPTION_PROLOG_2 \
265 CLR_TOP32(r11); \
266 stw r10,_CCR(r11); /* save registers */ \
267 stw r12,GPR12(r11); \
268 stw r9,GPR9(r11); \
269 mfspr r10,SPRN_SPRG0; \
270 stw r10,GPR10(r11); \
271 mfspr r12,SPRN_SPRG1; \
272 stw r12,GPR11(r11); \
273 mflr r10; \
274 stw r10,_LINK(r11); \
275 mfspr r12,SPRN_SRR0; \
276 mfspr r9,SPRN_SRR1; \
277 stw r1,GPR1(r11); \
278 stw r1,0(r11); \
279 tovirt(r1,r11); /* set new kernel sp */ \
280 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
281 MTMSRD(r10); /* (except for mach check in rtas) */ \
282 stw r0,GPR0(r11); \
283 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
284 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
285 stw r10,8(r11); \
286 SAVE_4GPRS(3, r11); \
287 SAVE_2GPRS(7, r11)
288
289 /*
290 * Note: code which follows this uses cr0.eq (set if from kernel),
291 * r11, r12 (SRR0), and r9 (SRR1).
292 *
293 * Note2: once we have set r1 we are in a position to take exceptions
294 * again, and we could thus set MSR:RI at that point.
295 */
296
297 /*
298 * Exception vectors.
299 */
300 #define EXCEPTION(n, label, hdlr, xfer) \
301 . = n; \
302 label: \
303 EXCEPTION_PROLOG; \
304 addi r3,r1,STACK_FRAME_OVERHEAD; \
305 xfer(n, hdlr)
306
307 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
308 li r10,trap; \
309 stw r10,_TRAP(r11); \
310 li r10,MSR_KERNEL; \
311 copyee(r10, r9); \
312 bl tfer; \
313 i##n: \
314 .long hdlr; \
315 .long ret
316
317 #define COPY_EE(d, s) rlwimi d,s,0,16,16
318 #define NOCOPY(d, s)
319
320 #define EXC_XFER_STD(n, hdlr) \
321 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
322 ret_from_except_full)
323
324 #define EXC_XFER_LITE(n, hdlr) \
325 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
326 ret_from_except)
327
328 #define EXC_XFER_EE(n, hdlr) \
329 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
330 ret_from_except_full)
331
332 #define EXC_XFER_EE_LITE(n, hdlr) \
333 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
334 ret_from_except)
335
336 /* System reset */
337 /* core99 pmac starts the seconary here by changing the vector, and
338 putting it back to what it was (unknown_exception) when done. */
339 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
340
341 /* Machine check */
342 /*
343 * On CHRP, this is complicated by the fact that we could get a
344 * machine check inside RTAS, and we have no guarantee that certain
345 * critical registers will have the values we expect. The set of
346 * registers that might have bad values includes all the GPRs
347 * and all the BATs. We indicate that we are in RTAS by putting
348 * a non-zero value, the address of the exception frame to use,
349 * in SPRG2. The machine check handler checks SPRG2 and uses its
350 * value if it is non-zero. If we ever needed to free up SPRG2,
351 * we could use a field in the thread_info or thread_struct instead.
352 * (Other exception handlers assume that r1 is a valid kernel stack
353 * pointer when we take an exception from supervisor mode.)
354 * -- paulus.
355 */
356 . = 0x200
357 mtspr SPRN_SPRG0,r10
358 mtspr SPRN_SPRG1,r11
359 mfcr r10
360 #ifdef CONFIG_PPC_CHRP
361 mfspr r11,SPRN_SPRG2
362 cmpwi 0,r11,0
363 bne 7f
364 #endif /* CONFIG_PPC_CHRP */
365 EXCEPTION_PROLOG_1
366 7: EXCEPTION_PROLOG_2
367 addi r3,r1,STACK_FRAME_OVERHEAD
368 #ifdef CONFIG_PPC_CHRP
369 mfspr r4,SPRN_SPRG2
370 cmpwi cr1,r4,0
371 bne cr1,1f
372 #endif
373 EXC_XFER_STD(0x200, machine_check_exception)
374 #ifdef CONFIG_PPC_CHRP
375 1: b machine_check_in_rtas
376 #endif
377
378 /* Data access exception. */
379 . = 0x300
380 DataAccess:
381 EXCEPTION_PROLOG
382 mfspr r10,SPRN_DSISR
383 stw r10,_DSISR(r11)
384 andis. r0,r10,0xa470 /* weird error? */
385 bne 1f /* if not, try to put a PTE */
386 mfspr r4,SPRN_DAR /* into the hash table */
387 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
388 bl hash_page
389 1: lwz r5,_DSISR(r11) /* get DSISR value */
390 mfspr r4,SPRN_DAR
391 EXC_XFER_EE_LITE(0x300, handle_page_fault)
392
393
394 /* Instruction access exception. */
395 . = 0x400
396 InstructionAccess:
397 EXCEPTION_PROLOG
398 andis. r0,r9,0x4000 /* no pte found? */
399 beq 1f /* if so, try to put a PTE */
400 li r3,0 /* into the hash table */
401 mr r4,r12 /* SRR0 is fault address */
402 bl hash_page
403 1: mr r4,r12
404 mr r5,r9
405 EXC_XFER_EE_LITE(0x400, handle_page_fault)
406
407 /* External interrupt */
408 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
409
410 /* Alignment exception */
411 . = 0x600
412 Alignment:
413 EXCEPTION_PROLOG
414 mfspr r4,SPRN_DAR
415 stw r4,_DAR(r11)
416 mfspr r5,SPRN_DSISR
417 stw r5,_DSISR(r11)
418 addi r3,r1,STACK_FRAME_OVERHEAD
419 EXC_XFER_EE(0x600, alignment_exception)
420
421 /* Program check exception */
422 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
423
424 /* Floating-point unavailable */
425 . = 0x800
426 FPUnavailable:
427 BEGIN_FTR_SECTION
428 /*
429 * Certain Freescale cores don't have a FPU and treat fp instructions
430 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
431 */
432 b ProgramCheck
433 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
434 EXCEPTION_PROLOG
435 beq 1f
436 bl load_up_fpu /* if from user, just load it up */
437 b fast_exception_return
438 1: addi r3,r1,STACK_FRAME_OVERHEAD
439 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
440
441 /* Decrementer */
442 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
443
444 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
445 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
446
447 /* System call */
448 . = 0xc00
449 SystemCall:
450 EXCEPTION_PROLOG
451 EXC_XFER_EE_LITE(0xc00, DoSyscall)
452
453 /* Single step - not used on 601 */
454 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
455 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
456
457 /*
458 * The Altivec unavailable trap is at 0x0f20. Foo.
459 * We effectively remap it to 0x3000.
460 * We include an altivec unavailable exception vector even if
461 * not configured for Altivec, so that you can't panic a
462 * non-altivec kernel running on a machine with altivec just
463 * by executing an altivec instruction.
464 */
465 . = 0xf00
466 b PerformanceMonitor
467
468 . = 0xf20
469 b AltiVecUnavailable
470
471 /*
472 * Handle TLB miss for instruction on 603/603e.
473 * Note: we get an alternate set of r0 - r3 to use automatically.
474 */
475 . = 0x1000
476 InstructionTLBMiss:
477 /*
478 * r0: scratch
479 * r1: linux style pte ( later becomes ppc hardware pte )
480 * r2: ptr to linux-style pte
481 * r3: scratch
482 */
483 /* Get PTE (linux-style) and check access */
484 mfspr r3,SPRN_IMISS
485 lis r1,PAGE_OFFSET@h /* check if kernel address */
486 cmplw 0,r1,r3
487 mfspr r2,SPRN_SPRG3
488 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
489 lwz r2,PGDIR(r2)
490 bge- 112f
491 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
492 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
493 lis r2,swapper_pg_dir@ha /* if kernel address, use */
494 addi r2,r2,swapper_pg_dir@l /* kernel page table */
495 112: tophys(r2,r2)
496 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
497 lwz r2,0(r2) /* get pmd entry */
498 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
499 beq- InstructionAddressInvalid /* return if no mapping */
500 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
501 lwz r0,0(r2) /* get linux-style pte */
502 andc. r1,r1,r0 /* check access & ~permission */
503 bne- InstructionAddressInvalid /* return if access not permitted */
504 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
505 /*
506 * NOTE! We are assuming this is not an SMP system, otherwise
507 * we would need to update the pte atomically with lwarx/stwcx.
508 */
509 stw r0,0(r2) /* update PTE (accessed bit) */
510 /* Convert linux-style PTE to low word of PPC-style PTE */
511 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
512 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
513 and r1,r1,r2 /* writable if _RW and _DIRTY */
514 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
515 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
516 ori r1,r1,0xe04 /* clear out reserved bits */
517 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
518 BEGIN_FTR_SECTION
519 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
520 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
521 mtspr SPRN_RPA,r1
522 tlbli r3
523 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
524 mtcrf 0x80,r3
525 rfi
526 InstructionAddressInvalid:
527 mfspr r3,SPRN_SRR1
528 rlwinm r1,r3,9,6,6 /* Get load/store bit */
529
530 addis r1,r1,0x2000
531 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
532 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
533 or r2,r2,r1
534 mtspr SPRN_SRR1,r2
535 mfspr r1,SPRN_IMISS /* Get failing address */
536 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
537 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
538 xor r1,r1,r2
539 mtspr SPRN_DAR,r1 /* Set fault address */
540 mfmsr r0 /* Restore "normal" registers */
541 xoris r0,r0,MSR_TGPR>>16
542 mtcrf 0x80,r3 /* Restore CR0 */
543 mtmsr r0
544 b InstructionAccess
545
546 /*
547 * Handle TLB miss for DATA Load operation on 603/603e
548 */
549 . = 0x1100
550 DataLoadTLBMiss:
551 /*
552 * r0: scratch
553 * r1: linux style pte ( later becomes ppc hardware pte )
554 * r2: ptr to linux-style pte
555 * r3: scratch
556 */
557 /* Get PTE (linux-style) and check access */
558 mfspr r3,SPRN_DMISS
559 lis r1,PAGE_OFFSET@h /* check if kernel address */
560 cmplw 0,r1,r3
561 mfspr r2,SPRN_SPRG3
562 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
563 lwz r2,PGDIR(r2)
564 bge- 112f
565 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
566 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
567 lis r2,swapper_pg_dir@ha /* if kernel address, use */
568 addi r2,r2,swapper_pg_dir@l /* kernel page table */
569 112: tophys(r2,r2)
570 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
571 lwz r2,0(r2) /* get pmd entry */
572 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
573 beq- DataAddressInvalid /* return if no mapping */
574 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
575 lwz r0,0(r2) /* get linux-style pte */
576 andc. r1,r1,r0 /* check access & ~permission */
577 bne- DataAddressInvalid /* return if access not permitted */
578 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
579 /*
580 * NOTE! We are assuming this is not an SMP system, otherwise
581 * we would need to update the pte atomically with lwarx/stwcx.
582 */
583 stw r0,0(r2) /* update PTE (accessed bit) */
584 /* Convert linux-style PTE to low word of PPC-style PTE */
585 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
586 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
587 and r1,r1,r2 /* writable if _RW and _DIRTY */
588 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
589 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
590 ori r1,r1,0xe04 /* clear out reserved bits */
591 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
592 BEGIN_FTR_SECTION
593 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
594 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
595 mtspr SPRN_RPA,r1
596 tlbld r3
597 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
598 mtcrf 0x80,r3
599 rfi
600 DataAddressInvalid:
601 mfspr r3,SPRN_SRR1
602 rlwinm r1,r3,9,6,6 /* Get load/store bit */
603 addis r1,r1,0x2000
604 mtspr SPRN_DSISR,r1
605 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
606 mtspr SPRN_SRR1,r2
607 mfspr r1,SPRN_DMISS /* Get failing address */
608 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
609 beq 20f /* Jump if big endian */
610 xori r1,r1,3
611 20: mtspr SPRN_DAR,r1 /* Set fault address */
612 mfmsr r0 /* Restore "normal" registers */
613 xoris r0,r0,MSR_TGPR>>16
614 mtcrf 0x80,r3 /* Restore CR0 */
615 mtmsr r0
616 b DataAccess
617
618 /*
619 * Handle TLB miss for DATA Store on 603/603e
620 */
621 . = 0x1200
622 DataStoreTLBMiss:
623 /*
624 * r0: scratch
625 * r1: linux style pte ( later becomes ppc hardware pte )
626 * r2: ptr to linux-style pte
627 * r3: scratch
628 */
629 /* Get PTE (linux-style) and check access */
630 mfspr r3,SPRN_DMISS
631 lis r1,PAGE_OFFSET@h /* check if kernel address */
632 cmplw 0,r1,r3
633 mfspr r2,SPRN_SPRG3
634 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
635 lwz r2,PGDIR(r2)
636 bge- 112f
637 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
638 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
639 lis r2,swapper_pg_dir@ha /* if kernel address, use */
640 addi r2,r2,swapper_pg_dir@l /* kernel page table */
641 112: tophys(r2,r2)
642 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
643 lwz r2,0(r2) /* get pmd entry */
644 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
645 beq- DataAddressInvalid /* return if no mapping */
646 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
647 lwz r0,0(r2) /* get linux-style pte */
648 andc. r1,r1,r0 /* check access & ~permission */
649 bne- DataAddressInvalid /* return if access not permitted */
650 ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
651 /*
652 * NOTE! We are assuming this is not an SMP system, otherwise
653 * we would need to update the pte atomically with lwarx/stwcx.
654 */
655 stw r0,0(r2) /* update PTE (accessed/dirty bits) */
656 /* Convert linux-style PTE to low word of PPC-style PTE */
657 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
658 li r1,0xe05 /* clear out reserved bits & PP lsb */
659 andc r1,r0,r1 /* PP = user? 2: 0 */
660 BEGIN_FTR_SECTION
661 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
662 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
663 mtspr SPRN_RPA,r1
664 tlbld r3
665 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
666 mtcrf 0x80,r3
667 rfi
668
669 #ifndef CONFIG_ALTIVEC
670 #define altivec_assist_exception unknown_exception
671 #endif
672
673 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
674 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
675 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
677 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
678 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
687 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
690 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
691 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
692 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
693 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
694 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
695 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
698 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
699 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
700 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
701 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
702
703 .globl mol_trampoline
704 .set mol_trampoline, i0x2f00
705
706 . = 0x3000
707
708 AltiVecUnavailable:
709 EXCEPTION_PROLOG
710 #ifdef CONFIG_ALTIVEC
711 bne load_up_altivec /* if from user, just load it up */
712 #endif /* CONFIG_ALTIVEC */
713 addi r3,r1,STACK_FRAME_OVERHEAD
714 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
715
716 PerformanceMonitor:
717 EXCEPTION_PROLOG
718 addi r3,r1,STACK_FRAME_OVERHEAD
719 EXC_XFER_STD(0xf00, performance_monitor_exception)
720
721 #ifdef CONFIG_ALTIVEC
722 /* Note that the AltiVec support is closely modeled after the FP
723 * support. Changes to one are likely to be applicable to the
724 * other! */
725 load_up_altivec:
726 /*
727 * Disable AltiVec for the task which had AltiVec previously,
728 * and save its AltiVec registers in its thread_struct.
729 * Enables AltiVec for use in the kernel on return.
730 * On SMP we know the AltiVec units are free, since we give it up every
731 * switch. -- Kumar
732 */
733 mfmsr r5
734 oris r5,r5,MSR_VEC@h
735 MTMSRD(r5) /* enable use of AltiVec now */
736 isync
737 /*
738 * For SMP, we don't do lazy AltiVec switching because it just gets too
739 * horrendously complex, especially when a task switches from one CPU
740 * to another. Instead we call giveup_altivec in switch_to.
741 */
742 #ifndef CONFIG_SMP
743 tophys(r6,0)
744 addis r3,r6,last_task_used_altivec@ha
745 lwz r4,last_task_used_altivec@l(r3)
746 cmpwi 0,r4,0
747 beq 1f
748 add r4,r4,r6
749 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
750 SAVE_32VRS(0,r10,r4)
751 mfvscr vr0
752 li r10,THREAD_VSCR
753 stvx vr0,r10,r4
754 lwz r5,PT_REGS(r4)
755 add r5,r5,r6
756 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
757 lis r10,MSR_VEC@h
758 andc r4,r4,r10 /* disable altivec for previous task */
759 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
760 1:
761 #endif /* CONFIG_SMP */
762 /* enable use of AltiVec after return */
763 oris r9,r9,MSR_VEC@h
764 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
765 li r4,1
766 li r10,THREAD_VSCR
767 stw r4,THREAD_USED_VR(r5)
768 lvx vr0,r10,r5
769 mtvscr vr0
770 REST_32VRS(0,r10,r5)
771 #ifndef CONFIG_SMP
772 subi r4,r5,THREAD
773 sub r4,r4,r6
774 stw r4,last_task_used_altivec@l(r3)
775 #endif /* CONFIG_SMP */
776 /* restore registers and return */
777 /* we haven't used ctr or xer or lr */
778 b fast_exception_return
779
780 /*
781 * giveup_altivec(tsk)
782 * Disable AltiVec for the task given as the argument,
783 * and save the AltiVec registers in its thread_struct.
784 * Enables AltiVec for use in the kernel on return.
785 */
786
787 .globl giveup_altivec
788 giveup_altivec:
789 mfmsr r5
790 oris r5,r5,MSR_VEC@h
791 SYNC
792 MTMSRD(r5) /* enable use of AltiVec now */
793 isync
794 cmpwi 0,r3,0
795 beqlr- /* if no previous owner, done */
796 addi r3,r3,THREAD /* want THREAD of task */
797 lwz r5,PT_REGS(r3)
798 cmpwi 0,r5,0
799 SAVE_32VRS(0, r4, r3)
800 mfvscr vr0
801 li r4,THREAD_VSCR
802 stvx vr0,r4,r3
803 beq 1f
804 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
805 lis r3,MSR_VEC@h
806 andc r4,r4,r3 /* disable AltiVec for previous task */
807 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
808 1:
809 #ifndef CONFIG_SMP
810 li r5,0
811 lis r4,last_task_used_altivec@ha
812 stw r5,last_task_used_altivec@l(r4)
813 #endif /* CONFIG_SMP */
814 blr
815 #endif /* CONFIG_ALTIVEC */
816
817 /*
818 * This code is jumped to from the startup code to copy
819 * the kernel image to physical address PHYSICAL_START.
820 */
821 relocate_kernel:
822 addis r9,r26,klimit@ha /* fetch klimit */
823 lwz r25,klimit@l(r9)
824 addis r25,r25,-KERNELBASE@h
825 lis r3,PHYSICAL_START@h /* Destination base address */
826 li r6,0 /* Destination offset */
827 li r5,0x4000 /* # bytes of memory to copy */
828 bl copy_and_flush /* copy the first 0x4000 bytes */
829 addi r0,r3,4f@l /* jump to the address of 4f */
830 mtctr r0 /* in copy and do the rest. */
831 bctr /* jump to the copy */
832 4: mr r5,r25
833 bl copy_and_flush /* copy the rest */
834 b turn_on_mmu
835
836 /*
837 * Copy routine used to copy the kernel to start at physical address 0
838 * and flush and invalidate the caches as needed.
839 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
840 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
841 */
842 _ENTRY(copy_and_flush)
843 addi r5,r5,-4
844 addi r6,r6,-4
845 4: li r0,L1_CACHE_BYTES/4
846 mtctr r0
847 3: addi r6,r6,4 /* copy a cache line */
848 lwzx r0,r6,r4
849 stwx r0,r6,r3
850 bdnz 3b
851 dcbst r6,r3 /* write it to memory */
852 sync
853 icbi r6,r3 /* flush the icache line */
854 cmplw 0,r6,r5
855 blt 4b
856 sync /* additional sync needed on g4 */
857 isync
858 addi r5,r5,4
859 addi r6,r6,4
860 blr
861
862 #ifdef CONFIG_SMP
863 #ifdef CONFIG_GEMINI
864 .globl __secondary_start_gemini
865 __secondary_start_gemini:
866 mfspr r4,SPRN_HID0
867 ori r4,r4,HID0_ICFI
868 li r3,0
869 ori r3,r3,HID0_ICE
870 andc r4,r4,r3
871 mtspr SPRN_HID0,r4
872 sync
873 b __secondary_start
874 #endif /* CONFIG_GEMINI */
875
876 .globl __secondary_start_mpc86xx
877 __secondary_start_mpc86xx:
878 mfspr r3, SPRN_PIR
879 stw r3, __secondary_hold_acknowledge@l(0)
880 mr r24, r3 /* cpu # */
881 b __secondary_start
882
883 .globl __secondary_start_pmac_0
884 __secondary_start_pmac_0:
885 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
886 li r24,0
887 b 1f
888 li r24,1
889 b 1f
890 li r24,2
891 b 1f
892 li r24,3
893 1:
894 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
895 set to map the 0xf0000000 - 0xffffffff region */
896 mfmsr r0
897 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
898 SYNC
899 mtmsr r0
900 isync
901
902 .globl __secondary_start
903 __secondary_start:
904 /* Copy some CPU settings from CPU 0 */
905 bl __restore_cpu_setup
906
907 lis r3,-KERNELBASE@h
908 mr r4,r24
909 bl call_setup_cpu /* Call setup_cpu for this CPU */
910 #ifdef CONFIG_6xx
911 lis r3,-KERNELBASE@h
912 bl init_idle_6xx
913 #endif /* CONFIG_6xx */
914
915 /* get current_thread_info and current */
916 lis r1,secondary_ti@ha
917 tophys(r1,r1)
918 lwz r1,secondary_ti@l(r1)
919 tophys(r2,r1)
920 lwz r2,TI_TASK(r2)
921
922 /* stack */
923 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
924 li r0,0
925 tophys(r3,r1)
926 stw r0,0(r3)
927
928 /* load up the MMU */
929 bl load_up_mmu
930
931 /* ptr to phys current thread */
932 tophys(r4,r2)
933 addi r4,r4,THREAD /* phys address of our thread_struct */
934 CLR_TOP32(r4)
935 mtspr SPRN_SPRG3,r4
936 li r3,0
937 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
938
939 /* enable MMU and jump to start_secondary */
940 li r4,MSR_KERNEL
941 FIX_SRR1(r4,r5)
942 lis r3,start_secondary@h
943 ori r3,r3,start_secondary@l
944 mtspr SPRN_SRR0,r3
945 mtspr SPRN_SRR1,r4
946 SYNC
947 RFI
948 #endif /* CONFIG_SMP */
949
950 /*
951 * Those generic dummy functions are kept for CPUs not
952 * included in CONFIG_6xx
953 */
954 #if !defined(CONFIG_6xx)
955 _ENTRY(__save_cpu_setup)
956 blr
957 _ENTRY(__restore_cpu_setup)
958 blr
959 #endif /* !defined(CONFIG_6xx) */
960
961
962 /*
963 * Load stuff into the MMU. Intended to be called with
964 * IR=0 and DR=0.
965 */
966 load_up_mmu:
967 sync /* Force all PTE updates to finish */
968 isync
969 tlbia /* Clear all TLB entries */
970 sync /* wait for tlbia/tlbie to finish */
971 TLBSYNC /* ... on all CPUs */
972 /* Load the SDR1 register (hash table base & size) */
973 lis r6,_SDR1@ha
974 tophys(r6,r6)
975 lwz r6,_SDR1@l(r6)
976 mtspr SPRN_SDR1,r6
977 li r0,16 /* load up segment register values */
978 mtctr r0 /* for context 0 */
979 lis r3,0x2000 /* Ku = 1, VSID = 0 */
980 li r4,0
981 3: mtsrin r3,r4
982 addi r3,r3,0x111 /* increment VSID */
983 addis r4,r4,0x1000 /* address of next segment */
984 bdnz 3b
985
986 /* Load the BAT registers with the values set up by MMU_init.
987 MMU_init takes care of whether we're on a 601 or not. */
988 mfpvr r3
989 srwi r3,r3,16
990 cmpwi r3,1
991 lis r3,BATS@ha
992 addi r3,r3,BATS@l
993 tophys(r3,r3)
994 LOAD_BAT(0,r3,r4,r5)
995 LOAD_BAT(1,r3,r4,r5)
996 LOAD_BAT(2,r3,r4,r5)
997 LOAD_BAT(3,r3,r4,r5)
998 BEGIN_MMU_FTR_SECTION
999 LOAD_BAT(4,r3,r4,r5)
1000 LOAD_BAT(5,r3,r4,r5)
1001 LOAD_BAT(6,r3,r4,r5)
1002 LOAD_BAT(7,r3,r4,r5)
1003 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1004 blr
1005
1006 /*
1007 * This is where the main kernel code starts.
1008 */
1009 start_here:
1010 /* ptr to current */
1011 lis r2,init_task@h
1012 ori r2,r2,init_task@l
1013 /* Set up for using our exception vectors */
1014 /* ptr to phys current thread */
1015 tophys(r4,r2)
1016 addi r4,r4,THREAD /* init task's THREAD */
1017 CLR_TOP32(r4)
1018 mtspr SPRN_SPRG3,r4
1019 li r3,0
1020 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1021
1022 /* stack */
1023 lis r1,init_thread_union@ha
1024 addi r1,r1,init_thread_union@l
1025 li r0,0
1026 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1027 /*
1028 * Do early platform-specific initialization,
1029 * and set up the MMU.
1030 */
1031 mr r3,r31
1032 mr r4,r30
1033 bl machine_init
1034 bl __save_cpu_setup
1035 bl MMU_init
1036
1037 /*
1038 * Go back to running unmapped so we can load up new values
1039 * for SDR1 (hash table pointer) and the segment registers
1040 * and change to using our exception vectors.
1041 */
1042 lis r4,2f@h
1043 ori r4,r4,2f@l
1044 tophys(r4,r4)
1045 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1046 FIX_SRR1(r3,r5)
1047 mtspr SPRN_SRR0,r4
1048 mtspr SPRN_SRR1,r3
1049 SYNC
1050 RFI
1051 /* Load up the kernel context */
1052 2: bl load_up_mmu
1053
1054 #ifdef CONFIG_BDI_SWITCH
1055 /* Add helper information for the Abatron bdiGDB debugger.
1056 * We do this here because we know the mmu is disabled, and
1057 * will be enabled for real in just a few instructions.
1058 */
1059 lis r5, abatron_pteptrs@h
1060 ori r5, r5, abatron_pteptrs@l
1061 stw r5, 0xf0(r0) /* This much match your Abatron config */
1062 lis r6, swapper_pg_dir@h
1063 ori r6, r6, swapper_pg_dir@l
1064 tophys(r5, r5)
1065 stw r6, 0(r5)
1066 #endif /* CONFIG_BDI_SWITCH */
1067
1068 /* Now turn on the MMU for real! */
1069 li r4,MSR_KERNEL
1070 FIX_SRR1(r4,r5)
1071 lis r3,start_kernel@h
1072 ori r3,r3,start_kernel@l
1073 mtspr SPRN_SRR0,r3
1074 mtspr SPRN_SRR1,r4
1075 SYNC
1076 RFI
1077
1078 /*
1079 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1080 *
1081 * Set up the segment registers for a new context.
1082 */
1083 _ENTRY(switch_mmu_context)
1084 lwz r3,MMCONTEXTID(r4)
1085 cmpwi cr0,r3,0
1086 blt- 4f
1087 mulli r3,r3,897 /* multiply context by skew factor */
1088 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1089 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1090 li r0,NUM_USER_SEGMENTS
1091 mtctr r0
1092
1093 #ifdef CONFIG_BDI_SWITCH
1094 /* Context switch the PTE pointer for the Abatron BDI2000.
1095 * The PGDIR is passed as second argument.
1096 */
1097 lwz r4,MM_PGD(r4)
1098 lis r5, KERNELBASE@h
1099 lwz r5, 0xf0(r5)
1100 stw r4, 0x4(r5)
1101 #endif
1102 li r4,0
1103 isync
1104 3:
1105 mtsrin r3,r4
1106 addi r3,r3,0x111 /* next VSID */
1107 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1108 addis r4,r4,0x1000 /* address of next segment */
1109 bdnz 3b
1110 sync
1111 isync
1112 blr
1113 4: trap
1114 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1115 blr
1116
1117 /*
1118 * An undocumented "feature" of 604e requires that the v bit
1119 * be cleared before changing BAT values.
1120 *
1121 * Also, newer IBM firmware does not clear bat3 and 4 so
1122 * this makes sure it's done.
1123 * -- Cort
1124 */
1125 clear_bats:
1126 li r10,0
1127 mfspr r9,SPRN_PVR
1128 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1129 cmpwi r9, 1
1130 beq 1f
1131
1132 mtspr SPRN_DBAT0U,r10
1133 mtspr SPRN_DBAT0L,r10
1134 mtspr SPRN_DBAT1U,r10
1135 mtspr SPRN_DBAT1L,r10
1136 mtspr SPRN_DBAT2U,r10
1137 mtspr SPRN_DBAT2L,r10
1138 mtspr SPRN_DBAT3U,r10
1139 mtspr SPRN_DBAT3L,r10
1140 1:
1141 mtspr SPRN_IBAT0U,r10
1142 mtspr SPRN_IBAT0L,r10
1143 mtspr SPRN_IBAT1U,r10
1144 mtspr SPRN_IBAT1L,r10
1145 mtspr SPRN_IBAT2U,r10
1146 mtspr SPRN_IBAT2L,r10
1147 mtspr SPRN_IBAT3U,r10
1148 mtspr SPRN_IBAT3L,r10
1149 BEGIN_MMU_FTR_SECTION
1150 /* Here's a tweak: at this point, CPU setup have
1151 * not been called yet, so HIGH_BAT_EN may not be
1152 * set in HID0 for the 745x processors. However, it
1153 * seems that doesn't affect our ability to actually
1154 * write to these SPRs.
1155 */
1156 mtspr SPRN_DBAT4U,r10
1157 mtspr SPRN_DBAT4L,r10
1158 mtspr SPRN_DBAT5U,r10
1159 mtspr SPRN_DBAT5L,r10
1160 mtspr SPRN_DBAT6U,r10
1161 mtspr SPRN_DBAT6L,r10
1162 mtspr SPRN_DBAT7U,r10
1163 mtspr SPRN_DBAT7L,r10
1164 mtspr SPRN_IBAT4U,r10
1165 mtspr SPRN_IBAT4L,r10
1166 mtspr SPRN_IBAT5U,r10
1167 mtspr SPRN_IBAT5L,r10
1168 mtspr SPRN_IBAT6U,r10
1169 mtspr SPRN_IBAT6L,r10
1170 mtspr SPRN_IBAT7U,r10
1171 mtspr SPRN_IBAT7L,r10
1172 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1173 blr
1174
1175 flush_tlbs:
1176 lis r10, 0x40
1177 1: addic. r10, r10, -0x1000
1178 tlbie r10
1179 bgt 1b
1180 sync
1181 blr
1182
1183 mmu_off:
1184 addi r4, r3, __after_mmu_off - _start
1185 mfmsr r3
1186 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1187 beqlr
1188 andc r3,r3,r0
1189 mtspr SPRN_SRR0,r4
1190 mtspr SPRN_SRR1,r3
1191 sync
1192 RFI
1193
1194 /*
1195 * Use the first pair of BAT registers to map the 1st 16MB
1196 * of RAM to PAGE_OFFSET. From this point on we can't safely
1197 * call OF any more.
1198 */
1199 initial_bats:
1200 lis r11,PAGE_OFFSET@h
1201 mfspr r9,SPRN_PVR
1202 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1203 cmpwi 0,r9,1
1204 bne 4f
1205 ori r11,r11,4 /* set up BAT registers for 601 */
1206 li r8,0x7f /* valid, block length = 8MB */
1207 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1208 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1209 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1210 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1211 mtspr SPRN_IBAT1U,r9
1212 mtspr SPRN_IBAT1L,r10
1213 isync
1214 blr
1215
1216 4: tophys(r8,r11)
1217 #ifdef CONFIG_SMP
1218 ori r8,r8,0x12 /* R/W access, M=1 */
1219 #else
1220 ori r8,r8,2 /* R/W access */
1221 #endif /* CONFIG_SMP */
1222 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1223
1224 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1225 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1226 mtspr SPRN_IBAT0L,r8
1227 mtspr SPRN_IBAT0U,r11
1228 isync
1229 blr
1230
1231
1232 #ifdef CONFIG_BOOTX_TEXT
1233 setup_disp_bat:
1234 /*
1235 * setup the display bat prepared for us in prom.c
1236 */
1237 mflr r8
1238 bl reloc_offset
1239 mtlr r8
1240 addis r8,r3,disp_BAT@ha
1241 addi r8,r8,disp_BAT@l
1242 cmpwi cr0,r8,0
1243 beqlr
1244 lwz r11,0(r8)
1245 lwz r8,4(r8)
1246 mfspr r9,SPRN_PVR
1247 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1248 cmpwi 0,r9,1
1249 beq 1f
1250 mtspr SPRN_DBAT3L,r8
1251 mtspr SPRN_DBAT3U,r11
1252 blr
1253 1: mtspr SPRN_IBAT3L,r8
1254 mtspr SPRN_IBAT3U,r11
1255 blr
1256 #endif /* CONFIG_BOOTX_TEXT */
1257
1258 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1259 setup_cpm_bat:
1260 lis r8, 0xf000
1261 ori r8, r8, 0x002a
1262 mtspr SPRN_DBAT1L, r8
1263
1264 lis r11, 0xf000
1265 ori r11, r11, (BL_1M << 2) | 2
1266 mtspr SPRN_DBAT1U, r11
1267
1268 blr
1269 #endif
1270
1271 #ifdef CONFIG_8260
1272 /* Jump into the system reset for the rom.
1273 * We first disable the MMU, and then jump to the ROM reset address.
1274 *
1275 * r3 is the board info structure, r4 is the location for starting.
1276 * I use this for building a small kernel that can load other kernels,
1277 * rather than trying to write or rely on a rom monitor that can tftp load.
1278 */
1279 .globl m8260_gorom
1280 m8260_gorom:
1281 mfmsr r0
1282 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1283 sync
1284 mtmsr r0
1285 sync
1286 mfspr r11, SPRN_HID0
1287 lis r10, 0
1288 ori r10,r10,HID0_ICE|HID0_DCE
1289 andc r11, r11, r10
1290 mtspr SPRN_HID0, r11
1291 isync
1292 li r5, MSR_ME|MSR_RI
1293 lis r6,2f@h
1294 addis r6,r6,-KERNELBASE@h
1295 ori r6,r6,2f@l
1296 mtspr SPRN_SRR0,r6
1297 mtspr SPRN_SRR1,r5
1298 isync
1299 sync
1300 rfi
1301 2:
1302 mtlr r4
1303 blr
1304 #endif
1305
1306
1307 /*
1308 * We put a few things here that have to be page-aligned.
1309 * This stuff goes at the beginning of the data segment,
1310 * which is page-aligned.
1311 */
1312 .data
1313 .globl sdata
1314 sdata:
1315 .globl empty_zero_page
1316 empty_zero_page:
1317 .space 4096
1318
1319 .globl swapper_pg_dir
1320 swapper_pg_dir:
1321 .space PGD_TABLE_SIZE
1322
1323 .globl intercept_table
1324 intercept_table:
1325 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1326 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1327 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1328 .long 0, 0, 0, 0, 0, 0, 0, 0
1329 .long 0, 0, 0, 0, 0, 0, 0, 0
1330 .long 0, 0, 0, 0, 0, 0, 0, 0
1331
1332 /* Room for two PTE pointers, usually the kernel and current user pointers
1333 * to their respective root page table.
1334 */
1335 abatron_pteptrs:
1336 .space 8
Linux kernel - Deliverables
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