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[deliverable/linux.git] / arch / powerpc / kernel / head_32.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/mmu.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/ptrace.h>
34 #include <asm/bug.h>
35
36 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
39 li RA,0; \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 beq 1f; \
47 lwz RA,(n*16)+8(reg); \
48 lwz RB,(n*16)+12(reg); \
49 mtspr SPRN_DBAT##n##U,RA; \
50 mtspr SPRN_DBAT##n##L,RB; \
51 1:
52
53 .section .text.head, "ax"
54 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
55 .stabs "head_32.S",N_SO,0,0,0f
56 0:
57 _ENTRY(_stext);
58
59 /*
60 * _start is defined this way because the XCOFF loader in the OpenFirmware
61 * on the powermac expects the entry point to be a procedure descriptor.
62 */
63 _ENTRY(_start);
64 /*
65 * These are here for legacy reasons, the kernel used to
66 * need to look like a coff function entry for the pmac
67 * but we're always started by some kind of bootloader now.
68 * -- Cort
69 */
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
72 nop
73
74 /* PMAC
75 * Enter here with the kernel text, data and bss loaded starting at
76 * 0, running with virtual == physical mapping.
77 * r5 points to the prom entry point (the client interface handler
78 * address). Address translation is turned on, with the prom
79 * managing the hash table. Interrupts are disabled. The stack
80 * pointer (r1) points to just below the end of the half-meg region
81 * from 0x380000 - 0x400000, which is mapped in already.
82 *
83 * If we are booted from MacOS via BootX, we enter with the kernel
84 * image loaded somewhere, and the following values in registers:
85 * r3: 'BooX' (0x426f6f58)
86 * r4: virtual address of boot_infos_t
87 * r5: 0
88 *
89 * PREP
90 * This is jumped to on prep systems right after the kernel is relocated
91 * to its proper place in memory by the boot loader. The expected layout
92 * of the regs is:
93 * r3: ptr to residual data
94 * r4: initrd_start or if no initrd then 0
95 * r5: initrd_end - unused if r4 is 0
96 * r6: Start of command line string
97 * r7: End of command line string
98 *
99 * This just gets a minimal mmu environment setup so we can call
100 * start_here() to do the real work.
101 * -- Cort
102 */
103
104 .globl __start
105 __start:
106 /*
107 * We have to do any OF calls before we map ourselves to KERNELBASE,
108 * because OF may have I/O devices mapped into that area
109 * (particularly on CHRP).
110 */
111 #ifdef CONFIG_PPC_MULTIPLATFORM
112 cmpwi 0,r5,0
113 beq 1f
114
115 /* find out where we are now */
116 bcl 20,31,$+4
117 0: mflr r8 /* r8 = runtime addr here */
118 addis r8,r8,(_stext - 0b)@ha
119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
120 bl prom_init
121 trap
122 #endif
123
124 /*
125 * Check for BootX signature when supporting PowerMac and branch to
126 * appropriate trampoline if it's present
127 */
128 #ifdef CONFIG_PPC_PMAC
129 1: lis r31,0x426f
130 ori r31,r31,0x6f58
131 cmpw 0,r3,r31
132 bne 1f
133 bl bootx_init
134 trap
135 #endif /* CONFIG_PPC_PMAC */
136
137 1: mr r31,r3 /* save parameters */
138 mr r30,r4
139 li r24,0 /* cpu # */
140
141 /*
142 * early_init() does the early machine identification and does
143 * the necessary low-level setup and clears the BSS
144 * -- Cort <cort@fsmlabs.com>
145 */
146 bl early_init
147
148 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
149 * the physical address we are running at, returned by early_init()
150 */
151 bl mmu_off
152 __after_mmu_off:
153 bl clear_bats
154 bl flush_tlbs
155
156 bl initial_bats
157 #if defined(CONFIG_BOOTX_TEXT)
158 bl setup_disp_bat
159 #endif
160 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
161 bl setup_cpm_bat
162 #endif
163
164 /*
165 * Call setup_cpu for CPU 0 and initialize 6xx Idle
166 */
167 bl reloc_offset
168 li r24,0 /* cpu# */
169 bl call_setup_cpu /* Call setup_cpu for this CPU */
170 #ifdef CONFIG_6xx
171 bl reloc_offset
172 bl init_idle_6xx
173 #endif /* CONFIG_6xx */
174
175
176 /*
177 * We need to run with _start at physical address 0.
178 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
179 * the exception vectors at 0 (and therefore this copy
180 * overwrites OF's exception vectors with our own).
181 * The MMU is off at this point.
182 */
183 bl reloc_offset
184 mr r26,r3
185 addis r4,r3,KERNELBASE@h /* current address of _start */
186 lis r5,PHYSICAL_START@h
187 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
188 bne relocate_kernel
189 /*
190 * we now have the 1st 16M of ram mapped with the bats.
191 * prep needs the mmu to be turned on here, but pmac already has it on.
192 * this shouldn't bother the pmac since it just gets turned on again
193 * as we jump to our code at KERNELBASE. -- Cort
194 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
195 * off, and in other cases, we now turn it off before changing BATs above.
196 */
197 turn_on_mmu:
198 mfmsr r0
199 ori r0,r0,MSR_DR|MSR_IR
200 mtspr SPRN_SRR1,r0
201 lis r0,start_here@h
202 ori r0,r0,start_here@l
203 mtspr SPRN_SRR0,r0
204 SYNC
205 RFI /* enables MMU */
206
207 /*
208 * We need __secondary_hold as a place to hold the other cpus on
209 * an SMP machine, even when we are running a UP kernel.
210 */
211 . = 0xc0 /* for prep bootloader */
212 li r3,1 /* MTX only has 1 cpu */
213 .globl __secondary_hold
214 __secondary_hold:
215 /* tell the master we're here */
216 stw r3,__secondary_hold_acknowledge@l(0)
217 #ifdef CONFIG_SMP
218 100: lwz r4,0(0)
219 /* wait until we're told to start */
220 cmpw 0,r4,r3
221 bne 100b
222 /* our cpu # was at addr 0 - go */
223 mr r24,r3 /* cpu # */
224 b __secondary_start
225 #else
226 b .
227 #endif /* CONFIG_SMP */
228
229 .globl __secondary_hold_spinloop
230 __secondary_hold_spinloop:
231 .long 0
232 .globl __secondary_hold_acknowledge
233 __secondary_hold_acknowledge:
234 .long -1
235
236 /*
237 * Exception entry code. This code runs with address translation
238 * turned off, i.e. using physical addresses.
239 * We assume sprg3 has the physical address of the current
240 * task's thread_struct.
241 */
242 #define EXCEPTION_PROLOG \
243 mtspr SPRN_SPRG0,r10; \
244 mtspr SPRN_SPRG1,r11; \
245 mfcr r10; \
246 EXCEPTION_PROLOG_1; \
247 EXCEPTION_PROLOG_2
248
249 #define EXCEPTION_PROLOG_1 \
250 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
251 andi. r11,r11,MSR_PR; \
252 tophys(r11,r1); /* use tophys(r1) if kernel */ \
253 beq 1f; \
254 mfspr r11,SPRN_SPRG3; \
255 lwz r11,THREAD_INFO-THREAD(r11); \
256 addi r11,r11,THREAD_SIZE; \
257 tophys(r11,r11); \
258 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
259
260
261 #define EXCEPTION_PROLOG_2 \
262 CLR_TOP32(r11); \
263 stw r10,_CCR(r11); /* save registers */ \
264 stw r12,GPR12(r11); \
265 stw r9,GPR9(r11); \
266 mfspr r10,SPRN_SPRG0; \
267 stw r10,GPR10(r11); \
268 mfspr r12,SPRN_SPRG1; \
269 stw r12,GPR11(r11); \
270 mflr r10; \
271 stw r10,_LINK(r11); \
272 mfspr r12,SPRN_SRR0; \
273 mfspr r9,SPRN_SRR1; \
274 stw r1,GPR1(r11); \
275 stw r1,0(r11); \
276 tovirt(r1,r11); /* set new kernel sp */ \
277 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
278 MTMSRD(r10); /* (except for mach check in rtas) */ \
279 stw r0,GPR0(r11); \
280 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
281 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
282 stw r10,8(r11); \
283 SAVE_4GPRS(3, r11); \
284 SAVE_2GPRS(7, r11)
285
286 /*
287 * Note: code which follows this uses cr0.eq (set if from kernel),
288 * r11, r12 (SRR0), and r9 (SRR1).
289 *
290 * Note2: once we have set r1 we are in a position to take exceptions
291 * again, and we could thus set MSR:RI at that point.
292 */
293
294 /*
295 * Exception vectors.
296 */
297 #define EXCEPTION(n, label, hdlr, xfer) \
298 . = n; \
299 label: \
300 EXCEPTION_PROLOG; \
301 addi r3,r1,STACK_FRAME_OVERHEAD; \
302 xfer(n, hdlr)
303
304 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
305 li r10,trap; \
306 stw r10,_TRAP(r11); \
307 li r10,MSR_KERNEL; \
308 copyee(r10, r9); \
309 bl tfer; \
310 i##n: \
311 .long hdlr; \
312 .long ret
313
314 #define COPY_EE(d, s) rlwimi d,s,0,16,16
315 #define NOCOPY(d, s)
316
317 #define EXC_XFER_STD(n, hdlr) \
318 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
319 ret_from_except_full)
320
321 #define EXC_XFER_LITE(n, hdlr) \
322 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
323 ret_from_except)
324
325 #define EXC_XFER_EE(n, hdlr) \
326 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
327 ret_from_except_full)
328
329 #define EXC_XFER_EE_LITE(n, hdlr) \
330 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
331 ret_from_except)
332
333 /* System reset */
334 /* core99 pmac starts the seconary here by changing the vector, and
335 putting it back to what it was (unknown_exception) when done. */
336 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
337
338 /* Machine check */
339 /*
340 * On CHRP, this is complicated by the fact that we could get a
341 * machine check inside RTAS, and we have no guarantee that certain
342 * critical registers will have the values we expect. The set of
343 * registers that might have bad values includes all the GPRs
344 * and all the BATs. We indicate that we are in RTAS by putting
345 * a non-zero value, the address of the exception frame to use,
346 * in SPRG2. The machine check handler checks SPRG2 and uses its
347 * value if it is non-zero. If we ever needed to free up SPRG2,
348 * we could use a field in the thread_info or thread_struct instead.
349 * (Other exception handlers assume that r1 is a valid kernel stack
350 * pointer when we take an exception from supervisor mode.)
351 * -- paulus.
352 */
353 . = 0x200
354 mtspr SPRN_SPRG0,r10
355 mtspr SPRN_SPRG1,r11
356 mfcr r10
357 #ifdef CONFIG_PPC_CHRP
358 mfspr r11,SPRN_SPRG2
359 cmpwi 0,r11,0
360 bne 7f
361 #endif /* CONFIG_PPC_CHRP */
362 EXCEPTION_PROLOG_1
363 7: EXCEPTION_PROLOG_2
364 addi r3,r1,STACK_FRAME_OVERHEAD
365 #ifdef CONFIG_PPC_CHRP
366 mfspr r4,SPRN_SPRG2
367 cmpwi cr1,r4,0
368 bne cr1,1f
369 #endif
370 EXC_XFER_STD(0x200, machine_check_exception)
371 #ifdef CONFIG_PPC_CHRP
372 1: b machine_check_in_rtas
373 #endif
374
375 /* Data access exception. */
376 . = 0x300
377 DataAccess:
378 EXCEPTION_PROLOG
379 mfspr r10,SPRN_DSISR
380 stw r10,_DSISR(r11)
381 andis. r0,r10,0xa470 /* weird error? */
382 bne 1f /* if not, try to put a PTE */
383 mfspr r4,SPRN_DAR /* into the hash table */
384 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
385 bl hash_page
386 1: lwz r5,_DSISR(r11) /* get DSISR value */
387 mfspr r4,SPRN_DAR
388 EXC_XFER_EE_LITE(0x300, handle_page_fault)
389
390
391 /* Instruction access exception. */
392 . = 0x400
393 InstructionAccess:
394 EXCEPTION_PROLOG
395 andis. r0,r9,0x4000 /* no pte found? */
396 beq 1f /* if so, try to put a PTE */
397 li r3,0 /* into the hash table */
398 mr r4,r12 /* SRR0 is fault address */
399 bl hash_page
400 1: mr r4,r12
401 mr r5,r9
402 EXC_XFER_EE_LITE(0x400, handle_page_fault)
403
404 /* External interrupt */
405 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
406
407 /* Alignment exception */
408 . = 0x600
409 Alignment:
410 EXCEPTION_PROLOG
411 mfspr r4,SPRN_DAR
412 stw r4,_DAR(r11)
413 mfspr r5,SPRN_DSISR
414 stw r5,_DSISR(r11)
415 addi r3,r1,STACK_FRAME_OVERHEAD
416 EXC_XFER_EE(0x600, alignment_exception)
417
418 /* Program check exception */
419 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
420
421 /* Floating-point unavailable */
422 . = 0x800
423 FPUnavailable:
424 BEGIN_FTR_SECTION
425 /*
426 * Certain Freescale cores don't have a FPU and treat fp instructions
427 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
428 */
429 b ProgramCheck
430 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
431 EXCEPTION_PROLOG
432 beq 1f
433 bl load_up_fpu /* if from user, just load it up */
434 b fast_exception_return
435 1: addi r3,r1,STACK_FRAME_OVERHEAD
436 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
437
438 /* Decrementer */
439 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
440
441 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
442 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
443
444 /* System call */
445 . = 0xc00
446 SystemCall:
447 EXCEPTION_PROLOG
448 EXC_XFER_EE_LITE(0xc00, DoSyscall)
449
450 /* Single step - not used on 601 */
451 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
452 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
453
454 /*
455 * The Altivec unavailable trap is at 0x0f20. Foo.
456 * We effectively remap it to 0x3000.
457 * We include an altivec unavailable exception vector even if
458 * not configured for Altivec, so that you can't panic a
459 * non-altivec kernel running on a machine with altivec just
460 * by executing an altivec instruction.
461 */
462 . = 0xf00
463 b PerformanceMonitor
464
465 . = 0xf20
466 b AltiVecUnavailable
467
468 /*
469 * Handle TLB miss for instruction on 603/603e.
470 * Note: we get an alternate set of r0 - r3 to use automatically.
471 */
472 . = 0x1000
473 InstructionTLBMiss:
474 /*
475 * r0: stored ctr
476 * r1: linux style pte ( later becomes ppc hardware pte )
477 * r2: ptr to linux-style pte
478 * r3: scratch
479 */
480 mfctr r0
481 /* Get PTE (linux-style) and check access */
482 mfspr r3,SPRN_IMISS
483 lis r1,PAGE_OFFSET@h /* check if kernel address */
484 cmplw 0,r1,r3
485 mfspr r2,SPRN_SPRG3
486 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
487 lwz r2,PGDIR(r2)
488 bge- 112f
489 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
490 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
491 lis r2,swapper_pg_dir@ha /* if kernel address, use */
492 addi r2,r2,swapper_pg_dir@l /* kernel page table */
493 112: tophys(r2,r2)
494 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
495 lwz r2,0(r2) /* get pmd entry */
496 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
497 beq- InstructionAddressInvalid /* return if no mapping */
498 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
499 lwz r3,0(r2) /* get linux-style pte */
500 andc. r1,r1,r3 /* check access & ~permission */
501 bne- InstructionAddressInvalid /* return if access not permitted */
502 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
503 /*
504 * NOTE! We are assuming this is not an SMP system, otherwise
505 * we would need to update the pte atomically with lwarx/stwcx.
506 */
507 stw r3,0(r2) /* update PTE (accessed bit) */
508 /* Convert linux-style PTE to low word of PPC-style PTE */
509 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
510 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
511 and r1,r1,r2 /* writable if _RW and _DIRTY */
512 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
513 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
514 ori r1,r1,0xe14 /* clear out reserved bits and M */
515 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
516 mtspr SPRN_RPA,r1
517 mfspr r3,SPRN_IMISS
518 tlbli r3
519 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
520 mtcrf 0x80,r3
521 rfi
522 InstructionAddressInvalid:
523 mfspr r3,SPRN_SRR1
524 rlwinm r1,r3,9,6,6 /* Get load/store bit */
525
526 addis r1,r1,0x2000
527 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
528 mtctr r0 /* Restore CTR */
529 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
530 or r2,r2,r1
531 mtspr SPRN_SRR1,r2
532 mfspr r1,SPRN_IMISS /* Get failing address */
533 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
534 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
535 xor r1,r1,r2
536 mtspr SPRN_DAR,r1 /* Set fault address */
537 mfmsr r0 /* Restore "normal" registers */
538 xoris r0,r0,MSR_TGPR>>16
539 mtcrf 0x80,r3 /* Restore CR0 */
540 mtmsr r0
541 b InstructionAccess
542
543 /*
544 * Handle TLB miss for DATA Load operation on 603/603e
545 */
546 . = 0x1100
547 DataLoadTLBMiss:
548 /*
549 * r0: stored ctr
550 * r1: linux style pte ( later becomes ppc hardware pte )
551 * r2: ptr to linux-style pte
552 * r3: scratch
553 */
554 mfctr r0
555 /* Get PTE (linux-style) and check access */
556 mfspr r3,SPRN_DMISS
557 lis r1,PAGE_OFFSET@h /* check if kernel address */
558 cmplw 0,r1,r3
559 mfspr r2,SPRN_SPRG3
560 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
561 lwz r2,PGDIR(r2)
562 bge- 112f
563 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
564 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
565 lis r2,swapper_pg_dir@ha /* if kernel address, use */
566 addi r2,r2,swapper_pg_dir@l /* kernel page table */
567 112: tophys(r2,r2)
568 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
569 lwz r2,0(r2) /* get pmd entry */
570 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
571 beq- DataAddressInvalid /* return if no mapping */
572 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
573 lwz r3,0(r2) /* get linux-style pte */
574 andc. r1,r1,r3 /* check access & ~permission */
575 bne- DataAddressInvalid /* return if access not permitted */
576 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
577 /*
578 * NOTE! We are assuming this is not an SMP system, otherwise
579 * we would need to update the pte atomically with lwarx/stwcx.
580 */
581 stw r3,0(r2) /* update PTE (accessed bit) */
582 /* Convert linux-style PTE to low word of PPC-style PTE */
583 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
584 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
585 and r1,r1,r2 /* writable if _RW and _DIRTY */
586 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
587 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
588 ori r1,r1,0xe14 /* clear out reserved bits and M */
589 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
590 mtspr SPRN_RPA,r1
591 mfspr r3,SPRN_DMISS
592 tlbld r3
593 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
594 mtcrf 0x80,r3
595 rfi
596 DataAddressInvalid:
597 mfspr r3,SPRN_SRR1
598 rlwinm r1,r3,9,6,6 /* Get load/store bit */
599 addis r1,r1,0x2000
600 mtspr SPRN_DSISR,r1
601 mtctr r0 /* Restore CTR */
602 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
603 mtspr SPRN_SRR1,r2
604 mfspr r1,SPRN_DMISS /* Get failing address */
605 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
606 beq 20f /* Jump if big endian */
607 xori r1,r1,3
608 20: mtspr SPRN_DAR,r1 /* Set fault address */
609 mfmsr r0 /* Restore "normal" registers */
610 xoris r0,r0,MSR_TGPR>>16
611 mtcrf 0x80,r3 /* Restore CR0 */
612 mtmsr r0
613 b DataAccess
614
615 /*
616 * Handle TLB miss for DATA Store on 603/603e
617 */
618 . = 0x1200
619 DataStoreTLBMiss:
620 /*
621 * r0: stored ctr
622 * r1: linux style pte ( later becomes ppc hardware pte )
623 * r2: ptr to linux-style pte
624 * r3: scratch
625 */
626 mfctr r0
627 /* Get PTE (linux-style) and check access */
628 mfspr r3,SPRN_DMISS
629 lis r1,PAGE_OFFSET@h /* check if kernel address */
630 cmplw 0,r1,r3
631 mfspr r2,SPRN_SPRG3
632 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
633 lwz r2,PGDIR(r2)
634 bge- 112f
635 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
636 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
637 lis r2,swapper_pg_dir@ha /* if kernel address, use */
638 addi r2,r2,swapper_pg_dir@l /* kernel page table */
639 112: tophys(r2,r2)
640 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
641 lwz r2,0(r2) /* get pmd entry */
642 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
643 beq- DataAddressInvalid /* return if no mapping */
644 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
645 lwz r3,0(r2) /* get linux-style pte */
646 andc. r1,r1,r3 /* check access & ~permission */
647 bne- DataAddressInvalid /* return if access not permitted */
648 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
649 /*
650 * NOTE! We are assuming this is not an SMP system, otherwise
651 * we would need to update the pte atomically with lwarx/stwcx.
652 */
653 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
654 /* Convert linux-style PTE to low word of PPC-style PTE */
655 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
656 li r1,0xe15 /* clear out reserved bits and M */
657 andc r1,r3,r1 /* PP = user? 2: 0 */
658 mtspr SPRN_RPA,r1
659 mfspr r3,SPRN_DMISS
660 tlbld r3
661 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
662 mtcrf 0x80,r3
663 rfi
664
665 #ifndef CONFIG_ALTIVEC
666 #define altivec_assist_exception unknown_exception
667 #endif
668
669 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
670 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
671 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
672 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
673 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
674 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
677 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
683 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
690 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
691 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
692 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
693 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
694 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
695 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
698
699 .globl mol_trampoline
700 .set mol_trampoline, i0x2f00
701
702 . = 0x3000
703
704 AltiVecUnavailable:
705 EXCEPTION_PROLOG
706 #ifdef CONFIG_ALTIVEC
707 bne load_up_altivec /* if from user, just load it up */
708 #endif /* CONFIG_ALTIVEC */
709 addi r3,r1,STACK_FRAME_OVERHEAD
710 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
711
712 PerformanceMonitor:
713 EXCEPTION_PROLOG
714 addi r3,r1,STACK_FRAME_OVERHEAD
715 EXC_XFER_STD(0xf00, performance_monitor_exception)
716
717 #ifdef CONFIG_ALTIVEC
718 /* Note that the AltiVec support is closely modeled after the FP
719 * support. Changes to one are likely to be applicable to the
720 * other! */
721 load_up_altivec:
722 /*
723 * Disable AltiVec for the task which had AltiVec previously,
724 * and save its AltiVec registers in its thread_struct.
725 * Enables AltiVec for use in the kernel on return.
726 * On SMP we know the AltiVec units are free, since we give it up every
727 * switch. -- Kumar
728 */
729 mfmsr r5
730 oris r5,r5,MSR_VEC@h
731 MTMSRD(r5) /* enable use of AltiVec now */
732 isync
733 /*
734 * For SMP, we don't do lazy AltiVec switching because it just gets too
735 * horrendously complex, especially when a task switches from one CPU
736 * to another. Instead we call giveup_altivec in switch_to.
737 */
738 #ifndef CONFIG_SMP
739 tophys(r6,0)
740 addis r3,r6,last_task_used_altivec@ha
741 lwz r4,last_task_used_altivec@l(r3)
742 cmpwi 0,r4,0
743 beq 1f
744 add r4,r4,r6
745 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
746 SAVE_32VRS(0,r10,r4)
747 mfvscr vr0
748 li r10,THREAD_VSCR
749 stvx vr0,r10,r4
750 lwz r5,PT_REGS(r4)
751 add r5,r5,r6
752 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
753 lis r10,MSR_VEC@h
754 andc r4,r4,r10 /* disable altivec for previous task */
755 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
756 1:
757 #endif /* CONFIG_SMP */
758 /* enable use of AltiVec after return */
759 oris r9,r9,MSR_VEC@h
760 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
761 li r4,1
762 li r10,THREAD_VSCR
763 stw r4,THREAD_USED_VR(r5)
764 lvx vr0,r10,r5
765 mtvscr vr0
766 REST_32VRS(0,r10,r5)
767 #ifndef CONFIG_SMP
768 subi r4,r5,THREAD
769 sub r4,r4,r6
770 stw r4,last_task_used_altivec@l(r3)
771 #endif /* CONFIG_SMP */
772 /* restore registers and return */
773 /* we haven't used ctr or xer or lr */
774 b fast_exception_return
775
776 /*
777 * giveup_altivec(tsk)
778 * Disable AltiVec for the task given as the argument,
779 * and save the AltiVec registers in its thread_struct.
780 * Enables AltiVec for use in the kernel on return.
781 */
782
783 .globl giveup_altivec
784 giveup_altivec:
785 mfmsr r5
786 oris r5,r5,MSR_VEC@h
787 SYNC
788 MTMSRD(r5) /* enable use of AltiVec now */
789 isync
790 cmpwi 0,r3,0
791 beqlr- /* if no previous owner, done */
792 addi r3,r3,THREAD /* want THREAD of task */
793 lwz r5,PT_REGS(r3)
794 cmpwi 0,r5,0
795 SAVE_32VRS(0, r4, r3)
796 mfvscr vr0
797 li r4,THREAD_VSCR
798 stvx vr0,r4,r3
799 beq 1f
800 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
801 lis r3,MSR_VEC@h
802 andc r4,r4,r3 /* disable AltiVec for previous task */
803 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
804 1:
805 #ifndef CONFIG_SMP
806 li r5,0
807 lis r4,last_task_used_altivec@ha
808 stw r5,last_task_used_altivec@l(r4)
809 #endif /* CONFIG_SMP */
810 blr
811 #endif /* CONFIG_ALTIVEC */
812
813 /*
814 * This code is jumped to from the startup code to copy
815 * the kernel image to physical address PHYSICAL_START.
816 */
817 relocate_kernel:
818 addis r9,r26,klimit@ha /* fetch klimit */
819 lwz r25,klimit@l(r9)
820 addis r25,r25,-KERNELBASE@h
821 lis r3,PHYSICAL_START@h /* Destination base address */
822 li r6,0 /* Destination offset */
823 li r5,0x4000 /* # bytes of memory to copy */
824 bl copy_and_flush /* copy the first 0x4000 bytes */
825 addi r0,r3,4f@l /* jump to the address of 4f */
826 mtctr r0 /* in copy and do the rest. */
827 bctr /* jump to the copy */
828 4: mr r5,r25
829 bl copy_and_flush /* copy the rest */
830 b turn_on_mmu
831
832 /*
833 * Copy routine used to copy the kernel to start at physical address 0
834 * and flush and invalidate the caches as needed.
835 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
836 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
837 */
838 _ENTRY(copy_and_flush)
839 addi r5,r5,-4
840 addi r6,r6,-4
841 4: li r0,L1_CACHE_BYTES/4
842 mtctr r0
843 3: addi r6,r6,4 /* copy a cache line */
844 lwzx r0,r6,r4
845 stwx r0,r6,r3
846 bdnz 3b
847 dcbst r6,r3 /* write it to memory */
848 sync
849 icbi r6,r3 /* flush the icache line */
850 cmplw 0,r6,r5
851 blt 4b
852 sync /* additional sync needed on g4 */
853 isync
854 addi r5,r5,4
855 addi r6,r6,4
856 blr
857
858 #ifdef CONFIG_SMP
859 #ifdef CONFIG_GEMINI
860 .globl __secondary_start_gemini
861 __secondary_start_gemini:
862 mfspr r4,SPRN_HID0
863 ori r4,r4,HID0_ICFI
864 li r3,0
865 ori r3,r3,HID0_ICE
866 andc r4,r4,r3
867 mtspr SPRN_HID0,r4
868 sync
869 b __secondary_start
870 #endif /* CONFIG_GEMINI */
871
872 .globl __secondary_start_mpc86xx
873 __secondary_start_mpc86xx:
874 mfspr r3, SPRN_PIR
875 stw r3, __secondary_hold_acknowledge@l(0)
876 mr r24, r3 /* cpu # */
877 b __secondary_start
878
879 .globl __secondary_start_pmac_0
880 __secondary_start_pmac_0:
881 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
882 li r24,0
883 b 1f
884 li r24,1
885 b 1f
886 li r24,2
887 b 1f
888 li r24,3
889 1:
890 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
891 set to map the 0xf0000000 - 0xffffffff region */
892 mfmsr r0
893 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
894 SYNC
895 mtmsr r0
896 isync
897
898 .globl __secondary_start
899 __secondary_start:
900 /* Copy some CPU settings from CPU 0 */
901 bl __restore_cpu_setup
902
903 lis r3,-KERNELBASE@h
904 mr r4,r24
905 bl call_setup_cpu /* Call setup_cpu for this CPU */
906 #ifdef CONFIG_6xx
907 lis r3,-KERNELBASE@h
908 bl init_idle_6xx
909 #endif /* CONFIG_6xx */
910
911 /* get current_thread_info and current */
912 lis r1,secondary_ti@ha
913 tophys(r1,r1)
914 lwz r1,secondary_ti@l(r1)
915 tophys(r2,r1)
916 lwz r2,TI_TASK(r2)
917
918 /* stack */
919 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
920 li r0,0
921 tophys(r3,r1)
922 stw r0,0(r3)
923
924 /* load up the MMU */
925 bl load_up_mmu
926
927 /* ptr to phys current thread */
928 tophys(r4,r2)
929 addi r4,r4,THREAD /* phys address of our thread_struct */
930 CLR_TOP32(r4)
931 mtspr SPRN_SPRG3,r4
932 li r3,0
933 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
934
935 /* enable MMU and jump to start_secondary */
936 li r4,MSR_KERNEL
937 FIX_SRR1(r4,r5)
938 lis r3,start_secondary@h
939 ori r3,r3,start_secondary@l
940 mtspr SPRN_SRR0,r3
941 mtspr SPRN_SRR1,r4
942 SYNC
943 RFI
944 #endif /* CONFIG_SMP */
945
946 /*
947 * Those generic dummy functions are kept for CPUs not
948 * included in CONFIG_6xx
949 */
950 #if !defined(CONFIG_6xx)
951 _ENTRY(__save_cpu_setup)
952 blr
953 _ENTRY(__restore_cpu_setup)
954 blr
955 #endif /* !defined(CONFIG_6xx) */
956
957
958 /*
959 * Load stuff into the MMU. Intended to be called with
960 * IR=0 and DR=0.
961 */
962 load_up_mmu:
963 sync /* Force all PTE updates to finish */
964 isync
965 tlbia /* Clear all TLB entries */
966 sync /* wait for tlbia/tlbie to finish */
967 TLBSYNC /* ... on all CPUs */
968 /* Load the SDR1 register (hash table base & size) */
969 lis r6,_SDR1@ha
970 tophys(r6,r6)
971 lwz r6,_SDR1@l(r6)
972 mtspr SPRN_SDR1,r6
973 li r0,16 /* load up segment register values */
974 mtctr r0 /* for context 0 */
975 lis r3,0x2000 /* Ku = 1, VSID = 0 */
976 li r4,0
977 3: mtsrin r3,r4
978 addi r3,r3,0x111 /* increment VSID */
979 addis r4,r4,0x1000 /* address of next segment */
980 bdnz 3b
981
982 /* Load the BAT registers with the values set up by MMU_init.
983 MMU_init takes care of whether we're on a 601 or not. */
984 mfpvr r3
985 srwi r3,r3,16
986 cmpwi r3,1
987 lis r3,BATS@ha
988 addi r3,r3,BATS@l
989 tophys(r3,r3)
990 LOAD_BAT(0,r3,r4,r5)
991 LOAD_BAT(1,r3,r4,r5)
992 LOAD_BAT(2,r3,r4,r5)
993 LOAD_BAT(3,r3,r4,r5)
994 BEGIN_MMU_FTR_SECTION
995 LOAD_BAT(4,r3,r4,r5)
996 LOAD_BAT(5,r3,r4,r5)
997 LOAD_BAT(6,r3,r4,r5)
998 LOAD_BAT(7,r3,r4,r5)
999 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1000 blr
1001
1002 /*
1003 * This is where the main kernel code starts.
1004 */
1005 start_here:
1006 /* ptr to current */
1007 lis r2,init_task@h
1008 ori r2,r2,init_task@l
1009 /* Set up for using our exception vectors */
1010 /* ptr to phys current thread */
1011 tophys(r4,r2)
1012 addi r4,r4,THREAD /* init task's THREAD */
1013 CLR_TOP32(r4)
1014 mtspr SPRN_SPRG3,r4
1015 li r3,0
1016 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1017
1018 /* stack */
1019 lis r1,init_thread_union@ha
1020 addi r1,r1,init_thread_union@l
1021 li r0,0
1022 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1023 /*
1024 * Do early platform-specific initialization,
1025 * and set up the MMU.
1026 */
1027 mr r3,r31
1028 mr r4,r30
1029 bl machine_init
1030 bl __save_cpu_setup
1031 bl MMU_init
1032
1033 /*
1034 * Go back to running unmapped so we can load up new values
1035 * for SDR1 (hash table pointer) and the segment registers
1036 * and change to using our exception vectors.
1037 */
1038 lis r4,2f@h
1039 ori r4,r4,2f@l
1040 tophys(r4,r4)
1041 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1042 FIX_SRR1(r3,r5)
1043 mtspr SPRN_SRR0,r4
1044 mtspr SPRN_SRR1,r3
1045 SYNC
1046 RFI
1047 /* Load up the kernel context */
1048 2: bl load_up_mmu
1049
1050 #ifdef CONFIG_BDI_SWITCH
1051 /* Add helper information for the Abatron bdiGDB debugger.
1052 * We do this here because we know the mmu is disabled, and
1053 * will be enabled for real in just a few instructions.
1054 */
1055 lis r5, abatron_pteptrs@h
1056 ori r5, r5, abatron_pteptrs@l
1057 stw r5, 0xf0(r0) /* This much match your Abatron config */
1058 lis r6, swapper_pg_dir@h
1059 ori r6, r6, swapper_pg_dir@l
1060 tophys(r5, r5)
1061 stw r6, 0(r5)
1062 #endif /* CONFIG_BDI_SWITCH */
1063
1064 /* Now turn on the MMU for real! */
1065 li r4,MSR_KERNEL
1066 FIX_SRR1(r4,r5)
1067 lis r3,start_kernel@h
1068 ori r3,r3,start_kernel@l
1069 mtspr SPRN_SRR0,r3
1070 mtspr SPRN_SRR1,r4
1071 SYNC
1072 RFI
1073
1074 /*
1075 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1076 *
1077 * Set up the segment registers for a new context.
1078 */
1079 _ENTRY(switch_mmu_context)
1080 lwz r3,MMCONTEXTID(r4)
1081 cmpwi cr0,r3,0
1082 blt- 4f
1083 mulli r3,r3,897 /* multiply context by skew factor */
1084 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1085 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1086 li r0,NUM_USER_SEGMENTS
1087 mtctr r0
1088
1089 #ifdef CONFIG_BDI_SWITCH
1090 /* Context switch the PTE pointer for the Abatron BDI2000.
1091 * The PGDIR is passed as second argument.
1092 */
1093 lwz r4,MM_PGD(r4)
1094 lis r5, KERNELBASE@h
1095 lwz r5, 0xf0(r5)
1096 stw r4, 0x4(r5)
1097 #endif
1098 li r4,0
1099 isync
1100 3:
1101 mtsrin r3,r4
1102 addi r3,r3,0x111 /* next VSID */
1103 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1104 addis r4,r4,0x1000 /* address of next segment */
1105 bdnz 3b
1106 sync
1107 isync
1108 blr
1109 4: trap
1110 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1111 blr
1112
1113 /*
1114 * An undocumented "feature" of 604e requires that the v bit
1115 * be cleared before changing BAT values.
1116 *
1117 * Also, newer IBM firmware does not clear bat3 and 4 so
1118 * this makes sure it's done.
1119 * -- Cort
1120 */
1121 clear_bats:
1122 li r10,0
1123 mfspr r9,SPRN_PVR
1124 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1125 cmpwi r9, 1
1126 beq 1f
1127
1128 mtspr SPRN_DBAT0U,r10
1129 mtspr SPRN_DBAT0L,r10
1130 mtspr SPRN_DBAT1U,r10
1131 mtspr SPRN_DBAT1L,r10
1132 mtspr SPRN_DBAT2U,r10
1133 mtspr SPRN_DBAT2L,r10
1134 mtspr SPRN_DBAT3U,r10
1135 mtspr SPRN_DBAT3L,r10
1136 1:
1137 mtspr SPRN_IBAT0U,r10
1138 mtspr SPRN_IBAT0L,r10
1139 mtspr SPRN_IBAT1U,r10
1140 mtspr SPRN_IBAT1L,r10
1141 mtspr SPRN_IBAT2U,r10
1142 mtspr SPRN_IBAT2L,r10
1143 mtspr SPRN_IBAT3U,r10
1144 mtspr SPRN_IBAT3L,r10
1145 BEGIN_MMU_FTR_SECTION
1146 /* Here's a tweak: at this point, CPU setup have
1147 * not been called yet, so HIGH_BAT_EN may not be
1148 * set in HID0 for the 745x processors. However, it
1149 * seems that doesn't affect our ability to actually
1150 * write to these SPRs.
1151 */
1152 mtspr SPRN_DBAT4U,r10
1153 mtspr SPRN_DBAT4L,r10
1154 mtspr SPRN_DBAT5U,r10
1155 mtspr SPRN_DBAT5L,r10
1156 mtspr SPRN_DBAT6U,r10
1157 mtspr SPRN_DBAT6L,r10
1158 mtspr SPRN_DBAT7U,r10
1159 mtspr SPRN_DBAT7L,r10
1160 mtspr SPRN_IBAT4U,r10
1161 mtspr SPRN_IBAT4L,r10
1162 mtspr SPRN_IBAT5U,r10
1163 mtspr SPRN_IBAT5L,r10
1164 mtspr SPRN_IBAT6U,r10
1165 mtspr SPRN_IBAT6L,r10
1166 mtspr SPRN_IBAT7U,r10
1167 mtspr SPRN_IBAT7L,r10
1168 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1169 blr
1170
1171 flush_tlbs:
1172 lis r10, 0x40
1173 1: addic. r10, r10, -0x1000
1174 tlbie r10
1175 bgt 1b
1176 sync
1177 blr
1178
1179 mmu_off:
1180 addi r4, r3, __after_mmu_off - _start
1181 mfmsr r3
1182 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1183 beqlr
1184 andc r3,r3,r0
1185 mtspr SPRN_SRR0,r4
1186 mtspr SPRN_SRR1,r3
1187 sync
1188 RFI
1189
1190 /*
1191 * Use the first pair of BAT registers to map the 1st 16MB
1192 * of RAM to PAGE_OFFSET. From this point on we can't safely
1193 * call OF any more.
1194 */
1195 initial_bats:
1196 lis r11,PAGE_OFFSET@h
1197 mfspr r9,SPRN_PVR
1198 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1199 cmpwi 0,r9,1
1200 bne 4f
1201 ori r11,r11,4 /* set up BAT registers for 601 */
1202 li r8,0x7f /* valid, block length = 8MB */
1203 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1204 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1205 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1206 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1207 mtspr SPRN_IBAT1U,r9
1208 mtspr SPRN_IBAT1L,r10
1209 isync
1210 blr
1211
1212 4: tophys(r8,r11)
1213 #ifdef CONFIG_SMP
1214 ori r8,r8,0x12 /* R/W access, M=1 */
1215 #else
1216 ori r8,r8,2 /* R/W access */
1217 #endif /* CONFIG_SMP */
1218 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1219
1220 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1221 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1222 mtspr SPRN_IBAT0L,r8
1223 mtspr SPRN_IBAT0U,r11
1224 isync
1225 blr
1226
1227
1228 #ifdef CONFIG_BOOTX_TEXT
1229 setup_disp_bat:
1230 /*
1231 * setup the display bat prepared for us in prom.c
1232 */
1233 mflr r8
1234 bl reloc_offset
1235 mtlr r8
1236 addis r8,r3,disp_BAT@ha
1237 addi r8,r8,disp_BAT@l
1238 cmpwi cr0,r8,0
1239 beqlr
1240 lwz r11,0(r8)
1241 lwz r8,4(r8)
1242 mfspr r9,SPRN_PVR
1243 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1244 cmpwi 0,r9,1
1245 beq 1f
1246 mtspr SPRN_DBAT3L,r8
1247 mtspr SPRN_DBAT3U,r11
1248 blr
1249 1: mtspr SPRN_IBAT3L,r8
1250 mtspr SPRN_IBAT3U,r11
1251 blr
1252 #endif /* CONFIG_BOOTX_TEXT */
1253
1254 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1255 setup_cpm_bat:
1256 lis r8, 0xf000
1257 ori r8, r8, 0x002a
1258 mtspr SPRN_DBAT1L, r8
1259
1260 lis r11, 0xf000
1261 ori r11, r11, (BL_1M << 2) | 2
1262 mtspr SPRN_DBAT1U, r11
1263
1264 blr
1265 #endif
1266
1267 #ifdef CONFIG_8260
1268 /* Jump into the system reset for the rom.
1269 * We first disable the MMU, and then jump to the ROM reset address.
1270 *
1271 * r3 is the board info structure, r4 is the location for starting.
1272 * I use this for building a small kernel that can load other kernels,
1273 * rather than trying to write or rely on a rom monitor that can tftp load.
1274 */
1275 .globl m8260_gorom
1276 m8260_gorom:
1277 mfmsr r0
1278 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1279 sync
1280 mtmsr r0
1281 sync
1282 mfspr r11, SPRN_HID0
1283 lis r10, 0
1284 ori r10,r10,HID0_ICE|HID0_DCE
1285 andc r11, r11, r10
1286 mtspr SPRN_HID0, r11
1287 isync
1288 li r5, MSR_ME|MSR_RI
1289 lis r6,2f@h
1290 addis r6,r6,-KERNELBASE@h
1291 ori r6,r6,2f@l
1292 mtspr SPRN_SRR0,r6
1293 mtspr SPRN_SRR1,r5
1294 isync
1295 sync
1296 rfi
1297 2:
1298 mtlr r4
1299 blr
1300 #endif
1301
1302
1303 /*
1304 * We put a few things here that have to be page-aligned.
1305 * This stuff goes at the beginning of the data segment,
1306 * which is page-aligned.
1307 */
1308 .data
1309 .globl sdata
1310 sdata:
1311 .globl empty_zero_page
1312 empty_zero_page:
1313 .space 4096
1314
1315 .globl swapper_pg_dir
1316 swapper_pg_dir:
1317 .space PGD_TABLE_SIZE
1318
1319 .globl intercept_table
1320 intercept_table:
1321 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1322 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1323 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1324 .long 0, 0, 0, 0, 0, 0, 0, 0
1325 .long 0, 0, 0, 0, 0, 0, 0, 0
1326 .long 0, 0, 0, 0, 0, 0, 0, 0
1327
1328 /* Room for two PTE pointers, usually the kernel and current user pointers
1329 * to their respective root page table.
1330 */
1331 abatron_pteptrs:
1332 .space 8
Linux kernel - Deliverables
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